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[HAL]

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- Move the rest from halamd64 to halx86

svn path=/branches/ros-amd64-bringup/; revision=44835
This commit is contained in:
Timo Kreuzer 2009-12-31 21:23:01 +00:00
parent 2a0c1bf649
commit 5ec7192b66
17 changed files with 14 additions and 559 deletions
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5
reactos/hal/hal.rbuild
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@ -15,9 +15,4 @@
<xi:include href="halarm/directory.rbuild" />
</directory>
</if>
<if property="ARCH" value="amd64">
<directory name="halamd64">
<xi:include href="halamd64/directory.rbuild" />
</directory>
</if>
</group>

7
reactos/hal/halamd64/directory.rbuild
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@ -1,7 +0,0 @@
<?xml version="1.0"?>
<!DOCTYPE group SYSTEM "../../tools/rbuild/project.dtd">
<group xmlns:xi="http://www.w3.org/2001/XInclude">
<directory name="generic">
<xi:include href="generic/generic.rbuild" />
</directory>
</group>

16
reactos/hal/halamd64/generic/generic.rbuild
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@ -1,16 +0,0 @@
<?xml version="1.0"?>
<!DOCTYPE module SYSTEM "../../../tools/rbuild/project.dtd">
<group>
<module name="hal_generic_amd64" type="objectlibrary">
<include base="hal_generic_amd64">../include</include>
<include base="ntoskrnl">include</include>
<define name="_DISABLE_TIDENTS" />
<define name="_NTHAL_" />
<file>halinit.c</file>
<file>misc.c</file>
<file>mps.S</file>
<file>usage.c</file>
<file>pic.c</file>
<pch>../include/hal.h</pch>
</module>
</group>

296
reactos/hal/halamd64/include/bus.h
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@ -1,296 +0,0 @@
#ifndef __INTERNAL_HAL_BUS_H
#define __INTERNAL_HAL_BUS_H
//
// Helper Macros
//
#define PASTE2(x,y) x ## y
#define POINTER_TO_(x) PASTE2(P,x)
#define READ_FROM(x) PASTE2(READ_PORT_, x)
#define WRITE_TO(x) PASTE2(WRITE_PORT_, x)
//
// Declares a PCI Register Read/Write Routine
//
#define TYPE_DEFINE(x, y) \
ULONG \
NTAPI \
x( \
IN PPCIPBUSDATA BusData, \
IN y PciCfg, \
IN PUCHAR Buffer, \
IN ULONG Offset \
)
#define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
#define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
//
// Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
//
#define TYPE1_START(x, y) \
TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS) \
{ \
ULONG i = Offset % sizeof(ULONG); \
PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG); \
WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
#define TYPE1_END(y) \
return sizeof(y); }
#define TYPE2_END TYPE1_END
//
// PCI Register Read Type 1 Routine
//
#define TYPE1_READ(x, y) \
TYPE1_START(x, y) \
*((POINTER_TO_(y))Buffer) = \
READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \
TYPE1_END(y)
//
// PCI Register Write Type 1 Routine
//
#define TYPE1_WRITE(x, y) \
TYPE1_START(x, y) \
WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \
*((POINTER_TO_(y))Buffer)); \
TYPE1_END(y)
//
// Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
//
#define TYPE2_START(x, y) \
TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS) \
{ \
PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
//
// PCI Register Read Type 2 Routine
//
#define TYPE2_READ(x, y) \
TYPE2_START(x, y) \
*((POINTER_TO_(y))Buffer) = \
READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \
TYPE2_END(y)
//
// PCI Register Write Type 2 Routine
//
#define TYPE2_WRITE(x, y) \
TYPE2_START(x, y) \
WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \
*((POINTER_TO_(y))Buffer)); \
TYPE2_END(y)
typedef struct _PCIPBUSDATA
{
PCIBUSDATA CommonData;
union
{
struct
{
PULONG Address;
ULONG Data;
} Type1;
struct
{
PUCHAR CSE;
PUCHAR Forward;
ULONG Base;
} Type2;
} Config;
ULONG MaxDevice;
} PCIPBUSDATA, *PPCIPBUSDATA;
typedef ULONG
(NTAPI *FncConfigIO)(
IN PPCIPBUSDATA BusData,
IN PVOID State,
IN PUCHAR Buffer,
IN ULONG Offset
);
typedef VOID
(NTAPI *FncSync)(
IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql,
IN PVOID State
);
typedef VOID
(NTAPI *FncReleaseSync)(
IN PBUS_HANDLER BusHandler,
IN KIRQL Irql
);
typedef struct _PCI_CONFIG_HANDLER
{
FncSync Synchronize;
FncReleaseSync ReleaseSynchronzation;
FncConfigIO ConfigRead[3];
FncConfigIO ConfigWrite[3];
} PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
typedef struct _PCI_REGISTRY_INFO_INTERNAL
{
UCHAR MajorRevision;
UCHAR MinorRevision;
UCHAR NoBuses;
UCHAR HardwareMechanism;
ULONG ElementCount;
PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
} PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
/* FUNCTIONS *****************************************************************/
VOID
NTAPI
HalpPCISynchronizeType1(
IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql,
IN PPCI_TYPE1_CFG_BITS PciCfg
);
VOID
NTAPI
HalpPCIReleaseSynchronzationType1(
IN PBUS_HANDLER BusHandler,
IN KIRQL Irql
);
VOID
NTAPI
HalpPCISynchronizeType2(
IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql,
IN PPCI_TYPE2_ADDRESS_BITS PciCfg
);
VOID
NTAPI
HalpPCIReleaseSynchronizationType2(
IN PBUS_HANDLER BusHandler,
IN KIRQL Irql
);
TYPE1_DEFINE(HalpPCIReadUcharType1);
TYPE1_DEFINE(HalpPCIReadUshortType1);
TYPE1_DEFINE(HalpPCIReadUlongType1);
TYPE2_DEFINE(HalpPCIReadUcharType2);
TYPE2_DEFINE(HalpPCIReadUshortType2);
TYPE2_DEFINE(HalpPCIReadUlongType2);
TYPE1_DEFINE(HalpPCIWriteUcharType1);
TYPE1_DEFINE(HalpPCIWriteUshortType1);
TYPE1_DEFINE(HalpPCIWriteUlongType1);
TYPE2_DEFINE(HalpPCIWriteUcharType2);
TYPE2_DEFINE(HalpPCIWriteUshortType2);
TYPE2_DEFINE(HalpPCIWriteUlongType2);
BOOLEAN
NTAPI
HalpValidPCISlot(
IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot
);
VOID
NTAPI
HalpReadPCIConfig(
IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PVOID Buffer,
IN ULONG Offset,
IN ULONG Length
);
VOID
NTAPI
HalpWritePCIConfig(
IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PVOID Buffer,
IN ULONG Offset,
IN ULONG Length
);
ULONG
NTAPI
HalpGetSystemInterruptVector(
ULONG BusNumber,
ULONG BusInterruptLevel,
ULONG BusInterruptVector,
PKIRQL Irql,
PKAFFINITY Affinity
);
ULONG
NTAPI
HalpGetCmosData(
IN ULONG BusNumber,
IN ULONG SlotNumber,
IN PVOID Buffer,
IN ULONG Length
);
ULONG
NTAPI
HalpSetCmosData(
IN ULONG BusNumber,
IN ULONG SlotNumber,
IN PVOID Buffer,
IN ULONG Length
);
ULONG
NTAPI
HalpGetPCIData(
IN PBUS_HANDLER BusHandler,
IN PBUS_HANDLER RootBusHandler,
IN PCI_SLOT_NUMBER SlotNumber,
IN PUCHAR Buffer,
IN ULONG Offset,
IN ULONG Length
);
ULONG
NTAPI
HalpSetPCIData(
IN PBUS_HANDLER BusHandler,
IN PBUS_HANDLER RootBusHandler,
IN PCI_SLOT_NUMBER SlotNumber,
IN PUCHAR Buffer,
IN ULONG Offset,
IN ULONG Length
);
NTSTATUS
NTAPI
HalpAssignPCISlotResources(
IN PBUS_HANDLER BusHandler,
IN PBUS_HANDLER RootHandler,
IN PUNICODE_STRING RegistryPath,
IN PUNICODE_STRING DriverClassName OPTIONAL,
IN PDRIVER_OBJECT DriverObject,
IN PDEVICE_OBJECT DeviceObject OPTIONAL,
IN ULONG Slot,
IN OUT PCM_RESOURCE_LIST *pAllocatedResources
);
VOID
NTAPI
HalpInitializePciBus(
VOID
);
extern ULONG HalpBusType;
extern BOOLEAN HalpPCIConfigInitialized;
extern BUS_HANDLER HalpFakePciBusHandler;
extern ULONG HalpMinPciBus, HalpMaxPciBus;
#endif /* __INTERNAL_HAL_BUS_H */
/* EOF */

52
reactos/hal/halamd64/include/hal.h
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@ -1,52 +0,0 @@
/*
* COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS Hardware Abstraction Layer
* FILE: hal/halx86/include/hal.h
* PURPOSE: HAL Header
* PROGRAMMER: Alex Ionescu (alex@relsoft.net)
*/
/* INCLUDES ******************************************************************/
/* C Headers */
#include <stdio.h>
/* WDK HAL Compilation hack */
#ifdef _MSC_VER
#include <excpt.h>
#include <ntdef.h>
#undef _NTHAL_
#undef DECLSPEC_IMPORT
#define DECLSPEC_IMPORT
#define __declspec(dllimport)
#endif
/* IFS/DDK/NDK Headers */
#include <ntifs.h>
#include <bugcodes.h>
#include <ntdddisk.h>
#include <arc/arc.h>
#include <iotypes.h>
#include <kefuncs.h>
#include <halfuncs.h>
#include <iofuncs.h>
#include <ldrtypes.h>
#include <obfuncs.h>
/* Internal kernel headers */
#include "internal/pci.h"
#include "internal/i386/intrin_i.h"
/* Internal HAL Headers */
//#include "apic.h"
#include "bus.h"
//#include "halirq.h"
//#include "haldma.h"
#include "halp.h"
//#include "mps.h"
//#include "ioapic.h"
/* Helper Header */
#include <reactos/helper.h>
/* EOF */

176
reactos/hal/halamd64/include/halp.h
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@ -1,176 +0,0 @@
/*
*
*/
#ifndef __INTERNAL_HAL_HAL_H
#define __INTERNAL_HAL_HAL_H
#define HAL_APC_REQUEST 0
#define HAL_DPC_REQUEST 1
/* CMOS Registers and Ports */
#define CMOS_CONTROL_PORT (PUCHAR)0x70
#define CMOS_DATA_PORT (PUCHAR)0x71
#define RTC_REGISTER_A 0x0A
#define RTC_REGISTER_B 0x0B
#define RTC_REG_A_UIP 0x80
#define RTC_REGISTER_CENTURY 0x32
/* Timer Registers and Ports */
#define TIMER_CONTROL_PORT 0x43
#define TIMER_DATA_PORT0 0x40
#define TIMER_SC0 0
#define TIMER_BOTH 0x30
#define TIMER_MD2 0x4
/* Conversion functions */
#define BCD_INT(bcd) \
(((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
#define INT_BCD(int) \
(UCHAR)(((int / 10) << 4) + (int % 10))
/* adapter.c */
PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
/* bus.c */
VOID NTAPI HalpInitNonBusHandler (VOID);
/* irql.c */
VOID NTAPI HalpInitPICs(VOID);
/* udelay.c */
VOID NTAPI HalpInitializeClock(VOID);
/* pci.c */
VOID HalpInitPciBus (VOID);
/* dma.c */
VOID HalpInitDma (VOID);
/* Non-generic initialization */
VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
VOID HalpInitPhase1(VOID);
VOID NTAPI HalpClockInterrupt(VOID);
//
// KD Support
//
VOID
NTAPI
HalpCheckPowerButton(
VOID
);
VOID
NTAPI
HalpRegisterKdSupportFunctions(
VOID
);
NTSTATUS
NTAPI
HalpSetupPciDeviceForDebugging(
IN PVOID LoaderBlock,
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
);
NTSTATUS
NTAPI
HalpReleasePciDeviceForDebugging(
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
);
//
// Memory routines
//
PVOID
NTAPI
HalpMapPhysicalMemory64(
IN PHYSICAL_ADDRESS PhysicalAddress,
IN ULONG NumberPage
);
VOID
NTAPI
HalpUnmapVirtualAddress(
IN PVOID VirtualAddress,
IN ULONG NumberPages
);
/* sysinfo.c */
NTSTATUS
NTAPI
HaliQuerySystemInformation(
IN HAL_QUERY_INFORMATION_CLASS InformationClass,
IN ULONG BufferSize,
IN OUT PVOID Buffer,
OUT PULONG ReturnedLength
);
NTSTATUS
NTAPI
HaliSetSystemInformation(
IN HAL_SET_INFORMATION_CLASS InformationClass,
IN ULONG BufferSize,
IN OUT PVOID Buffer
);
//
// BIOS Routines
//
BOOLEAN
NTAPI
HalpBiosDisplayReset(
VOID
);
ULONG
NTAPI
HalpBorrowTss(
VOID
);
ULONG
NTAPI
HalpReturnTss(
ULONG SavedTss
);
VOID
NTAPI
HalpBiosCall(
VOID
);
VOID
NTAPI
HalpTrap0D(
VOID
);
VOID
NTAPI
HalpTrap06(
VOID
);
PDMA_ADAPTER
NTAPI
HalpGetDmaAdapter(
IN PVOID Context,
IN PDEVICE_DESCRIPTION DeviceDescription,
OUT PULONG NumberOfMapRegisters);
VOID HaliInitBSP(VOID);
VOID HaliStartApplicationProcessor(ULONG Cpu, ULONG Stack);
VOID NTAPI HalpInitIdtEntry(PKIDTENTRY64 Idt, PVOID Address);
VOID NTAPI HalpSetInterruptGate(ULONG Index, PVOID Address);
VOID NTAPI HalpInitCpuInterruptHandling(ULONG Cpu);
extern PVOID HalpRealModeStart;
extern PVOID HalpRealModeEnd;
extern KSPIN_LOCK HalpSystemHardwareLock;
#endif /* __INTERNAL_HAL_HAL_H */

0
reactos/hal/halamd64/generic/halinit.c → reactos/hal/halx86/generic/amd64/halinit.c
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0
reactos/hal/halamd64/generic/misc.c → reactos/hal/halx86/generic/amd64/misc.c
View file

0
reactos/hal/halamd64/generic/pic.c → reactos/hal/halx86/generic/amd64/pic.c
View file

0
reactos/hal/halamd64/generic/usage.c → reactos/hal/halx86/generic/amd64/usage.c
View file

4
reactos/hal/halx86/hal_generic.rbuild
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@ -38,8 +38,12 @@
</if>
<if property="ARCH" value="amd64">
<directory name="amd64">
<file>halinit.c</file>
<file>irq.s</file>
<file>misc.c</file>
<file>pic.c</file>
<file>systimer.S</file>
<file>usage.c</file>
</directory>
</if>
</directory>

9
reactos/hal/halx86/halamd64.rbuild
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@ -7,7 +7,6 @@
<include base="ntoskrnl">include</include>
<define name="_DISABLE_TIDENTS" />
<define name="_NTHAL_" />
<library>hal_generic_amd64</library>
<library>hal_generic</library>
<library>hal_generic_up</library>
<library>ntoskrnl</library>
@ -17,7 +16,9 @@
<file>halup.rc</file>
</directory>
<!--directory name="mp">
<file>apic.c</file>
</directory -->
<directory name="mp">
<directory name="amd64">
<file>mps.S</file>
</directory>
</directory>
</module>

8
reactos/hal/halx86/halmps.rbuild
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@ -16,12 +16,14 @@
<file>ioapic.c</file>
<file>ipi_mp.c</file>
<file>mpconfig.c</file>
<file>mps.S</file>
<file>mpsboot.asm</file>
<file>mpsirql.c</file>
<file>processor_mp.c</file>
<file>spinlock.c</file>
<file>halmp.rc</file>
<directory name="i386">
<file>mps.S</file>
<file>mpsboot.asm</file>
<file>spinlock.c</file>
</directory>
</directory>
</module>
</group>

0
reactos/hal/halamd64/generic/mps.S → reactos/hal/halx86/mp/amd64/mps.S
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0
reactos/hal/halx86/mp/mps.S → reactos/hal/halx86/mp/i386/mps.S
View file

0
reactos/hal/halx86/mp/mpsboot.asm → reactos/hal/halx86/mp/i386/mpsboot.asm
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0
reactos/hal/halx86/mp/spinlock.c → reactos/hal/halx86/mp/i386/spinlock.c
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