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- Move more stuff to wdm.h

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- Add _PCI_COMMON_HEADER
- Improve _PCI_COMMON_CONFIG
- Enable msc extensions

svn path=/branches/header-work/; revision=45750
This commit is contained in:
Amine Khaldi 2010-03-01 21:24:36 +00:00
parent 706a8e639a
commit 5bf6e1937a
3 changed files with 85 additions and 74 deletions
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1
ReactOS-i386.rbuild
View file

@ -24,6 +24,7 @@
<compilerflag>-ftracer</compilerflag>
<compilerflag>-momit-leaf-frame-pointer</compilerflag>
</if>
<compilerflag>-fms-extensions</compilerflag>
<compilerflag>-mpreferred-stack-boundary=2</compilerflag>
<compilerflag compiler="midl">-m32 --win32</compilerflag>
<compilerflag compiler="cc,cxx">-gstabs+</compilerflag>

84
include/ddk/wdm.h
View file

@ -2598,8 +2598,92 @@ typedef struct _SHARE_ACCESS {
ULONG SharedDelete;
} SHARE_ACCESS, *PSHARE_ACCESS;
typedef struct _PCI_COMMON_HEADER {
USHORT VendorID;
USHORT DeviceID;
USHORT Command;
USHORT Status;
UCHAR RevisionID;
UCHAR ProgIf;
UCHAR SubClass;
UCHAR BaseClass;
UCHAR CacheLineSize;
UCHAR LatencyTimer;
UCHAR HeaderType;
UCHAR BIST;
union {
struct _PCI_HEADER_TYPE_0 {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG CIS;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG ROMBaseAddress;
UCHAR CapabilitiesPtr;
UCHAR Reserved1[3];
ULONG Reserved2;
UCHAR InterruptLine;
UCHAR InterruptPin;
UCHAR MinimumGrant;
UCHAR MaximumLatency;
} type0;
struct _PCI_HEADER_TYPE_1 {
ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
UCHAR PrimaryBus;
UCHAR SecondaryBus;
UCHAR SubordinateBus;
UCHAR SecondaryLatency;
UCHAR IOBase;
UCHAR IOLimit;
USHORT SecondaryStatus;
USHORT MemoryBase;
USHORT MemoryLimit;
USHORT PrefetchBase;
USHORT PrefetchLimit;
ULONG PrefetchBaseUpper32;
ULONG PrefetchLimitUpper32;
USHORT IOBaseUpper16;
USHORT IOLimitUpper16;
UCHAR CapabilitiesPtr;
UCHAR Reserved1[3];
ULONG ROMBaseAddress;
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
} type1;
struct _PCI_HEADER_TYPE_2 {
ULONG SocketRegistersBaseAddress;
UCHAR CapabilitiesPtr;
UCHAR Reserved;
USHORT SecondaryStatus;
UCHAR PrimaryBus;
UCHAR SecondaryBus;
UCHAR SubordinateBus;
UCHAR SecondaryLatency;
struct {
ULONG Base;
ULONG Limit;
} Range[PCI_TYPE2_ADDRESSES-1];
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
} type2;
} u;
} PCI_COMMON_HEADER, *PPCI_COMMON_HEADER;
#ifdef __cplusplus
typedef struct _PCI_COMMON_CONFIG : PCI_COMMON_HEADER {
UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
#else
typedef struct _PCI_COMMON_CONFIG {
PCI_COMMON_HEADER DUMMYSTRUCTNAME;
UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
#endif
typedef struct _PCI_SLOT_NUMBER {
union {

74
include/ddk/winddk.h
View file

@ -1124,80 +1124,6 @@ typedef struct _KEY_USER_FLAGS_INFORMATION {
ULONG UserFlags;
} KEY_USER_FLAGS_INFORMATION, *PKEY_USER_FLAGS_INFORMATION;
typedef struct _PCI_COMMON_CONFIG {
USHORT VendorID;
USHORT DeviceID;
USHORT Command;
USHORT Status;
UCHAR RevisionID;
UCHAR ProgIf;
UCHAR SubClass;
UCHAR BaseClass;
UCHAR CacheLineSize;
UCHAR LatencyTimer;
UCHAR HeaderType;
UCHAR BIST;
union {
struct _PCI_HEADER_TYPE_0 {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG CIS;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG ROMBaseAddress;
UCHAR CapabilitiesPtr;
UCHAR Reserved1[3];
ULONG Reserved2;
UCHAR InterruptLine;
UCHAR InterruptPin;
UCHAR MinimumGrant;
UCHAR MaximumLatency;
} type0;
struct _PCI_HEADER_TYPE_1 {
ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
UCHAR PrimaryBus;
UCHAR SecondaryBus;
UCHAR SubordinateBus;
UCHAR SecondaryLatency;
UCHAR IOBase;
UCHAR IOLimit;
USHORT SecondaryStatus;
USHORT MemoryBase;
USHORT MemoryLimit;
USHORT PrefetchBase;
USHORT PrefetchLimit;
ULONG PrefetchBaseUpper32;
ULONG PrefetchLimitUpper32;
USHORT IOBaseUpper16;
USHORT IOLimitUpper16;
UCHAR CapabilitiesPtr;
UCHAR Reserved1[3];
ULONG ROMBaseAddress;
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
} type1;
struct _PCI_HEADER_TYPE_2 {
ULONG SocketRegistersBaseAddress;
UCHAR CapabilitiesPtr;
UCHAR Reserved;
USHORT SecondaryStatus;
UCHAR PrimaryBus;
UCHAR SecondaryBus;
UCHAR SubordinateBus;
UCHAR SecondaryLatency;
struct {
ULONG Base;
ULONG Limit;
} Range[PCI_TYPE2_ADDRESSES - 1];
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
} type2;
} u;
UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
#define PCI_ADDRESS_MEMORY_SPACE 0x00000000
typedef struct _OSVERSIONINFOA {