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Add a generic implementation of InterlockedBitTestAndSet/InterlockedBitTestAndReset/BitScanReverse
svn path=/trunk/; revision=28807
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@ -4,6 +4,9 @@
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#pragma GCC system_header
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#endif
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#ifdef __GNUC__
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#include "intrin.h"
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#endif
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/* translate GCC target defines to MS equivalents. Keep this synchronized
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with windows.h. */
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@ -2341,7 +2344,7 @@ typedef struct _CONTEXT {
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#endif
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} CONTEXT;
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#elif defined(MIPS)
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#elif defined(_MIPS_)
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/* The following flags control the contents of the CONTEXT structure. */
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@ -4039,28 +4042,32 @@ typedef struct _OBJECT_TYPE_LIST {
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#if defined(__GNUC__)
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#ifdef _M_IX86
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#if defined(_M_IX86)
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static __inline__ PVOID GetCurrentFiber(void)
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{
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void* ret;
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__asm__ __volatile__ (
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"movl %%fs:0x10,%0"
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: "=r" (ret) /* allow use of reg eax,ebx,ecx,edx,esi,edi */
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);
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"movl %%fs:0x10,%0"
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: "=r" (ret) /* allow use of reg eax,ebx,ecx,edx,esi,edi */
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);
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return ret;
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}
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#else
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#if defined(_M_PPC)
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static __inline__ __attribute__((always_inline)) unsigned long __readfsdword_winnt(const unsigned long Offset)
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{
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unsigned long result;
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__asm__("\tadd 7,13,%1\n"
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"\tlwz %0,0(7)\n"
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: "=r" (result)
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: "r" (Offset)
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: "r7");
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"\tlwz %0,0(7)\n"
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: "=r" (result)
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: "r" (Offset)
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: "r7");
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return result;
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}
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#else
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#error Unknown architecture
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#endif
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static __inline__ PVOID GetCurrentFiber(void)
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{
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return __readfsdword_winnt(0x10);
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@ -4147,78 +4154,36 @@ static __inline__ BOOLEAN
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InterlockedBitTestAndSet(IN LONG volatile *Base,
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IN LONG Bit)
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{
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#if defined(_M_IX86)
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LONG OldBit;
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#ifdef _M_IX86
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__asm__ __volatile__("lock "
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"btsl %2,%1\n\t"
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"sbbl %0,%0\n\t"
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:"=r" (OldBit),"=m" (*Base)
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:"Ir" (Bit)
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: "memory");
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#elif defined(_M_PPC)
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LONG scratch = 0;
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Bit = 1 << Bit;
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/* %0 - OldBit
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* %1 - Bit
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* %2 - scratch
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* %3 - Base
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*/
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__asm__ __volatile__(
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"sync\n"
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"0:\n\t"
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"lwarx %2,0,%3\n\t"
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"mr %0,%2\n\t"
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"or %2,%1,%2\n\t"
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"stwcx. %2,0,%3\n\t"
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"bne- 0b\n\t" :
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"=r" (OldBit) :
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"r" (Bit),
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"r" (scratch),
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"r" (Base)
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);
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#endif
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:"=r" (OldBit),"=m" (*Base)
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:"Ir" (Bit)
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: "memory");
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return OldBit;
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#else
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return (_InterlockedOr(Base, 1 << Bit) >> Bit) & 1;
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#endif
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}
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static __inline__ BOOLEAN
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InterlockedBitTestAndReset(IN LONG volatile *Base,
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IN LONG Bit)
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IN LONG Bit)
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{
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#if defined(_M_IX86)
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LONG OldBit;
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#ifdef _M_IX86
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__asm__ __volatile__("lock "
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"btrl %2,%1\n\t"
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"sbbl %0,%0\n\t"
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:"=r" (OldBit),"=m" (*Base)
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:"Ir" (Bit)
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: "memory");
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#elif defined(_M_PPC)
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LONG scratch = 0;
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Bit = ~(1 << Bit);
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/* %0 - OldBit
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* %1 - Bit
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* %2 - scratch
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* %3 - Base
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*/
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__asm__ __volatile__(
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"sync\n"
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"0:\n\t"
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"lwarx %2,0,%3\n\t"
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"mr %0,%2\n\t"
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"and %2,%1,%2\n\t"
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"stwcx. %2,0,%3\n\t"
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"bne- 0b\n\t" :
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"=r" (OldBit) :
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"r" (Bit),
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"r" (scratch),
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"r" (Base)
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);
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#endif
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:"=r" (OldBit),"=m" (*Base)
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:"Ir" (Bit)
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: "memory");
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return OldBit;
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#else
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return (_InterlockedAnd(Base, ~(1 << Bit)) >> Bit) & 1;
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#endif
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}
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static __inline__ BOOLEAN
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@ -4226,14 +4191,14 @@ BitScanReverse(OUT ULONG *Index,
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IN ULONG Mask)
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{
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BOOLEAN BitPosition = 0;
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#ifdef _M_IX86
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#if defined(_M_IX86)
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__asm__ __volatile__("bsrl %2,%0\n\t"
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"setnz %1\n\t"
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:"=&r" (*Index), "=r" (BitPosition)
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:"rm" (Mask)
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:"memory");
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:"=&r" (*Index), "=r" (BitPosition)
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:"rm" (Mask)
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:"memory");
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return BitPosition;
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#elif defined(_M_PPC)
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#else
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/* Slow implementation for now */
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for( *Index = 31; *Index; *Index-- ) {
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if( (1<<*Index) & Mask ) {
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@ -4247,10 +4212,14 @@ BitScanReverse(OUT ULONG *Index,
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#endif
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#ifdef _M_IX86
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#if defined(_M_IX86)
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#define YieldProcessor() __asm__ __volatile__("pause");
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#elif defined(_M_PPC)
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#define YieldProcessor() __asm__ __volatile__("nop");
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#elif defined(_M_MIPS)
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#define YieldProcessor() __asm__ __volatile__("nop");
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#else
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#error Unknown architecture
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#endif
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#if defined(_AMD64_)
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