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This is part of the big 'ReactOS under MSVC6' project. Main work on converting ROS to be able to be compiled under MSVC6 was done by Mark Nordell.

Browse source 
Work done by me - incorporating all this stuff into the newest CVS tree. So blame me if I did something wrong during tamlin -> new CVS tree merging :-)
It's HAL turn now.

svn path=/trunk/; revision=7301
This commit is contained in:
Aleksey Bragin 2003-12-28 22:39:06 +00:00
parent 585b1fea42
commit 5a6b27edc4
20 changed files with 498 additions and 148 deletions
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24
reactos/hal/halx86/adapter.c
View file

@ -1,4 +1,4 @@
/* $Id: adapter.c,v 1.8 2003/10/31 01:08:00 gdalsnes Exp $ /* $Id: adapter.c,v 1.9 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -286,10 +286,14 @@ IoMapTransfer (
* - If the controller supports scatter/gather, the copyover should not happen * - If the controller supports scatter/gather, the copyover should not happen
*/ */
{ {
PHYSICAL_ADDRESS Address; PHYSICAL_ADDRESS Address;
#if defined(__GNUC__)
Address.QuadPart = 0ULL;
/* Isa System (slave) DMA? */ #else
Address.QuadPart = 0;
#endif
/* Isa System (slave) DMA? */
if (AdapterObject && AdapterObject->InterfaceType == Isa && !AdapterObject->Master) if (AdapterObject && AdapterObject->InterfaceType == Isa && !AdapterObject->Master)
{ {
#if 0 #if 0
@ -309,18 +313,18 @@ IoMapTransfer (
if( WriteToDevice ) if( WriteToDevice )
{ {
memcpy(MapRegisterBase, memcpy(MapRegisterBase,
MmGetSystemAddressForMdl(Mdl) + ((ULONG)CurrentVa - (ULONG)MmGetMdlVirtualAddress(Mdl)), (char*)MmGetSystemAddressForMdl(Mdl) + ((ULONG)CurrentVa - (ULONG)MmGetMdlVirtualAddress(Mdl)),
*Length ); *Length );
} }
// program up the dma controller, and return // program up the dma controller, and return
Address = MmGetPhysicalAddress( MapRegisterBase ); Address = MmGetPhysicalAddress( MapRegisterBase );
// port 0xA is the dma mask register, or a 0x10 on to the channel number to mask it // port 0xA is the dma mask register, or a 0x10 on to the channel number to mask it
WRITE_PORT_UCHAR( (PVOID)0x0A, AdapterObject->Channel | 0x10 ); WRITE_PORT_UCHAR( (PVOID)0x0A, (UCHAR)(AdapterObject->Channel | 0x10));
// write zero to the reset register // write zero to the reset register
WRITE_PORT_UCHAR( (PVOID)0x0C, 0 ); WRITE_PORT_UCHAR( (PVOID)0x0C, 0 );
// mode register, or channel with 0x4 for write memory, 0x8 for read memory, 0x10 for non auto initialize // mode register, or channel with 0x4 for write memory, 0x8 for read memory, 0x10 for non auto initialize
WRITE_PORT_UCHAR( (PVOID)0x0B, AdapterObject->Channel | ( WriteToDevice ? 0x8 : 0x4 ) ); WRITE_PORT_UCHAR( (PVOID)0x0B, (UCHAR)(AdapterObject->Channel | ( WriteToDevice ? 0x8 : 0x4 )) );
// set the 64k page register for the channel // set the 64k page register for the channel
WRITE_PORT_UCHAR( AdapterObject->PagePort, (UCHAR)(((ULONG)Address.QuadPart)>>16) ); WRITE_PORT_UCHAR( AdapterObject->PagePort, (UCHAR)(((ULONG)Address.QuadPart)>>16) );
// low, then high address byte, which is always 0 for us, because we have a 64k alligned address // low, then high address byte, which is always 0 for us, because we have a 64k alligned address
@ -330,7 +334,7 @@ IoMapTransfer (
WRITE_PORT_UCHAR( AdapterObject->CountPort, (UCHAR)(*Length - 1) ); WRITE_PORT_UCHAR( AdapterObject->CountPort, (UCHAR)(*Length - 1) );
WRITE_PORT_UCHAR( AdapterObject->CountPort, (UCHAR)((*Length - 1)>>8) ); WRITE_PORT_UCHAR( AdapterObject->CountPort, (UCHAR)((*Length - 1)>>8) );
// unmask the channel to let it rip // unmask the channel to let it rip
WRITE_PORT_UCHAR( (PVOID)0x0A, AdapterObject->Channel ); WRITE_PORT_UCHAR( (PVOID)0x0A, (UCHAR)AdapterObject->Channel );
/* /*
NOTE: Return value should be ignored when doing System DMA. NOTE: Return value should be ignored when doing System DMA.
@ -408,7 +412,7 @@ IoMapTransfer (
if( WriteToDevice ) if( WriteToDevice )
{ {
memcpy(MapRegisterBase, memcpy(MapRegisterBase,
MmGetSystemAddressForMdl(Mdl) + ((ULONG)CurrentVa - (ULONG)MmGetMdlVirtualAddress(Mdl)), (char*)MmGetSystemAddressForMdl(Mdl) + ((ULONG)CurrentVa - (ULONG)MmGetMdlVirtualAddress(Mdl)),
*Length ); *Length );
} }

23
reactos/hal/halx86/beep.c
View file

@ -41,12 +41,19 @@ HalMakeBeep (
UCHAR b; UCHAR b;
/* save flags and disable interrupts */ /* save flags and disable interrupts */
#if defined(__GNUC__)
__asm__("pushf\n\t" \ __asm__("pushf\n\t" \
"cli\n\t"); "cli\n\t");
#elif defined(_MSC_VER)
__asm pushfd
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
/* speaker off */ /* speaker off */
b = READ_PORT_UCHAR((PUCHAR)PORT_B); b = READ_PORT_UCHAR((PUCHAR)PORT_B);
WRITE_PORT_UCHAR((PUCHAR)PORT_B, b & 0xFC); WRITE_PORT_UCHAR((PUCHAR)PORT_B, (UCHAR)(b & 0xFC));
if (Frequency) if (Frequency)
{ {
@ -55,7 +62,13 @@ HalMakeBeep (
if (Divider > 0x10000) if (Divider > 0x10000)
{ {
/* restore flags */ /* restore flags */
#if defined(__GNUC__)
__asm__("popf\n\t"); __asm__("popf\n\t");
#elif defined(_MSC_VER)
__asm popfd
#else
#error Unknown compiler for inline assembler
#endif
return FALSE; return FALSE;
} }
@ -66,11 +79,17 @@ HalMakeBeep (
WRITE_PORT_UCHAR((PUCHAR)TIMER2, (UCHAR)((Divider>>8) & 0xFF)); WRITE_PORT_UCHAR((PUCHAR)TIMER2, (UCHAR)((Divider>>8) & 0xFF));
/* speaker on */ /* speaker on */
WRITE_PORT_UCHAR((PUCHAR)PORT_B, READ_PORT_UCHAR((PUCHAR)PORT_B) | 0x03); WRITE_PORT_UCHAR((PUCHAR)PORT_B, (UCHAR)(READ_PORT_UCHAR((PUCHAR)PORT_B) | 0x03));
} }
/* restore flags */ /* restore flags */
#if defined(__GNUC__)
__asm__("popf\n\t"); __asm__("popf\n\t");
#elif defined(_MSC_VER)
__asm popfd
#else
#error Unknown compiler for inline assembler
#endif
return TRUE; return TRUE;
} }

4
reactos/hal/halx86/bus.c
View file

@ -1,4 +1,4 @@
/* $Id: bus.c,v 1.6 2003/02/26 14:14:03 ekohl Exp $ /* $Id: bus.c,v 1.7 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -518,7 +518,7 @@ HalTranslateBusAddress(INTERFACE_TYPE InterfaceType,
if (BusHandler == NULL) if (BusHandler == NULL)
return FALSE; return FALSE;
Result = BusHandler->TranslateBusAddress(BusHandler, Result = (BOOLEAN)BusHandler->TranslateBusAddress(BusHandler,
BusNumber, BusNumber,
BusAddress, BusAddress,
AddressSpace, AddressSpace,

46
reactos/hal/halx86/display.c
View file

@ -16,7 +16,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
/* $Id: display.c,v 1.11 2003/09/02 20:11:43 ea Exp $ /* $Id: display.c,v 1.12 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -223,7 +223,7 @@ HalScrollDisplay (VOID)
SizeX * (SizeY - 1) * 2); SizeX * (SizeY - 1) * 2);
ptr = VideoBuffer + (SizeX * (SizeY - 1)); ptr = VideoBuffer + (SizeX * (SizeY - 1));
for (i = 0; i < SizeX; i++, ptr++) for (i = 0; i < (int)SizeX; i++, ptr++)
{ {
*ptr = (CHAR_ATTRIBUTE << 8) + ' '; *ptr = (CHAR_ATTRIBUTE << 8) + ' ';
} }
@ -257,28 +257,28 @@ HalEnablePalette(VOID)
UCHAR STATIC FASTCALL UCHAR STATIC FASTCALL
HalReadGc(ULONG Index) HalReadGc(ULONG Index)
{ {
WRITE_PORT_UCHAR((PUCHAR)VGA_GC_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_GC_INDEX, (UCHAR)Index);
return(READ_PORT_UCHAR((PUCHAR)VGA_GC_DATA)); return(READ_PORT_UCHAR((PUCHAR)VGA_GC_DATA));
} }
VOID STATIC FASTCALL VOID STATIC FASTCALL
HalWriteGc(ULONG Index, UCHAR Value) HalWriteGc(ULONG Index, UCHAR Value)
{ {
WRITE_PORT_UCHAR((PUCHAR)VGA_GC_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_GC_INDEX, (UCHAR)Index);
WRITE_PORT_UCHAR((PUCHAR)VGA_GC_DATA, Value); WRITE_PORT_UCHAR((PUCHAR)VGA_GC_DATA, Value);
} }
UCHAR STATIC FASTCALL UCHAR STATIC FASTCALL
HalReadSeq(ULONG Index) HalReadSeq(ULONG Index)
{ {
WRITE_PORT_UCHAR((PUCHAR)VGA_SEQ_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_SEQ_INDEX, (UCHAR)Index);
return(READ_PORT_UCHAR((PUCHAR)VGA_SEQ_DATA)); return(READ_PORT_UCHAR((PUCHAR)VGA_SEQ_DATA));
} }
VOID STATIC FASTCALL VOID STATIC FASTCALL
HalWriteSeq(ULONG Index, UCHAR Value) HalWriteSeq(ULONG Index, UCHAR Value)
{ {
WRITE_PORT_UCHAR((PUCHAR)VGA_SEQ_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_SEQ_INDEX, (UCHAR)Index);
WRITE_PORT_UCHAR((PUCHAR)VGA_SEQ_DATA, Value); WRITE_PORT_UCHAR((PUCHAR)VGA_SEQ_DATA, Value);
} }
@ -294,7 +294,7 @@ HalWriteAc(ULONG Index, UCHAR Value)
Index |= 0x20; Index |= 0x20;
} }
(VOID)READ_PORT_UCHAR((PUCHAR)VGA_INSTAT_READ); (VOID)READ_PORT_UCHAR((PUCHAR)VGA_INSTAT_READ);
WRITE_PORT_UCHAR((PUCHAR)VGA_AC_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_AC_INDEX, (UCHAR)Index);
WRITE_PORT_UCHAR((PUCHAR)VGA_AC_WRITE, Value); WRITE_PORT_UCHAR((PUCHAR)VGA_AC_WRITE, Value);
} }
@ -310,21 +310,21 @@ HalReadAc(ULONG Index)
Index |= 0x20; Index |= 0x20;
} }
(VOID)READ_PORT_UCHAR((PUCHAR)VGA_INSTAT_READ); (VOID)READ_PORT_UCHAR((PUCHAR)VGA_INSTAT_READ);
WRITE_PORT_UCHAR((PUCHAR)VGA_AC_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_AC_INDEX, (UCHAR)Index);
return(READ_PORT_UCHAR((PUCHAR)VGA_AC_READ)); return(READ_PORT_UCHAR((PUCHAR)VGA_AC_READ));
} }
VOID STATIC FASTCALL VOID STATIC FASTCALL
HalWriteCrtc(ULONG Index, UCHAR Value) HalWriteCrtc(ULONG Index, UCHAR Value)
{ {
WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, (UCHAR)Index);
WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA, Value); WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA, Value);
} }
UCHAR STATIC FASTCALL UCHAR STATIC FASTCALL
HalReadCrtc(ULONG Index) HalReadCrtc(ULONG Index)
{ {
WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, Index); WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, (UCHAR)Index);
return(READ_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA)); return(READ_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA));
} }
@ -385,16 +385,16 @@ HalSaveFont(VOID)
Seq4 = HalReadSeq(0x04); Seq4 = HalReadSeq(0x04);
/* Force colour mode. */ /* Force colour mode. */
WRITE_PORT_UCHAR((PUCHAR)VGA_MISC_WRITE, MiscOut | 0x01); WRITE_PORT_UCHAR((PUCHAR)VGA_MISC_WRITE, (UCHAR)(MiscOut | 0x01));
HalBlankScreen(FALSE); HalBlankScreen(FALSE);
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
{ {
/* Save font 1 */ /* Save font 1 */
HalWriteSeq(0x02, 0x04 << i); /* Write to plane 2 or 3 */ HalWriteSeq(0x02, (UCHAR)(0x04 << i)); /* Write to plane 2 or 3 */
HalWriteSeq(0x04, 0x06); /* Enable plane graphics. */ HalWriteSeq(0x04, 0x06); /* Enable plane graphics. */
HalWriteGc(0x04, 0x02 + i); /* Read plane 2 or 3 */ HalWriteGc(0x04, (UCHAR)(0x02 + i)); /* Read plane 2 or 3 */
HalWriteGc(0x05, 0x00); /* Write mode 0; read mode 0 */ HalWriteGc(0x05, 0x00); /* Write mode 0; read mode 0 */
HalWriteGc(0x06, 0x05); /* Set graphics. */ HalWriteGc(0x06, 0x05); /* Set graphics. */
memcpy(SavedTextFont[i], GraphVideoBuffer, FONT_AMOUNT); memcpy(SavedTextFont[i], GraphVideoBuffer, FONT_AMOUNT);
@ -482,7 +482,7 @@ HalRestoreFont(VOID)
Seq4 = HalReadSeq(0x04); Seq4 = HalReadSeq(0x04);
/* Force into colour mode. */ /* Force into colour mode. */
WRITE_PORT_UCHAR((PUCHAR)VGA_MISC_WRITE, MiscOut | 0x10); WRITE_PORT_UCHAR((PUCHAR)VGA_MISC_WRITE, (UCHAR)(MiscOut | 0x10));
HalBlankScreen(FALSE); HalBlankScreen(FALSE);
@ -492,9 +492,9 @@ HalRestoreFont(VOID)
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
{ {
HalWriteSeq(0x02, 0x04 << i); /* Write to plane 2 or 3 */ HalWriteSeq(0x02, (UCHAR)(0x04 << i)); /* Write to plane 2 or 3 */
HalWriteSeq(0x04, 0x06); /* Enable plane graphics. */ HalWriteSeq(0x04, 0x06); /* Enable plane graphics. */
HalWriteGc(0x04, 0x02 + i); /* Read plane 2 or 3 */ HalWriteGc(0x04, (UCHAR)(0x02 + i)); /* Read plane 2 or 3 */
HalWriteGc(0x05, 0x00); /* Write mode 0; read mode 0. */ HalWriteGc(0x05, 0x00); /* Write mode 0; read mode 0. */
HalWriteGc(0x06, 0x05); /* Set graphics. */ HalWriteGc(0x06, 0x05); /* Set graphics. */
memcpy(GraphVideoBuffer, SavedTextFont[i], FONT_AMOUNT); memcpy(GraphVideoBuffer, SavedTextFont[i], FONT_AMOUNT);
@ -528,7 +528,7 @@ HalRestoreMode(VOID)
} }
/* Unlock CRTC registers 0-7 */ /* Unlock CRTC registers 0-7 */
HalWriteCrtc(17, SavedTextCrtcReg[17] & ~0x80); HalWriteCrtc(17, (UCHAR)(SavedTextCrtcReg[17] & ~0x80));
for (i = 0; i < VGA_CRTC_NUM_REGISTERS; i++) for (i = 0; i < VGA_CRTC_NUM_REGISTERS; i++)
{ {
@ -683,7 +683,15 @@ HalDisplayString(IN PCH String)
pch = String; pch = String;
pushfl(Flags); pushfl(Flags);
#if defined(__GNUC__)
__asm__ ("cli\n\t"); __asm__ ("cli\n\t");
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
KeAcquireSpinLockAtDpcLevel(&Lock); KeAcquireSpinLockAtDpcLevel(&Lock);
#if 0 #if 0
@ -742,9 +750,9 @@ HalDisplayString(IN PCH String)
offset = (CursorY * SizeX) + CursorX; offset = (CursorY * SizeX) + CursorX;
WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, CRTC_CURLO); WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, CRTC_CURLO);
WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA, offset & 0xff); WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA, (UCHAR)(offset & 0xff));
WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, CRTC_CURHI); WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_INDEX, CRTC_CURHI);
WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA, (offset >> 8) & 0xff); WRITE_PORT_UCHAR((PUCHAR)VGA_CRTC_DATA, (UCHAR)((offset >> 8) & 0xff));
#endif #endif
KeReleaseSpinLockFromDpcLevel(&Lock); KeReleaseSpinLockFromDpcLevel(&Lock);
popfl(Flags); popfl(Flags);

10
reactos/hal/halx86/include/bus.h
View file

@ -6,12 +6,12 @@
#define __INTERNAL_HAL_BUS_H #define __INTERNAL_HAL_BUS_H
typedef NTSTATUS STDCALL typedef NTSTATUS STDCALL_FUNC
(*pAdjustResourceList)(IN PBUS_HANDLER BusHandler, (*pAdjustResourceList)(IN PBUS_HANDLER BusHandler,
IN ULONG BusNumber, IN ULONG BusNumber,
IN OUT PCM_RESOURCE_LIST Resources); IN OUT PCM_RESOURCE_LIST Resources);
typedef NTSTATUS STDCALL typedef NTSTATUS STDCALL_FUNC
(*pAssignSlotResources)(IN PBUS_HANDLER BusHandler, (*pAssignSlotResources)(IN PBUS_HANDLER BusHandler,
IN ULONG BusNumber, IN ULONG BusNumber,
IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING RegistryPath,
@ -21,7 +21,7 @@ typedef NTSTATUS STDCALL
IN ULONG SlotNumber, IN ULONG SlotNumber,
IN OUT PCM_RESOURCE_LIST *AllocatedResources); IN OUT PCM_RESOURCE_LIST *AllocatedResources);
typedef ULONG STDCALL typedef ULONG STDCALL_FUNC
(*pGetSetBusData)(IN PBUS_HANDLER BusHandler, (*pGetSetBusData)(IN PBUS_HANDLER BusHandler,
IN ULONG BusNumber, IN ULONG BusNumber,
IN ULONG SlotNumber, IN ULONG SlotNumber,
@ -29,7 +29,7 @@ typedef ULONG STDCALL
IN ULONG Offset, IN ULONG Offset,
IN ULONG Length); IN ULONG Length);
typedef ULONG STDCALL typedef ULONG STDCALL_FUNC
(*pGetInterruptVector)(IN PBUS_HANDLER BusHandler, (*pGetInterruptVector)(IN PBUS_HANDLER BusHandler,
IN ULONG BusNumber, IN ULONG BusNumber,
IN ULONG BusInterruptLevel, IN ULONG BusInterruptLevel,
@ -37,7 +37,7 @@ typedef ULONG STDCALL
OUT PKIRQL Irql, OUT PKIRQL Irql,
OUT PKAFFINITY Affinity); OUT PKAFFINITY Affinity);
typedef ULONG STDCALL typedef ULONG STDCALL_FUNC
(*pTranslateBusAddress)(IN PBUS_HANDLER BusHandler, (*pTranslateBusAddress)(IN PBUS_HANDLER BusHandler,
IN ULONG BusNumber, IN ULONG BusNumber,
IN PHYSICAL_ADDRESS BusAddress, IN PHYSICAL_ADDRESS BusAddress,

15
reactos/hal/halx86/include/mps.h
View file

@ -382,7 +382,15 @@ static inline VOID ReadPentiumClock(PULARGE_INTEGER Count)
register ULONG nLow; register ULONG nLow;
register ULONG nHigh; register ULONG nHigh;
#if defined(__GNUC__)
__asm__ __volatile__ ("rdtsc" : "=a" (nLow), "=d" (nHigh)); __asm__ __volatile__ ("rdtsc" : "=a" (nLow), "=d" (nHigh));
#elif defined(_MSC_VER)
__asm rdtsc
__asm mov nLow, eax
__asm mov nHigh, edx
#else
#error Unknown compiler for inline assembler
#endif
Count->u.LowPart = nLow; Count->u.LowPart = nLow;
Count->u.HighPart = nHigh; Count->u.HighPart = nHigh;
@ -415,8 +423,15 @@ typedef enum {
} APIC_MODE; } APIC_MODE;
#if defined(__GNUC__)
#define pushfl(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */) #define pushfl(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
#define popfl(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory") #define popfl(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
#elif defined(_MSC_VER)
#define pushfl(x) __asm pushfd __asm pop x;
#define popfl(x) __asm push x __asm popfd;
#else
#error Unknown compiler for inline assembler
#endif
#define PIC_IRQS 16 #define PIC_IRQS 16

48
reactos/hal/halx86/irql.c
View file

@ -1,4 +1,4 @@
/* $Id: irql.c,v 1.13 2003/11/19 21:04:10 gdalsnes Exp $ /* $Id: irql.c,v 1.14 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -44,13 +44,21 @@ PIC_MASK;
* PURPOSE: - Mask for HalEnableSystemInterrupt and HalDisableSystemInterrupt * PURPOSE: - Mask for HalEnableSystemInterrupt and HalDisableSystemInterrupt
* - At startup enable timer and cascade * - At startup enable timer and cascade
*/ */
#if defined(__GNUC__)
static PIC_MASK pic_mask = {.both = 0xFFFA}; static PIC_MASK pic_mask = {.both = 0xFFFA};
#else
static PIC_MASK pic_mask = { 0xFFFA };
#endif
/* /*
* PURPOSE: Mask for disabling of acknowledged interrupts * PURPOSE: Mask for disabling of acknowledged interrupts
*/ */
#if defined(__GNUC__)
static PIC_MASK pic_mask_intr = {.both = 0x0000}; static PIC_MASK pic_mask_intr = {.both = 0x0000};
#else
static PIC_MASK pic_mask_intr = { 0 };
#endif
extern IMPORTED ULONG DpcQueueSize; extern IMPORTED ULONG DpcQueueSize;
@ -95,7 +103,13 @@ VOID HalpInitPICs(VOID)
WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave); WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave);
/* We can now enable interrupts */ /* We can now enable interrupts */
#if defined(__GNUC__)
__asm__ __volatile__ ("sti\n\t"); __asm__ __volatile__ ("sti\n\t");
#elif defined(_MSC_VER)
__asm sti
#else
#error Unknown compiler for inline assembler
#endif
} }
VOID HalpEndSystemInterrupt(KIRQL Irql) VOID HalpEndSystemInterrupt(KIRQL Irql)
@ -112,12 +126,26 @@ VOID HalpEndSystemInterrupt(KIRQL Irql)
}; };
/* Interrupts should be disable while enabling irqs of both pics */ /* Interrupts should be disable while enabling irqs of both pics */
#if defined(__GNUC__)
__asm__("pushf\n\t"); __asm__("pushf\n\t");
__asm__("cli\n\t"); __asm__("cli\n\t");
#elif defined(_MSC_VER)
__asm pushfd
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
pic_mask_intr.both &= mask[Irql]; pic_mask_intr.both &= mask[Irql];
WRITE_PORT_UCHAR((PUCHAR)0x21, pic_mask.master|pic_mask_intr.master); WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave|pic_mask_intr.slave); WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
#if defined(__GNUC__)
__asm__("popf\n\t"); __asm__("popf\n\t");
#elif defined(_MSC_VER)
__asm popfd
#else
#error Unknown compiler for inline assembler
#endif
} }
VOID STATIC VOID STATIC
@ -135,7 +163,7 @@ HalpExecuteIrqs(KIRQL NewIrql)
{ {
if (HalpPendingInterruptCount[i] > 0) if (HalpPendingInterruptCount[i] > 0)
{ {
CurrentIrql = IRQ_TO_DIRQL(i); CurrentIrql = (KIRQL)IRQ_TO_DIRQL(i);
while (HalpPendingInterruptCount[i] > 0) while (HalpPendingInterruptCount[i] > 0)
{ {
@ -366,12 +394,12 @@ HalBeginSystemInterrupt (ULONG Vector,
if (irq < 8) if (irq < 8)
{ {
WRITE_PORT_UCHAR((PUCHAR)0x21, pic_mask.master|pic_mask_intr.master); WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
WRITE_PORT_UCHAR((PUCHAR)0x20, 0x20); WRITE_PORT_UCHAR((PUCHAR)0x20, 0x20);
} }
else else
{ {
WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave|pic_mask_intr.slave); WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
/* Send EOI to the PICs */ /* Send EOI to the PICs */
WRITE_PORT_UCHAR((PUCHAR)0x20,0x20); WRITE_PORT_UCHAR((PUCHAR)0x20,0x20);
WRITE_PORT_UCHAR((PUCHAR)0xa0,0x20); WRITE_PORT_UCHAR((PUCHAR)0xa0,0x20);
@ -410,11 +438,11 @@ BOOLEAN STDCALL HalDisableSystemInterrupt (ULONG Vector,
pic_mask.both |= (1 << irq); pic_mask.both |= (1 << irq);
if (irq < 8) if (irq < 8)
{ {
WRITE_PORT_UCHAR((PUCHAR)0x21, pic_mask.master|pic_mask_intr.slave); WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.slave));
} }
else else
{ {
WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave|pic_mask_intr.slave); WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
} }
return TRUE; return TRUE;
@ -434,11 +462,11 @@ BOOLEAN STDCALL HalEnableSystemInterrupt (ULONG Vector,
pic_mask.both &= ~(1 << irq); pic_mask.both &= ~(1 << irq);
if (irq < 8) if (irq < 8)
{ {
WRITE_PORT_UCHAR((PUCHAR)0x21, pic_mask.master|pic_mask_intr.master); WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
} }
else else
{ {
WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave|pic_mask_intr.slave); WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
} }
return TRUE; return TRUE;

6
reactos/hal/halx86/isa.c
View file

@ -1,4 +1,4 @@
/* $Id: isa.c,v 1.5 2003/04/06 10:45:15 chorns Exp $ /* $Id: isa.c,v 1.6 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -72,11 +72,11 @@ HalpGetIsaInterruptVector(PVOID BusHandler,
PKAFFINITY Affinity) PKAFFINITY Affinity)
{ {
#ifdef MP #ifdef MP
*Irql = PROFILE_LEVEL - BusInterruptVector; *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF; *Affinity = 0xFFFFFFFF;
return IRQ2VECTOR(BusInterruptVector); return IRQ2VECTOR(BusInterruptVector);
#else #else
*Irql = PROFILE_LEVEL - BusInterruptVector; *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF; *Affinity = 0xFFFFFFFF;
return BusInterruptVector; return BusInterruptVector;
#endif #endif

10
reactos/hal/halx86/kdbg.c
View file

@ -1,4 +1,4 @@
/* $Id: kdbg.c,v 1.6 2002/09/08 10:22:24 chorns Exp $ /* $Id: kdbg.c,v 1.7 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -233,8 +233,8 @@ KdPortInitialize (
/* set baud rate */ /* set baud rate */
divisor = 115200 / BaudRate; divisor = 115200 / BaudRate;
WRITE_PORT_UCHAR (SER_DLL(PortBase), divisor & 0xff); WRITE_PORT_UCHAR (SER_DLL(PortBase), (UCHAR)(divisor & 0xff));
WRITE_PORT_UCHAR (SER_DLM(PortBase), (divisor >> 8) & 0xff); WRITE_PORT_UCHAR (SER_DLM(PortBase), (UCHAR)((divisor >> 8) & 0xff));
/* reset DLAB and set 8N1 format */ /* reset DLAB and set 8N1 format */
WRITE_PORT_UCHAR (SER_LCR(PortBase), WRITE_PORT_UCHAR (SER_LCR(PortBase),
@ -323,8 +323,8 @@ KdPortInitializeEx (
/* set baud rate */ /* set baud rate */
divisor = 115200 / PortInformation->BaudRate; divisor = 115200 / PortInformation->BaudRate;
WRITE_PORT_UCHAR (SER_DLL(ComPortBase), divisor & 0xff); WRITE_PORT_UCHAR (SER_DLL(ComPortBase), (UCHAR)(divisor & 0xff));
WRITE_PORT_UCHAR (SER_DLM(ComPortBase), (divisor >> 8) & 0xff); WRITE_PORT_UCHAR (SER_DLM(ComPortBase), (UCHAR)((divisor >> 8) & 0xff));
/* reset DLAB and set 8N1 format */ /* reset DLAB and set 8N1 format */
WRITE_PORT_UCHAR (SER_LCR(ComPortBase), WRITE_PORT_UCHAR (SER_LCR(ComPortBase),

6
reactos/hal/halx86/mca.c
View file

@ -16,7 +16,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
/* $Id: mca.c,v 1.2 2002/10/03 09:11:00 ekohl Exp $ /* $Id: mca.c,v 1.3 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -63,7 +63,7 @@ HalpGetMicroChannelData(PBUS_HANDLER BusHandler,
return(0); return(0);
/* Enter Setup-Mode for given slot */ /* Enter Setup-Mode for given slot */
WRITE_PORT_UCHAR((PUCHAR)0x96, ((UCHAR)(SlotNumber - 1) & 0x07) | 0x08); WRITE_PORT_UCHAR((PUCHAR)0x96, (UCHAR)(((UCHAR)(SlotNumber - 1) & 0x07) | 0x08));
/* Read POS data */ /* Read POS data */
PosData->AdapterId = (READ_PORT_UCHAR((PUCHAR)0x101) << 8) + PosData->AdapterId = (READ_PORT_UCHAR((PUCHAR)0x101) << 8) +
@ -74,7 +74,7 @@ HalpGetMicroChannelData(PBUS_HANDLER BusHandler,
PosData->PosData4 = READ_PORT_UCHAR((PUCHAR)0x105); PosData->PosData4 = READ_PORT_UCHAR((PUCHAR)0x105);
/* Leave Setup-Mode for given slot */ /* Leave Setup-Mode for given slot */
WRITE_PORT_UCHAR((PUCHAR)0x96, (UCHAR)(SlotNumber - 1) & 0x07); WRITE_PORT_UCHAR((PUCHAR)0x96, (UCHAR)((UCHAR)(SlotNumber - 1) & 0x07));
return(sizeof(CM_MCA_POS_DATA)); return(sizeof(CM_MCA_POS_DATA));
} }

15
reactos/hal/halx86/misc.c
View file

@ -1,4 +1,4 @@
/* $Id: misc.c,v 1.3 2002/09/08 10:22:24 chorns Exp $ /* $Id: misc.c,v 1.4 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -38,8 +38,21 @@ VOID STDCALL
HalProcessorIdle (VOID) HalProcessorIdle (VOID)
{ {
#if 1 #if 1
#if defined(__GNUC__)
__asm__("sti\n\t" \ __asm__("sti\n\t" \
"hlt\n\t"); "hlt\n\t");
#elif defined(_MSC_VER)
__asm sti
__asm hlt
#else
#error Unknown compiler for inline assembler
#endif
#else #else
#endif #endif

26
reactos/hal/halx86/mp.c
View file

@ -1,4 +1,4 @@
/* $Id: mp.c,v 1.8 2003/07/21 21:53:51 royce Exp $ /* $Id: mp.c,v 1.9 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -1293,7 +1293,13 @@ VOID APICSendIPI(
ULONG tmp, i, flags; ULONG tmp, i, flags;
pushfl(flags); pushfl(flags);
#if defined(__GNUC__)
__asm__ ("\n\tcli\n\t"); __asm__ ("\n\tcli\n\t");
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
/* Wait up to 100ms for the APIC to become ready */ /* Wait up to 100ms for the APIC to become ready */
for (i = 0; i < 10000; i++) { for (i = 0; i < 10000; i++) {
@ -1389,7 +1395,13 @@ VOID MpsTimerHandler(
* Enable interrupts * Enable interrupts
* NOTE: Only higher priority interrupts will get through * NOTE: Only higher priority interrupts will get through
*/ */
#if defined(__GNUC__)
__asm__("sti\n\t"); __asm__("sti\n\t");
#elif defined(_MSC_VER)
__asm sti
#else
#error Unknown compiler for inline assembler
#endif
if (KeGetCurrentProcessorNumber() == 0) if (KeGetCurrentProcessorNumber() == 0)
{ {
@ -1407,7 +1419,13 @@ VOID MpsTimerHandler(
/* /*
* Disable interrupts * Disable interrupts
*/ */
#if defined(__GNUC__)
__asm__("cli\n\t"); __asm__("cli\n\t");
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
DbgPrint("MpsTimerHandler() 0 IRQL 0x%.08x\n", OldIrql); DbgPrint("MpsTimerHandler() 0 IRQL 0x%.08x\n", OldIrql);
@ -2397,7 +2415,13 @@ HalpInitMPS(
HalpCalibrateStallExecution(); HalpCalibrateStallExecution();
/* We can now enable interrupts */ /* We can now enable interrupts */
#if defined(__GNUC__)
__asm__ __volatile__ ("sti\n\t"); __asm__ __volatile__ ("sti\n\t");
#elif defined(_MSC_VER)
__asm sti
#else
#error Unknown compiler for inline assembler
#endif
NextCPU = 0; NextCPU = 0;
} }

9
reactos/hal/halx86/mpsirql.c
View file

@ -77,10 +77,19 @@ VOID HalpEndSystemInterrupt (KIRQL Irql)
*/ */
{ {
/* Interrupts should be disabled while enabling irqs */ /* Interrupts should be disabled while enabling irqs */
#if defined(__GNUC__)
__asm__("pushf\n\t"); __asm__("pushf\n\t");
__asm__("cli\n\t"); __asm__("cli\n\t");
APICWrite (APIC_TPR, IRQL2TPR (Irql) & APIC_TPR_PRI); APICWrite (APIC_TPR, IRQL2TPR (Irql) & APIC_TPR_PRI);
__asm__("popf\n\t"); __asm__("popf\n\t");
#elif defined(_MSC_VER)
__asm pushfd
__asm cli
APICWrite (APIC_TPR, IRQL2TPR (Irql) & APIC_TPR_PRI);
__asm popfd
#else
#error Unknown compiler for inline assembler
#endif
} }

132
reactos/hal/halx86/pci.c
View file

@ -1,4 +1,4 @@
/* $Id: pci.c,v 1.10 2003/11/05 22:39:01 gvg Exp $ /* $Id: pci.c,v 1.11 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -86,7 +86,7 @@ ReadPciConfigUchar(UCHAR Bus,
case 2: case 2:
KeAcquireSpinLock(&PciLock, &oldIrql); KeAcquireSpinLock(&PciLock, &oldIrql);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot)); WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus); WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
*Value = READ_PORT_UCHAR((PUCHAR)(IOADDR(Slot, Offset))); *Value = READ_PORT_UCHAR((PUCHAR)(IOADDR(Slot, Offset)));
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0); WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
@ -121,7 +121,7 @@ ReadPciConfigUshort(UCHAR Bus,
case 2: case 2:
KeAcquireSpinLock(&PciLock, &oldIrql); KeAcquireSpinLock(&PciLock, &oldIrql);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot)); WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus); WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
*Value = READ_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset))); *Value = READ_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset)));
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0); WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
@ -156,7 +156,7 @@ ReadPciConfigUlong(UCHAR Bus,
case 2: case 2:
KeAcquireSpinLock(&PciLock, &oldIrql); KeAcquireSpinLock(&PciLock, &oldIrql);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot)); WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus); WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
*Value = READ_PORT_ULONG((PULONG)(IOADDR(Slot, Offset))); *Value = READ_PORT_ULONG((PULONG)(IOADDR(Slot, Offset)));
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0); WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
@ -186,7 +186,7 @@ WritePciConfigUchar(UCHAR Bus,
case 2: case 2:
KeAcquireSpinLock(&PciLock, &oldIrql); KeAcquireSpinLock(&PciLock, &oldIrql);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot)); WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus); WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
WRITE_PORT_UCHAR((PUCHAR)(IOADDR(Slot,Offset)), Value); WRITE_PORT_UCHAR((PUCHAR)(IOADDR(Slot,Offset)), Value);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0); WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
@ -221,7 +221,7 @@ WritePciConfigUshort(UCHAR Bus,
case 2: case 2:
KeAcquireSpinLock(&PciLock, &oldIrql); KeAcquireSpinLock(&PciLock, &oldIrql);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot)); WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus); WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
WRITE_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset)), Value); WRITE_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset)), Value);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0); WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
@ -256,7 +256,7 @@ WritePciConfigUlong(UCHAR Bus,
case 2: case 2:
KeAcquireSpinLock(&PciLock, &oldIrql); KeAcquireSpinLock(&PciLock, &oldIrql);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot)); WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus); WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
WRITE_PORT_ULONG((PULONG)(IOADDR(Slot, Offset)), Value); WRITE_PORT_ULONG((PULONG)(IOADDR(Slot, Offset)), Value);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0); WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
@ -290,8 +290,8 @@ HalpGetPciData(PBUS_HANDLER BusHandler,
if ((Length == 0) || (BusConfigType == 0)) if ((Length == 0) || (BusConfigType == 0))
return 0; return 0;
ReadPciConfigUlong(BusNumber, ReadPciConfigUlong((UCHAR)BusNumber,
SlotNumber & 0x1F, (UCHAR)(SlotNumber & 0x1F),
0x00, 0x00,
&Vendor); &Vendor);
/* some broken boards return 0 if a slot is empty: */ /* some broken boards return 0 if a slot is empty: */
@ -306,8 +306,8 @@ HalpGetPciData(PBUS_HANDLER BusHandler,
} }
/* 0E=PCI_HEADER_TYPE */ /* 0E=PCI_HEADER_TYPE */
ReadPciConfigUchar(BusNumber, ReadPciConfigUchar((UCHAR)BusNumber,
SlotNumber & 0x1F, (UCHAR)(SlotNumber & 0x1F),
0x0E, 0x0E,
&HeaderType); &HeaderType);
if (((HeaderType & PCI_MULTIFUNCTION) == 0) && ((SlotNumber & 0xE0) != 0)) if (((HeaderType & PCI_MULTIFUNCTION) == 0) && ((SlotNumber & 0xE0) != 0))
@ -319,8 +319,8 @@ HalpGetPciData(PBUS_HANDLER BusHandler,
} }
return 0; return 0;
} }
ReadPciConfigUlong(BusNumber, ReadPciConfigUlong((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
0x00, 0x00,
&Vendor); &Vendor);
/* some broken boards return 0 if a slot is empty: */ /* some broken boards return 0 if a slot is empty: */
@ -336,55 +336,55 @@ HalpGetPciData(PBUS_HANDLER BusHandler,
if ((Address & 1) && (Len >= 1)) if ((Address & 1) && (Len >= 1))
{ {
ReadPciConfigUchar(BusNumber, ReadPciConfigUchar((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
Ptr); Ptr);
Ptr = Ptr + 1; Ptr = (char*)Ptr + 1;
Address++; Address++;
Len--; Len--;
} }
if ((Address & 2) && (Len >= 2)) if ((Address & 2) && (Len >= 2))
{ {
ReadPciConfigUshort(BusNumber, ReadPciConfigUshort((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
Ptr); Ptr);
Ptr = Ptr + 2; Ptr = (char*)Ptr + 2;
Address += 2; Address += 2;
Len -= 2; Len -= 2;
} }
while (Len >= 4) while (Len >= 4)
{ {
ReadPciConfigUlong(BusNumber, ReadPciConfigUlong((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
Ptr); Ptr);
Ptr = Ptr + 4; Ptr = (char*)Ptr + 4;
Address += 4; Address += 4;
Len -= 4; Len -= 4;
} }
if (Len >= 2) if (Len >= 2)
{ {
ReadPciConfigUshort(BusNumber, ReadPciConfigUshort((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
Ptr); Ptr);
Ptr = Ptr + 2; Ptr = (char*)Ptr + 2;
Address += 2; Address += 2;
Len -= 2; Len -= 2;
} }
if (Len >= 1) if (Len >= 1)
{ {
ReadPciConfigUchar(BusNumber, ReadPciConfigUchar((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
Ptr); Ptr);
Ptr = Ptr + 1; Ptr = (char*)Ptr + 1;
Address++; Address++;
Len--; Len--;
} }
@ -416,8 +416,8 @@ HalpSetPciData(PBUS_HANDLER BusHandler,
if ((Length == 0) || (BusConfigType == 0)) if ((Length == 0) || (BusConfigType == 0))
return 0; return 0;
ReadPciConfigUlong(BusNumber, ReadPciConfigUlong((UCHAR)BusNumber,
SlotNumber & 0x1F, (UCHAR)(SlotNumber & 0x1F),
0x00, 0x00,
&Vendor); &Vendor);
/* some broken boards return 0 if a slot is empty: */ /* some broken boards return 0 if a slot is empty: */
@ -426,15 +426,15 @@ HalpSetPciData(PBUS_HANDLER BusHandler,
/* 0E=PCI_HEADER_TYPE */ /* 0E=PCI_HEADER_TYPE */
ReadPciConfigUchar(BusNumber, ReadPciConfigUchar((UCHAR)BusNumber,
SlotNumber & 0x1F, (UCHAR)(SlotNumber & 0x1F),
0x0E, 0x0E,
&HeaderType); &HeaderType);
if (((HeaderType & PCI_MULTIFUNCTION) == 0) && ((SlotNumber & 0xE0) != 0)) if (((HeaderType & PCI_MULTIFUNCTION) == 0) && ((SlotNumber & 0xE0) != 0))
return 0; return 0;
ReadPciConfigUlong(BusNumber, ReadPciConfigUlong((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
0x00, 0x00,
&Vendor); &Vendor);
/* some broken boards return 0 if a slot is empty: */ /* some broken boards return 0 if a slot is empty: */
@ -443,55 +443,55 @@ HalpSetPciData(PBUS_HANDLER BusHandler,
if ((Address & 1) && (Len >= 1)) if ((Address & 1) && (Len >= 1))
{ {
WritePciConfigUchar(BusNumber, WritePciConfigUchar((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
*(PUCHAR)Ptr); *(PUCHAR)Ptr);
Ptr = Ptr + 1; Ptr = (char*)Ptr + 1;
Address++; Address++;
Len--; Len--;
} }
if ((Address & 2) && (Len >= 2)) if ((Address & 2) && (Len >= 2))
{ {
WritePciConfigUshort(BusNumber, WritePciConfigUshort((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
*(PUSHORT)Ptr); *(PUSHORT)Ptr);
Ptr = Ptr + 2; Ptr = (char*)Ptr + 2;
Address += 2; Address += 2;
Len -= 2; Len -= 2;
} }
while (Len >= 4) while (Len >= 4)
{ {
WritePciConfigUlong(BusNumber, WritePciConfigUlong((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
*(PULONG)Ptr); *(PULONG)Ptr);
Ptr = Ptr + 4; Ptr = (char*)Ptr + 4;
Address += 4; Address += 4;
Len -= 4; Len -= 4;
} }
if (Len >= 2) if (Len >= 2)
{ {
WritePciConfigUshort(BusNumber, WritePciConfigUshort((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
*(PUSHORT)Ptr); *(PUSHORT)Ptr);
Ptr = Ptr + 2; Ptr = (char*)Ptr + 2;
Address += 2; Address += 2;
Len -= 2; Len -= 2;
} }
if (Len >= 1) if (Len >= 1)
{ {
WritePciConfigUchar(BusNumber, WritePciConfigUchar((UCHAR)BusNumber,
SlotNumber, (UCHAR)SlotNumber,
Address, (UCHAR)Address,
*(PUCHAR)Ptr); *(PUCHAR)Ptr);
Ptr = Ptr + 1; Ptr = (char*)Ptr + 1;
Address++; Address++;
Len--; Len--;
} }
@ -552,11 +552,11 @@ HalpGetPciInterruptVector(PVOID BusHandler,
PKAFFINITY Affinity) PKAFFINITY Affinity)
{ {
#ifdef MP #ifdef MP
*Irql = PROFILE_LEVEL - BusInterruptVector; *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF; *Affinity = 0xFFFFFFFF;
return IRQ2VECTOR(BusInterruptVector); return IRQ2VECTOR(BusInterruptVector);
#else #else
*Irql = PROFILE_LEVEL - BusInterruptVector; *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF; *Affinity = 0xFFFFFFFF;
return BusInterruptVector; return BusInterruptVector;
#endif #endif
@ -646,22 +646,22 @@ HalpAssignPciSlotResources(IN PBUS_HANDLER BusHandler,
{ {
ResourceCount++; ResourceCount++;
Offset = offsetof(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]); Offset = offsetof(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
Status = WritePciConfigUlong(BusNumber, SlotNumber, Offset, 0xffffffff); Status = WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset, 0xffffffff);
if (! NT_SUCCESS(Status)) if (! NT_SUCCESS(Status))
{ {
WritePciConfigUlong(BusNumber, SlotNumber, Offset, WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset,
PciConfig.u.type0.BaseAddresses[Address]); PciConfig.u.type0.BaseAddresses[Address]);
return Status; return Status;
} }
Status = ReadPciConfigUlong(BusNumber, SlotNumber, Status = ReadPciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber,
Offset, Size + Address); Offset, Size + Address);
if (! NT_SUCCESS(Status)) if (! NT_SUCCESS(Status))
{ {
WritePciConfigUlong(BusNumber, SlotNumber, Offset, WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset,
PciConfig.u.type0.BaseAddresses[Address]); PciConfig.u.type0.BaseAddresses[Address]);
return Status; return Status;
} }
Status = WritePciConfigUlong(BusNumber, SlotNumber, Offset, Status = WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset,
PciConfig.u.type0.BaseAddresses[Address]); PciConfig.u.type0.BaseAddresses[Address]);
if (! NT_SUCCESS(Status)) if (! NT_SUCCESS(Status))
{ {

168
reactos/hal/halx86/portio.c
View file

@ -1,4 +1,4 @@
/* $Id: portio.c,v 1.3 2002/09/08 10:22:24 chorns Exp $ /* $Id: portio.c,v 1.4 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -38,12 +38,27 @@
* Linus * Linus
*/ */
#if defined(__GNUC__)
#ifdef SLOW_IO_BY_JUMPING #ifdef SLOW_IO_BY_JUMPING
#define __SLOW_DOWN_IO __asm__ __volatile__("jmp 1f\n1:\tjmp 1f\n1:") #define __SLOW_DOWN_IO __asm__ __volatile__("jmp 1f\n1:\tjmp 1f\n1:")
#else #else
#define __SLOW_DOWN_IO __asm__ __volatile__("outb %al,$0x80") #define __SLOW_DOWN_IO __asm__ __volatile__("outb %al,$0x80")
#endif #endif
#elif defined(_MSC_VER)
#ifdef SLOW_IO_BY_JUMPING
#define __SLOW_DOWN_IO __asm jmp 1f __asm jmp 1f 1f:
#else
#define __SLOW_DOWN_IO __asm out 0x80, al
#endif
#else
#error Unknown compiler for inline assembler
#endif
#ifdef REALLY_SLOW_IO #ifdef REALLY_SLOW_IO
#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
#else #else
@ -55,9 +70,22 @@ READ_PORT_BUFFER_UCHAR (PUCHAR Port,
PUCHAR Buffer, PUCHAR Buffer,
ULONG Count) ULONG Count)
{ {
#if defined(__GNUC__)
__asm__ __volatile__ ("cld ; rep ; insb\n\t" __asm__ __volatile__ ("cld ; rep ; insb\n\t"
: "=D" (Buffer), "=c" (Count) : "=D" (Buffer), "=c" (Count)
: "d" (Port),"0" (Buffer),"1" (Count)); : "d" (Port),"0" (Buffer),"1" (Count));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov edi, Buffer
mov ecx, Count
cld
rep ins byte ptr[edi], dx
}
#else
#error Unknown compiler for inline assembler
#endif
} }
VOID STDCALL VOID STDCALL
@ -65,9 +93,22 @@ READ_PORT_BUFFER_USHORT (PUSHORT Port,
PUSHORT Buffer, PUSHORT Buffer,
ULONG Count) ULONG Count)
{ {
#if defined(__GNUC__)
__asm__ __volatile__ ("cld ; rep ; insw" __asm__ __volatile__ ("cld ; rep ; insw"
: "=D" (Buffer), "=c" (Count) : "=D" (Buffer), "=c" (Count)
: "d" (Port),"0" (Buffer),"1" (Count)); : "d" (Port),"0" (Buffer),"1" (Count));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov edi, Buffer
mov ecx, Count
cld
rep ins word ptr[edi], dx
}
#else
#error Unknown compiler for inline assembler
#endif
} }
VOID STDCALL VOID STDCALL
@ -75,19 +116,44 @@ READ_PORT_BUFFER_ULONG (PULONG Port,
PULONG Buffer, PULONG Buffer,
ULONG Count) ULONG Count)
{ {
#if defined(__GNUC__)
__asm__ __volatile__ ("cld ; rep ; insl" __asm__ __volatile__ ("cld ; rep ; insl"
: "=D" (Buffer), "=c" (Count) : "=D" (Buffer), "=c" (Count)
: "d" (Port),"0" (Buffer),"1" (Count)); : "d" (Port),"0" (Buffer),"1" (Count));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov edi, Buffer
mov ecx, Count
cld
rep ins dword ptr[edi], dx
}
#else
#error Unknown compiler for inline assembler
#endif
} }
UCHAR STDCALL UCHAR STDCALL
READ_PORT_UCHAR (PUCHAR Port) READ_PORT_UCHAR (PUCHAR Port)
{ {
UCHAR Value; UCHAR Value;
#if defined(__GNUC__)
__asm__("inb %w1, %0\n\t" __asm__("inb %w1, %0\n\t"
: "=a" (Value) : "=a" (Value)
: "d" (Port)); : "d" (Port));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
in al, dx
mov Value, al
}
#else
#error Unknown compiler for inline assembler
#endif
SLOW_DOWN_IO; SLOW_DOWN_IO;
return(Value); return(Value);
} }
@ -96,10 +162,21 @@ USHORT STDCALL
READ_PORT_USHORT (PUSHORT Port) READ_PORT_USHORT (PUSHORT Port)
{ {
USHORT Value; USHORT Value;
#if defined(__GNUC__)
__asm__("inw %w1, %0\n\t" __asm__("inw %w1, %0\n\t"
: "=a" (Value) : "=a" (Value)
: "d" (Port)); : "d" (Port));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
in ax, dx
mov Value, ax
}
#else
#error Unknown compiler for inline assembler
#endif
SLOW_DOWN_IO; SLOW_DOWN_IO;
return(Value); return(Value);
} }
@ -108,10 +185,21 @@ ULONG STDCALL
READ_PORT_ULONG (PULONG Port) READ_PORT_ULONG (PULONG Port)
{ {
ULONG Value; ULONG Value;
#if defined(__GNUC__)
__asm__("inl %w1, %0\n\t" __asm__("inl %w1, %0\n\t"
: "=a" (Value) : "=a" (Value)
: "d" (Port)); : "d" (Port));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
in eax, dx
mov Value, eax
}
#else
#error Unknown compiler for inline assembler
#endif
SLOW_DOWN_IO; SLOW_DOWN_IO;
return(Value); return(Value);
} }
@ -121,9 +209,22 @@ WRITE_PORT_BUFFER_UCHAR (PUCHAR Port,
PUCHAR Buffer, PUCHAR Buffer,
ULONG Count) ULONG Count)
{ {
#if defined(__GNUC__)
__asm__ __volatile__ ("cld ; rep ; outsb" __asm__ __volatile__ ("cld ; rep ; outsb"
: "=S" (Buffer), "=c" (Count) : "=S" (Buffer), "=c" (Count)
: "d" (Port),"0" (Buffer),"1" (Count)); : "d" (Port),"0" (Buffer),"1" (Count));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov esi, Buffer
mov ecx, Count
cld
rep outs
}
#else
#error Unknown compiler for inline assembler
#endif
} }
VOID STDCALL VOID STDCALL
@ -131,9 +232,22 @@ WRITE_PORT_BUFFER_USHORT (PUSHORT Port,
PUSHORT Buffer, PUSHORT Buffer,
ULONG Count) ULONG Count)
{ {
#if defined(__GNUC__)
__asm__ __volatile__ ("cld ; rep ; outsw" __asm__ __volatile__ ("cld ; rep ; outsw"
: "=S" (Buffer), "=c" (Count) : "=S" (Buffer), "=c" (Count)
: "d" (Port),"0" (Buffer),"1" (Count)); : "d" (Port),"0" (Buffer),"1" (Count));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov esi, Buffer
mov ecx, Count
cld
rep outsw
}
#else
#error Unknown compiler for inline assembler
#endif
} }
VOID STDCALL VOID STDCALL
@ -141,19 +255,43 @@ WRITE_PORT_BUFFER_ULONG (PULONG Port,
PULONG Buffer, PULONG Buffer,
ULONG Count) ULONG Count)
{ {
#if defined(__GNUC__)
__asm__ __volatile__ ("cld ; rep ; outsl" __asm__ __volatile__ ("cld ; rep ; outsl"
: "=S" (Buffer), "=c" (Count) : "=S" (Buffer), "=c" (Count)
: "d" (Port),"0" (Buffer),"1" (Count)); : "d" (Port),"0" (Buffer),"1" (Count));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov esi, Buffer
mov ecx, Count
cld
rep outsd
}
#else
#error Unknown compiler for inline assembler
#endif
} }
VOID STDCALL VOID STDCALL
WRITE_PORT_UCHAR (PUCHAR Port, WRITE_PORT_UCHAR (PUCHAR Port,
UCHAR Value) UCHAR Value)
{ {
#if defined(__GNUC__)
__asm__("outb %0, %w1\n\t" __asm__("outb %0, %w1\n\t"
: :
: "a" (Value), : "a" (Value),
"d" (Port)); "d" (Port));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov al, Value
out dx,al
}
#else
#error Unknown compiler for inline assembler
#endif
SLOW_DOWN_IO; SLOW_DOWN_IO;
} }
@ -161,10 +299,21 @@ VOID STDCALL
WRITE_PORT_USHORT (PUSHORT Port, WRITE_PORT_USHORT (PUSHORT Port,
USHORT Value) USHORT Value)
{ {
#if defined(__GNUC__)
__asm__("outw %0, %w1\n\t" __asm__("outw %0, %w1\n\t"
: :
: "a" (Value), : "a" (Value),
"d" (Port)); "d" (Port));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov ax, Value
out dx,ax
}
#else
#error Unknown compiler for inline assembler
#endif
SLOW_DOWN_IO; SLOW_DOWN_IO;
} }
@ -172,10 +321,21 @@ VOID STDCALL
WRITE_PORT_ULONG (PULONG Port, WRITE_PORT_ULONG (PULONG Port,
ULONG Value) ULONG Value)
{ {
#if defined(__GNUC__)
__asm__("outl %0, %w1\n\t" __asm__("outl %0, %w1\n\t"
: :
: "a" (Value), : "a" (Value),
"d" (Port)); "d" (Port));
#elif defined(_MSC_VER)
__asm
{
mov edx, Port
mov eax, Value
out dx,eax
}
#else
#error Unknown compiler for inline assembler
#endif
SLOW_DOWN_IO; SLOW_DOWN_IO;
} }

9
reactos/hal/halx86/pwroff.c
View file

@ -1,4 +1,4 @@
/* $Id: pwroff.c,v 1.3 2002/09/08 10:22:24 chorns Exp $ /* $Id: pwroff.c,v 1.4 2003/12/28 22:38:09 fireball Exp $
* *
* FILE : reactos/hal/x86/apm.c * FILE : reactos/hal/x86/apm.c
* DESCRIPTION: Turn CPU off... * DESCRIPTION: Turn CPU off...
@ -23,6 +23,8 @@
#if defined(__GNUC__)
nopm db 'No power management functionality',10,13,'$' nopm db 'No power management functionality',10,13,'$'
errmsg db 'Power management error',10,13,'$' errmsg db 'Power management error',10,13,'$'
wrongver db 'Need APM version 1.1 or better',10,13,'$' wrongver db 'Need APM version 1.1 or better',10,13,'$'
@ -89,6 +91,11 @@ ApmCall (
__asm__("int 21\n"); /* 0x15 */ __asm__("int 21\n"); /* 0x15 */
} }
#elif defined(_MSC_VER)
#else
#error Unknown compiler for inline assembler
#endif
BOOLEAN BOOLEAN
HalPowerOff (VOID) HalPowerOff (VOID)

19
reactos/hal/halx86/reboot.c
View file

@ -1,4 +1,4 @@
/* $Id: reboot.c,v 1.4 2003/06/21 14:25:30 gvg Exp $ /* $Id: reboot.c,v 1.5 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -27,17 +27,24 @@ HalReboot (VOID)
mem[0x473] = 0x12; mem[0x473] = 0x12;
/* disable interrupts */ /* disable interrupts */
#if defined(__GNUC__)
__asm__("cli\n"); __asm__("cli\n");
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
/* disable periodic interrupt (RTC) */ /* disable periodic interrupt (RTC) */
WRITE_PORT_UCHAR((PUCHAR)0x70, 0x0b); WRITE_PORT_UCHAR((PUCHAR)0x70, 0x0b);
data = READ_PORT_UCHAR((PUCHAR)0x71); data = READ_PORT_UCHAR((PUCHAR)0x71);
WRITE_PORT_UCHAR((PUCHAR)0x71, data & 0xbf); WRITE_PORT_UCHAR((PUCHAR)0x71, (UCHAR)(data & 0xbf));
/* */ /* */
WRITE_PORT_UCHAR((PUCHAR)0x70, 0x0a); WRITE_PORT_UCHAR((PUCHAR)0x70, 0x0a);
data = READ_PORT_UCHAR((PUCHAR)0x71); data = READ_PORT_UCHAR((PUCHAR)0x71);
WRITE_PORT_UCHAR((PUCHAR)0x71, (data & 0xf0) | 0x06); WRITE_PORT_UCHAR((PUCHAR)0x71, (UCHAR)((data & 0xf0) | 0x06));
/* */ /* */
WRITE_PORT_UCHAR((PUCHAR)0x70, 0x15); WRITE_PORT_UCHAR((PUCHAR)0x70, 0x15);
@ -47,7 +54,13 @@ HalReboot (VOID)
/* stop the processor */ /* stop the processor */
#if 1 #if 1
#if defined(__GNUC__)
__asm__("hlt\n"); __asm__("hlt\n");
#elif defined(_MSC_VER)
__asm hlt
#else
#error Unknown compiler for inline assembler
#endif
#else #else
for(;;); for(;;);
#endif #endif

6
reactos/hal/halx86/sysbus.c
View file

@ -1,4 +1,4 @@
/* $Id: sysbus.c,v 1.5 2003/04/06 10:45:15 chorns Exp $ /* $Id: sysbus.c,v 1.6 2003/12/28 22:38:09 fireball Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -30,11 +30,11 @@ HalpGetSystemInterruptVector(PVOID BusHandler,
PKAFFINITY Affinity) PKAFFINITY Affinity)
{ {
#ifdef MP #ifdef MP
*Irql = PROFILE_LEVEL - BusInterruptVector; *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF; *Affinity = 0xFFFFFFFF;
return IRQ2VECTOR(BusInterruptVector); return IRQ2VECTOR(BusInterruptVector);
#else #else
*Irql = PROFILE_LEVEL - BusInterruptVector; *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF; *Affinity = 0xFFFFFFFF;
return BusInterruptVector; return BusInterruptVector;
#endif #endif

42
reactos/hal/halx86/time.c
View file

@ -47,7 +47,13 @@ HalpQueryCMOS(UCHAR Reg)
Reg |= 0x80; Reg |= 0x80;
pushfl(Flags); pushfl(Flags);
#if defined(__GNUC__)
__asm__("cli\n"); // AP unsure as to whether to do this here __asm__("cli\n"); // AP unsure as to whether to do this here
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
WRITE_PORT_UCHAR((PUCHAR)0x70, Reg); WRITE_PORT_UCHAR((PUCHAR)0x70, Reg);
Val = READ_PORT_UCHAR((PUCHAR)0x71); Val = READ_PORT_UCHAR((PUCHAR)0x71);
WRITE_PORT_UCHAR((PUCHAR)0x70, 0); WRITE_PORT_UCHAR((PUCHAR)0x70, 0);
@ -65,7 +71,13 @@ HalpSetCMOS(UCHAR Reg,
Reg |= 0x80; Reg |= 0x80;
pushfl(Flags); pushfl(Flags);
#if defined(__GNUC__)
__asm__("cli\n"); // AP unsure as to whether to do this here __asm__("cli\n"); // AP unsure as to whether to do this here
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
WRITE_PORT_UCHAR((PUCHAR)0x70, Reg); WRITE_PORT_UCHAR((PUCHAR)0x70, Reg);
WRITE_PORT_UCHAR((PUCHAR)0x71, Val); WRITE_PORT_UCHAR((PUCHAR)0x71, Val);
WRITE_PORT_UCHAR((PUCHAR)0x70, 0); WRITE_PORT_UCHAR((PUCHAR)0x70, 0);
@ -80,7 +92,13 @@ HalpQueryECMOS(USHORT Reg)
ULONG Flags; ULONG Flags;
pushfl(Flags); pushfl(Flags);
#if defined(__GNUC__)
__asm__("cli\n"); // AP unsure as to whether to do this here __asm__("cli\n"); // AP unsure as to whether to do this here
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
WRITE_PORT_UCHAR((PUCHAR)0x74, (UCHAR)(Reg & 0x00FF)); WRITE_PORT_UCHAR((PUCHAR)0x74, (UCHAR)(Reg & 0x00FF));
WRITE_PORT_UCHAR((PUCHAR)0x75, (UCHAR)(Reg>>8)); WRITE_PORT_UCHAR((PUCHAR)0x75, (UCHAR)(Reg>>8));
Val = READ_PORT_UCHAR((PUCHAR)0x76); Val = READ_PORT_UCHAR((PUCHAR)0x76);
@ -97,7 +115,13 @@ HalpSetECMOS(USHORT Reg,
ULONG Flags; ULONG Flags;
pushfl(Flags); pushfl(Flags);
#if defined(__GNUC__)
__asm__("cli\n"); // AP unsure as to whether to do this here __asm__("cli\n"); // AP unsure as to whether to do this here
#elif defined(_MSC_VER)
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
WRITE_PORT_UCHAR((PUCHAR)0x74, (UCHAR)(Reg & 0x00FF)); WRITE_PORT_UCHAR((PUCHAR)0x74, (UCHAR)(Reg & 0x00FF));
WRITE_PORT_UCHAR((PUCHAR)0x75, (UCHAR)(Reg>>8)); WRITE_PORT_UCHAR((PUCHAR)0x75, (UCHAR)(Reg>>8));
WRITE_PORT_UCHAR((PUCHAR)0x76, Val); WRITE_PORT_UCHAR((PUCHAR)0x76, Val);
@ -160,13 +184,13 @@ HalSetRealTimeClock(PTIME_FIELDS Time)
/* check 'Update In Progress' bit */ /* check 'Update In Progress' bit */
while (HalpQueryCMOS (RTC_REGISTER_A) & RTC_REG_A_UIP); while (HalpQueryCMOS (RTC_REGISTER_A) & RTC_REG_A_UIP);
HalpSetCMOS (0, INT_BCD(Time->Second)); HalpSetCMOS (0, (UCHAR)INT_BCD(Time->Second));
HalpSetCMOS (2, INT_BCD(Time->Minute)); HalpSetCMOS (2, (UCHAR)INT_BCD(Time->Minute));
HalpSetCMOS (4, INT_BCD(Time->Hour)); HalpSetCMOS (4, (UCHAR)INT_BCD(Time->Hour));
HalpSetCMOS (6, INT_BCD(Time->Weekday)); HalpSetCMOS (6, (UCHAR)INT_BCD(Time->Weekday));
HalpSetCMOS (7, INT_BCD(Time->Day)); HalpSetCMOS (7, (UCHAR)INT_BCD(Time->Day));
HalpSetCMOS (8, INT_BCD(Time->Month)); HalpSetCMOS (8, (UCHAR)INT_BCD(Time->Month));
HalpSetCMOS (9, INT_BCD(Time->Year % 100)); HalpSetCMOS (9, (UCHAR)INT_BCD(Time->Year % 100));
#if 0 #if 0
/* Century */ /* Century */
@ -221,9 +245,9 @@ HalSetEnvironmentVariable(PCH Name,
Val = HalpQueryCMOS(RTC_REGISTER_B); Val = HalpQueryCMOS(RTC_REGISTER_B);
if (_stricmp(Value, "TRUE") == 0) if (_stricmp(Value, "TRUE") == 0)
HalpSetCMOS(RTC_REGISTER_B, Val | 0x01); HalpSetCMOS(RTC_REGISTER_B, (UCHAR)(Val | 0x01));
else if (_stricmp(Value, "FALSE") == 0) else if (_stricmp(Value, "FALSE") == 0)
HalpSetCMOS(RTC_REGISTER_B, Val & ~0x01); HalpSetCMOS(RTC_REGISTER_B, (UCHAR)(Val & ~0x01));
else else
result = FALSE; result = FALSE;

28
reactos/hal/halx86/timer.c
View file

@ -20,7 +20,7 @@
* MA 02139, USA. * MA 02139, USA.
* *
*/ */
/* $Id: timer.c,v 1.1 2003/06/19 16:00:03 gvg Exp $ /* $Id: timer.c,v 1.2 2003/12/28 22:38:09 fireball Exp $
* *
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
* FILE: ntoskrnl/hal/x86/udelay.c * FILE: ntoskrnl/hal/x86/udelay.c
@ -99,15 +99,28 @@ static ULONG Read8254Timer(VOID)
ULONG Count; ULONG Count;
/* save flags and disable interrupts */ /* save flags and disable interrupts */
#if defined(__GNUC__)
__asm__("pushf\n\t" \ __asm__("pushf\n\t" \
"cli\n\t"); "cli\n\t");
#elif defined(_MSC_VER)
__asm pushfd
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
WRITE_PORT_UCHAR((PUCHAR) TMR_CTRL, TMR_SC0 | TMR_LATCH); WRITE_PORT_UCHAR((PUCHAR) TMR_CTRL, TMR_SC0 | TMR_LATCH);
Count = READ_PORT_UCHAR((PUCHAR) TMR_CNT0); Count = READ_PORT_UCHAR((PUCHAR) TMR_CNT0);
Count |= READ_PORT_UCHAR((PUCHAR) TMR_CNT0) << 8; Count |= READ_PORT_UCHAR((PUCHAR) TMR_CNT0) << 8;
/* restore flags */ /* restore flags */
#if defined(__GNUC__)
__asm__("popf\n\t"); __asm__("popf\n\t");
#elif defined(_MSC_VER)
__asm popfd
#else
#error Unknown compiler for inline assembler
#endif
return Count; return Count;
} }
@ -228,13 +241,26 @@ HalCalibratePerformanceCounter(ULONG Count)
ULONG i; ULONG i;
/* save flags and disable interrupts */ /* save flags and disable interrupts */
#if defined(__GNUC__)
__asm__("pushf\n\t" \ __asm__("pushf\n\t" \
"cli\n\t"); "cli\n\t");
#elif defined(_MSC_VER)
__asm pushfd
__asm cli
#else
#error Unknown compiler for inline assembler
#endif
for (i = 0; i < Count; i++); for (i = 0; i < Count; i++);
/* restore flags */ /* restore flags */
#if defined(__GNUC__)
__asm__("popf\n\t"); __asm__("popf\n\t");
#elif defined(_MSC_VER)
__asm popfd
#else
#error Unknown compiler for inline assembler
#endif
} }