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[NTOSKRNL]
- Fix MiAddressToPti and implement MiAddressToPxi for amd64 - Replace #error with DPRINT and ASSERT(FALSE) in MiInitializeLargePageSupport - Implement amd64 specific MmCreateProcessAddressSpace - Add MmProtectToPteMask for amd64 (copied from x86) - Remove amd64 version of MmInitializeHandBuiltProcess svn path=/trunk/; revision=48249
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@ -108,12 +108,17 @@ ULONG
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FORCEINLINE
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FORCEINLINE
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MiAddressToPti(PVOID Address)
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MiAddressToPti(PVOID Address)
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{
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{
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ULONG64 Pti = (ULONG64)Address >> PTI_SHIFT;
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return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
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Pti &= PTI_MASK_AMD64;
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}
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return Pti;
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#define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
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ULONG
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FORCEINLINE
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MiAddressToPxi(PVOID Address)
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{
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return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
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}
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}
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#define MiAddressToPteOffset(x) MiAddressToPti(x)
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/* Convert a PTE into a corresponding address */
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/* Convert a PTE into a corresponding address */
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PVOID
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PVOID
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@ -34,7 +34,8 @@ NTAPI
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MiInitializeLargePageSupport(VOID)
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MiInitializeLargePageSupport(VOID)
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{
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{
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#if _MI_PAGING_LEVELS > 2
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#if _MI_PAGING_LEVELS > 2
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#error "PAE/x64 Not Implemented"
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DPRINT1("PAE/x64 Not Implemented\n");
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ASSERT(FALSE);
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#else
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#else
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/* Initialize the large-page hyperspace PTE used for initial mapping */
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/* Initialize the large-page hyperspace PTE used for initial mapping */
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MiLargePageHyperPte = MiReserveSystemPtes(1, SystemPteSpace);
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MiLargePageHyperPte = MiReserveSystemPtes(1, SystemPteSpace);
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@ -1040,6 +1040,7 @@ MmInitializeHandBuiltProcess2(IN PEPROCESS Process)
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return STATUS_SUCCESS;
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return STATUS_SUCCESS;
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}
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}
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#ifdef _M_IX86
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/* FIXME: Evaluate ways to make this portable yet arch-specific */
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/* FIXME: Evaluate ways to make this portable yet arch-specific */
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BOOLEAN
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BOOLEAN
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NTAPI
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NTAPI
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@ -1131,6 +1132,7 @@ MmCreateProcessAddressSpace(IN ULONG MinWs,
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MiReleaseSystemPtes(PointerPte, 1, SystemPteSpace);
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MiReleaseSystemPtes(PointerPte, 1, SystemPteSpace);
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return TRUE;
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return TRUE;
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}
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}
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#endif
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VOID
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VOID
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NTAPI
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NTAPI
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@ -5,6 +5,7 @@
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* PURPOSE: Low level memory managment manipulation
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* PURPOSE: Low level memory managment manipulation
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*
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*
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* PROGRAMMER: Timo Kreuzer (timo.kreuzer@reactos.org)
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* PROGRAMMER: Timo Kreuzer (timo.kreuzer@reactos.org)
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* ReactOS Portable Systems Group
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*/
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*/
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/* INCLUDES ***************************************************************/
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/* INCLUDES ***************************************************************/
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@ -12,6 +13,7 @@
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#include <ntoskrnl.h>
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#include <ntoskrnl.h>
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#define NDEBUG
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#define NDEBUG
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#include <debug.h>
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#include <debug.h>
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#include "../ARM3/miarm.h"
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#undef InterlockedExchangePte
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#undef InterlockedExchangePte
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#define InterlockedExchangePte(pte1, pte2) \
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#define InterlockedExchangePte(pte1, pte2) \
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@ -25,6 +27,55 @@ extern MMPTE HyperTemplatePte;
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/* GLOBALS *****************************************************************/
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/* GLOBALS *****************************************************************/
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const
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ULONG
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MmProtectToPteMask[32] =
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{
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//
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// These are the base MM_ protection flags
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//
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0,
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PTE_READONLY | PTE_ENABLE_CACHE,
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PTE_EXECUTE | PTE_ENABLE_CACHE,
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PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
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PTE_READWRITE | PTE_ENABLE_CACHE,
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PTE_WRITECOPY | PTE_ENABLE_CACHE,
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PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
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PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
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//
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// These OR in the MM_NOCACHE flag
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//
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0,
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PTE_READONLY | PTE_DISABLE_CACHE,
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PTE_EXECUTE | PTE_DISABLE_CACHE,
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PTE_EXECUTE_READ | PTE_DISABLE_CACHE,
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PTE_READWRITE | PTE_DISABLE_CACHE,
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PTE_WRITECOPY | PTE_DISABLE_CACHE,
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PTE_EXECUTE_READWRITE | PTE_DISABLE_CACHE,
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PTE_EXECUTE_WRITECOPY | PTE_DISABLE_CACHE,
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//
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// These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
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//
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0,
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PTE_READONLY | PTE_ENABLE_CACHE,
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PTE_EXECUTE | PTE_ENABLE_CACHE,
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PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
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PTE_READWRITE | PTE_ENABLE_CACHE,
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PTE_WRITECOPY | PTE_ENABLE_CACHE,
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PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
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PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
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//
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// These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
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//
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0,
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PTE_READONLY | PTE_WRITECOMBINED_CACHE,
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PTE_EXECUTE | PTE_WRITECOMBINED_CACHE,
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PTE_EXECUTE_READ | PTE_WRITECOMBINED_CACHE,
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PTE_READWRITE | PTE_WRITECOMBINED_CACHE,
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PTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
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PTE_EXECUTE_READWRITE | PTE_WRITECOMBINED_CACHE,
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PTE_EXECUTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
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};
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/* PRIVATE FUNCTIONS *******************************************************/
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/* PRIVATE FUNCTIONS *******************************************************/
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@ -489,34 +540,95 @@ MmCreateVirtualMapping(PEPROCESS Process,
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return MmCreateVirtualMappingUnsafe(Process, Address, Protect, Pages, PageCount);
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return MmCreateVirtualMappingUnsafe(Process, Address, Protect, Pages, PageCount);
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}
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}
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NTSTATUS
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NTAPI
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MmInitializeHandBuiltProcess(IN PEPROCESS Process,
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IN PULONG_PTR DirectoryTableBase)
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{
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/* Share the directory base with the idle process */
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DirectoryTableBase[0] = PsGetCurrentProcess()->Pcb.DirectoryTableBase[0];
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DirectoryTableBase[1] = PsGetCurrentProcess()->Pcb.DirectoryTableBase[1];
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/* Initialize the Addresss Space */
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KeInitializeGuardedMutex(&Process->AddressCreationLock);
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Process->Vm.WorkingSetExpansionLinks.Flink = NULL;
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ASSERT(Process->VadRoot.NumberGenericTableElements == 0);
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Process->VadRoot.BalancedRoot.u1.Parent = &Process->VadRoot.BalancedRoot;
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/* The process now has an address space */
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Process->HasAddressSpace = TRUE;
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return STATUS_SUCCESS;
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}
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BOOLEAN
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BOOLEAN
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NTAPI
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NTAPI
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MmCreateProcessAddressSpace(IN ULONG MinWs,
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MmCreateProcessAddressSpace(IN ULONG MinWs,
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IN PEPROCESS Process,
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IN PEPROCESS Process,
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IN PULONG_PTR DirectoryTableBase)
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OUT PULONG_PTR DirectoryTableBase)
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{
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{
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UNIMPLEMENTED;
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KIRQL OldIrql;
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return 0;
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PFN_NUMBER TableBasePfn, HyperPfn;
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PMMPTE PointerPte;
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MMPTE TempPte, PdePte;
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ULONG TableIndex;
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PMMPTE SystemTable;
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/* No page colors yet */
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Process->NextPageColor = 0;
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/* Setup the hyperspace lock */
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KeInitializeSpinLock(&Process->HyperSpaceLock);
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/* Lock PFN database */
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OldIrql = KeAcquireQueuedSpinLock(LockQueuePfnLock);
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/* Get a page for the table base and for hyperspace */
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TableBasePfn = MiRemoveAnyPage(0);
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HyperPfn = MiRemoveAnyPage(0);
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/* Release PFN lock */
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KeReleaseQueuedSpinLock(LockQueuePfnLock, OldIrql);
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/* Zero both pages */
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MiZeroPhysicalPage(TableBasePfn);
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MiZeroPhysicalPage(HyperPfn);
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/* Set the base directory pointers */
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DirectoryTableBase[0] = TableBasePfn << PAGE_SHIFT;
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DirectoryTableBase[1] = HyperPfn << PAGE_SHIFT;
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/* Make sure we don't already have a page directory setup */
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ASSERT(Process->Pcb.DirectoryTableBase[0] == 0);
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/* Insert us into the Mm process list */
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InsertTailList(&MmProcessList, &Process->MmProcessLinks);
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/* Get a PTE to map the page directory */
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PointerPte = MiReserveSystemPtes(1, SystemPteSpace);
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ASSERT(PointerPte != NULL);
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/* Build it */
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MI_MAKE_HARDWARE_PTE_KERNEL(&PdePte,
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PointerPte,
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MM_READWRITE,
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TableBasePfn);
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/* Set it dirty and map it */
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PdePte.u.Hard.Dirty = TRUE;
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MI_WRITE_VALID_PTE(PointerPte, PdePte);
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/* Now get the page directory (which we'll double map, so call it a page table */
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SystemTable = MiPteToAddress(PointerPte);
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/* Copy all the kernel mappings */
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TableIndex = MiAddressToPxi(MmSystemRangeStart);
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RtlCopyMemory(&SystemTable[TableIndex],
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MiAddressToPxe(MmSystemRangeStart),
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PAGE_SIZE - TableIndex * sizeof(MMPTE));
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/* Now write the PTE/PDE entry for hyperspace itself */
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TempPte = ValidKernelPte;
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TempPte.u.Hard.PageFrameNumber = HyperPfn;
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TableIndex = MiAddressToPxi(HYPER_SPACE);
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SystemTable[TableIndex] = TempPte;
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/* Sanity check */
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ASSERT(MiAddressToPxi(MmHyperSpaceEnd) > TableIndex);
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/* Now do the x86 trick of making the PDE a page table itself */
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TableIndex = MiAddressToPxi(PTE_BASE);
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TempPte.u.Hard.PageFrameNumber = TableBasePfn;
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SystemTable[TableIndex] = TempPte;
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/* Let go of the system PTE */
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MiReleaseSystemPtes(PointerPte, 1, SystemPteSpace);
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/* Switch to phase 1 initialization */
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ASSERT(Process->AddressSpaceInitialized == 0);
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Process->AddressSpaceInitialized = 1;
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return TRUE;
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}
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}
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/* EOF */
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/* EOF */
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