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- For one thing, fix build in ARM3/init.c (sorry!)
- Secondly, initialize hyperspace in ARM³ now, at the correct place: - Also, create the hyperspace PDE here, and not in FreeLDR, which was incorrect in the first place. - This might help booting Windows/WinLDR. - Install-tested w/ networking, with no issues found, on: - Virtual Box 2.4 - VMWare 6.5 - QEMU 0.9.0 - PEBKAC? svn path=/trunk/; revision=41573
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@ -149,10 +149,5 @@ MasterTranslationTable:
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.space 0x0400 // 0xYYYYYYYY->0xC10FFFFF
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.space 0x0400 // 0xYYYYYYYY->0xC10FFFFF
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.space 0x0C00 // PADDING FOR 4KB GRANULARITY
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.space 0x0C00 // PADDING FOR 4KB GRANULARITY
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.global HyperSpaceTranslationTable
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HyperSpaceTranslationTable:
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.space 0x0400 // 0xYYYYYYYY->0xC10FFFFF
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.space 0x0C00 // PADDING FOR 4KB GRANULARITY
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.global TranslationTableEnd
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.global TranslationTableEnd
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TranslationTableEnd:
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TranslationTableEnd:
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@ -42,7 +42,7 @@ PCHAR ArmSharedHeap;
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extern ADDRESS_RANGE ArmBoardMemoryMap[16];
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extern ADDRESS_RANGE ArmBoardMemoryMap[16];
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extern ULONG ArmBoardMemoryMapRangeCount;
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extern ULONG ArmBoardMemoryMapRangeCount;
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extern ARM_TRANSLATION_TABLE ArmTranslationTable;
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extern ARM_TRANSLATION_TABLE ArmTranslationTable;
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extern ARM_COARSE_PAGE_TABLE BootTranslationTable, KernelTranslationTable, FlatMapTranslationTable, MasterTranslationTable, HyperSpaceTranslationTable;
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extern ARM_COARSE_PAGE_TABLE BootTranslationTable, KernelTranslationTable, FlatMapTranslationTable, MasterTranslationTable;
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extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint;
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extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint;
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extern ULONG_PTR KernelBase;
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extern ULONG_PTR KernelBase;
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extern ULONG_PTR AnsiData, OemData, UnicodeData, RegistryData, KernelData, HalData, DriverData[16];
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extern ULONG_PTR AnsiData, OemData, UnicodeData, RegistryData, KernelData, HalData, DriverData[16];
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@ -683,7 +683,7 @@ ArmSetupPageDirectory(VOID)
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ARM_PTE Pte;
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ARM_PTE Pte;
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ULONG i, j;
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ULONG i, j;
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PARM_TRANSLATION_TABLE ArmTable;
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PARM_TRANSLATION_TABLE ArmTable;
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PARM_COARSE_PAGE_TABLE BootTable, KernelTable, FlatMapTable, MasterTable, HyperSpaceTable;
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PARM_COARSE_PAGE_TABLE BootTable, KernelTable, FlatMapTable, MasterTable;
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//
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//
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// Get the PDEs that we will use
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// Get the PDEs that we will use
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@ -693,7 +693,6 @@ ArmSetupPageDirectory(VOID)
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KernelTable = &KernelTranslationTable;
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KernelTable = &KernelTranslationTable;
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FlatMapTable = &FlatMapTranslationTable;
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FlatMapTable = &FlatMapTranslationTable;
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MasterTable = &MasterTranslationTable;
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MasterTable = &MasterTranslationTable;
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HyperSpaceTable = &HyperSpaceTranslationTable;
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//
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//
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// Set the master L1 PDE as the TTB
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// Set the master L1 PDE as the TTB
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@ -811,12 +810,6 @@ ArmSetupPageDirectory(VOID)
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Pte.L1.Coarse.BaseAddress = (ULONG)MasterTable >> CPT_SHIFT;
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Pte.L1.Coarse.BaseAddress = (ULONG)MasterTable >> CPT_SHIFT;
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ArmTable->Pte[PDE_BASE >> PDE_SHIFT] = Pte;
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ArmTable->Pte[PDE_BASE >> PDE_SHIFT] = Pte;
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//
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// Now create the template for the hyperspace table which maps 1MB
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//
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Pte.L1.Coarse.BaseAddress = (ULONG)HyperSpaceTable >> CPT_SHIFT;
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ArmTable->Pte[HYPER_SPACE >> PDE_SHIFT] = Pte;
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//
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//
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// Now create the template for the coarse page tables which map the first 8MB
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// Now create the template for the coarse page tables which map the first 8MB
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//
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//
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@ -983,12 +976,6 @@ ArmSetupPageDirectory(VOID)
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Pte.L2.Small.BaseAddress = (ULONG)&MasterTranslationTable >> PTE_SHIFT;
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Pte.L2.Small.BaseAddress = (ULONG)&MasterTranslationTable >> PTE_SHIFT;
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FlatMapTable->Pte[16] = Pte;
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FlatMapTable->Pte[16] = Pte;
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//
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// And finally for the 0xC1100000 region (1MB)
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//
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Pte.L2.Small.BaseAddress = (ULONG)&HyperSpaceTranslationTable >> PTE_SHIFT;
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FlatMapTable->Pte[17] = Pte;
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//
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//
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// Now we handle the master translation area for our PDEs. We'll just make
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// Now we handle the master translation area for our PDEs. We'll just make
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// the 4 page tables point to the ARM TTB.
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// the 4 page tables point to the ARM TTB.
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@ -27,7 +27,6 @@
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extern PAGE_DIRECTORY_X86 startup_pagedirectory;
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extern PAGE_DIRECTORY_X86 startup_pagedirectory;
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extern PAGE_DIRECTORY_X86 lowmem_pagetable;
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extern PAGE_DIRECTORY_X86 lowmem_pagetable;
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extern PAGE_DIRECTORY_X86 kernel_pagetable;
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extern PAGE_DIRECTORY_X86 kernel_pagetable;
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extern PAGE_DIRECTORY_X86 hyperspace_pagetable;
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extern PAGE_DIRECTORY_X86 apic_pagetable;
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extern PAGE_DIRECTORY_X86 apic_pagetable;
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extern PAGE_DIRECTORY_X86 kpcr_pagetable;
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extern PAGE_DIRECTORY_X86 kpcr_pagetable;
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extern PAGE_DIRECTORY_X86 kuser_pagetable;
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extern PAGE_DIRECTORY_X86 kuser_pagetable;
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@ -150,11 +149,6 @@ FrLdrSetupPageDirectory(VOID)
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PageDir->Pde[StartupPageTableIndex].Write = 1;
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PageDir->Pde[StartupPageTableIndex].Write = 1;
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PageDir->Pde[StartupPageTableIndex].PageFrameNumber = PaPtrToPfn(startup_pagedirectory);
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PageDir->Pde[StartupPageTableIndex].PageFrameNumber = PaPtrToPfn(startup_pagedirectory);
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/* Set up the Hyperspace PDE */
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PageDir->Pde[HyperspacePageTableIndex].Valid = 1;
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PageDir->Pde[HyperspacePageTableIndex].Write = 1;
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PageDir->Pde[HyperspacePageTableIndex].PageFrameNumber = PaPtrToPfn(hyperspace_pagetable);
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/* Set up the HAL PDE */
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/* Set up the HAL PDE */
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PageDir->Pde[HalPageTableIndex].Valid = 1;
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PageDir->Pde[HalPageTableIndex].Valid = 1;
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PageDir->Pde[HalPageTableIndex].Write = 1;
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PageDir->Pde[HalPageTableIndex].Write = 1;
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@ -34,7 +34,6 @@
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.globl _startup_pagedirectory
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.globl _startup_pagedirectory
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.globl _lowmem_pagetable
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.globl _lowmem_pagetable
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.globl _kernel_pagetable
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.globl _kernel_pagetable
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.globl _hyperspace_pagetable
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.globl _apic_pagetable
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.globl _apic_pagetable
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.globl _kpcr_pagetable
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.globl _kpcr_pagetable
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.globl _kuser_pagetable
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.globl _kuser_pagetable
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@ -64,9 +63,6 @@ _lowmem_pagetable:
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_kernel_pagetable:
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_kernel_pagetable:
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.fill 2*4096, 1, 0
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.fill 2*4096, 1, 0
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_hyperspace_pagetable:
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.fill 4096, 1, 0
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_apic_pagetable:
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_apic_pagetable:
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.fill 4096, 1, 0
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.fill 4096, 1, 0
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@ -41,13 +41,11 @@
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((p) >> PFN_SHIFT)
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((p) >> PFN_SHIFT)
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#define STARTUP_BASE 0xC0000000
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#define STARTUP_BASE 0xC0000000
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#define HYPERSPACE_BASE 0xC0400000
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#define HAL_BASE 0xFFC00000
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#define HAL_BASE 0xFFC00000
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#define APIC_BASE 0xFFFE0000
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#define APIC_BASE 0xFFFE0000
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#define LowMemPageTableIndex 0
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#define LowMemPageTableIndex 0
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#define StartupPageTableIndex (STARTUP_BASE >> 22)
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#define StartupPageTableIndex (STARTUP_BASE >> 22)
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#define HyperspacePageTableIndex (HYPERSPACE_BASE >> 22)
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#define HalPageTableIndex (HAL_BASE >> 22)
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#define HalPageTableIndex (HAL_BASE >> 22)
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typedef struct _PAGE_DIRECTORY_X86
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typedef struct _PAGE_DIRECTORY_X86
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@ -297,7 +297,8 @@ MmArmInitSystem(IN ULONG Phase,
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PageFrameIndex = MmGetContinuousPages(MmSizeOfNonPagedPoolInBytes,
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PageFrameIndex = MmGetContinuousPages(MmSizeOfNonPagedPoolInBytes,
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Low,
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Low,
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High,
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High,
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BoundaryAddressMultiple);
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BoundaryAddressMultiple,
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FALSE);
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ASSERT(PageFrameIndex != 0);
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ASSERT(PageFrameIndex != 0);
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DPRINT1("NP VA begins at: %p and ends at: %p\n",
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DPRINT1("NP VA begins at: %p and ends at: %p\n",
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MmNonPagedPoolStart,
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MmNonPagedPoolStart,
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@ -448,6 +449,34 @@ MmArmInitSystem(IN ULONG Phase,
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// Create the system PTE space
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// Create the system PTE space
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//
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//
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MiInitializeSystemPtes(PointerPte, MmNumberOfSystemPtes, SystemPteSpace);
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MiInitializeSystemPtes(PointerPte, MmNumberOfSystemPtes, SystemPteSpace);
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//
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// Get the PDE For hyperspace
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//
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StartPde = MiAddressToPde(HYPER_SPACE);
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//
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// Allocate a page for it and create it
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//
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PageFrameIndex = MmAllocPage(MC_SYSTEM, 0);
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TempPde.u.Hard.PageFrameNumber = PageFrameIndex;
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TempPde.u.Hard.Global = FALSE; // Hyperspace is local!
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ASSERT(StartPde->u.Hard.Valid == 0);
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ASSERT(TempPde.u.Hard.Valid == 1);
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*StartPde = TempPde;
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//
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// Zero out the page table now
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//
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PointerPte = MiAddressToPte(HYPER_SPACE);
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RtlZeroMemory(PointerPte, PAGE_SIZE);
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//
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// Setup the mapping PTEs
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//
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MmFirstReservedMappingPte = MiAddressToPte(MI_MAPPING_RANGE_START);
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MmLastReservedMappingPte = MiAddressToPte(MI_MAPPING_RANGE_END);
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MmFirstReservedMappingPte->u.Hard.PageFrameNumber = MI_HYPERSPACE_PTES;
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}
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}
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//
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//
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@ -26,6 +26,7 @@ extern ULONG MmSizeOfNonPagedPoolInBytes;
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extern ULONG MmMaximumNonPagedPoolInBytes;
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extern ULONG MmMaximumNonPagedPoolInBytes;
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extern PVOID MmNonPagedPoolStart;
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extern PVOID MmNonPagedPoolStart;
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extern PVOID MmNonPagedPoolExpansionStart;
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extern PVOID MmNonPagedPoolExpansionStart;
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extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
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VOID
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VOID
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NTAPI
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NTAPI
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/* GLOBALS ********************************************************************/
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/* GLOBALS ********************************************************************/
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PMMPTE MmFirstReservedMappingPte;
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PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
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PMMPTE MmLastReservedMappingPte;
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MMPTE HyperTemplatePte;
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MMPTE HyperTemplatePte;
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PEPROCESS HyperProcess;
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PEPROCESS HyperProcess;
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KIRQL HyperIrql;
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KIRQL HyperIrql;
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/* PRIVATE FUNCTIONS **********************************************************/
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/* PRIVATE FUNCTIONS **********************************************************/
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VOID
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NTAPI
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MiInitHyperSpace(VOID)
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{
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PMMPTE PointerPte;
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/* Get the hyperspace PTE and zero out the page table */
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PointerPte = MiAddressToPte(HYPER_SPACE);
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RtlZeroMemory(PointerPte, PAGE_SIZE);
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/* Setup mapping PTEs */
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MmFirstReservedMappingPte = MiAddressToPte(MI_MAPPING_RANGE_START);
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MmLastReservedMappingPte = MiAddressToPte(MI_MAPPING_RANGE_END);
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MmFirstReservedMappingPte->u.Hard.PageFrameNumber = MI_HYPERSPACE_PTES;
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}
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PVOID
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PVOID
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NTAPI
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NTAPI
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MiMapPageInHyperSpace(IN PEPROCESS Process,
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MiMapPageInHyperSpace(IN PEPROCESS Process,
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@ -375,9 +375,6 @@ MmInit1(VOID)
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/* Intialize system memory areas */
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/* Intialize system memory areas */
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MiInitSystemMemoryAreas();
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MiInitSystemMemoryAreas();
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/* Initialize hyperspace */
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MiInitHyperSpace();
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/* Initialize the page list */
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/* Initialize the page list */
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MmInitializePageList();
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MmInitializePageList();
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