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[NTOS:KE][HALX86] Implement AP startup code (#5879)

Browse source 
Co-authored-by: Victor Perevertkin <victor.perevertkin@reactos.org>

Introduce the initial changes needed to get other processors up and into kernel mode. 
This only supports x86 as of now but is the first real step towards using other system processors.
This commit is contained in:
Justin Miller 2023-11-19 15:51:33 -08:00 • committed by GitHub
parent 9e42809fc1
commit 516ccad340
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
30 changed files with 799 additions and 135 deletions
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4
hal/halx86/acpi/halacpi.c
View file

@ -851,12 +851,12 @@ HalpSetupAcpiPhase0(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
/* Allocate it */
HalpLowStubPhysicalAddress.QuadPart = HalpAllocPhysicalMemory(LoaderBlock,
0x100000,
1,
HALP_LOW_STUB_SIZE_IN_PAGES,
FALSE);
if (HalpLowStubPhysicalAddress.QuadPart)
{
/* Map it */
HalpLowStub = HalpMapPhysicalMemory64(HalpLowStubPhysicalAddress, 1);
HalpLowStub = HalpMapPhysicalMemory64(HalpLowStubPhysicalAddress, HALP_LOW_STUB_SIZE_IN_PAGES);
}
}

56
hal/halx86/apic/apicsmp.c
View file

@ -1,18 +1,23 @@
/*
* PROJECT: ReactOS HAL
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* FILE: hal/halx86/apic/apicsmp.c
* PURPOSE: SMP specific APIC code
* PROGRAMMERS: Copyright 2021 Timo Kreuzer (timo.kreuzer@reactos.org)
* COPYRIGHT: Copyright 2021 Timo Kreuzer <timo.kreuzer@reactos.org>
* Copyright 2023 Justin Miller <justin.miller@reactos.org>
*/
/* INCLUDES *******************************************************************/
#include <hal.h>
#include "apicp.h"
#include <smp.h>
#define NDEBUG
#include <debug.h>
extern PPROCESSOR_IDENTITY HalpProcessorIdentity;
/* INTERNAL FUNCTIONS *********************************************************/
/*!
@ -36,7 +41,7 @@
local APIC(s) specified in Destination field. Vector specifies
the startup address.
APIC_MT_ExtInt - Delivers an external interrupt to the target local
APIC specified in Destination field.
APIC specified in Destination field.
\param TriggerMode - The trigger mode of the interrupt. Can be:
APIC_TGM_Edge - The interrupt is edge triggered.
@ -62,8 +67,19 @@ ApicRequestGlobalInterrupt(
_In_ APIC_TGM TriggerMode,
_In_ APIC_DSH DestinationShortHand)
{
ULONG Flags;
APIC_INTERRUPT_COMMAND_REGISTER Icr;
/* Disable interrupts so that we can change IRR without being interrupted */
Flags = __readeflags();
_disable();
/* Wait for the APIC to be idle */
do
{
Icr.Long0 = ApicRead(APIC_ICR0);
} while (Icr.DeliveryStatus);
/* Setup the command register */
Icr.LongLong = 0;
Icr.Vector = Vector;
@ -79,18 +95,46 @@ ApicRequestGlobalInterrupt(
/* Write the low dword last to send the interrupt */
ApicWrite(APIC_ICR1, Icr.Long1);
ApicWrite(APIC_ICR0, Icr.Long0);
/* Finally, restore the original interrupt state */
if (Flags & EFLAGS_INTERRUPT_MASK)
{
_enable();
}
}
/* SMP SUPPORT FUNCTIONS ******************************************************/
// Should be called by SMP version of HalRequestIpi
VOID
NTAPI
HalpRequestIpi(KAFFINITY TargetProcessors)
HalpRequestIpi(_In_ KAFFINITY TargetProcessors)
{
UNIMPLEMENTED;
__debugbreak();
}
// APIC specific SMP code here
VOID
ApicStartApplicationProcessor(
_In_ ULONG NTProcessorNumber,
_In_ PHYSICAL_ADDRESS StartupLoc)
{
ASSERT(StartupLoc.HighPart == 0);
ASSERT((StartupLoc.QuadPart & 0xFFF) == 0);
ASSERT((StartupLoc.QuadPart & 0xFFF00FFF) == 0);
/* Init IPI */
ApicRequestGlobalInterrupt(HalpProcessorIdentity[NTProcessorNumber].LapicId, 0,
APIC_MT_INIT, APIC_TGM_Edge, APIC_DSH_Destination);
/* De-Assert Init IPI */
ApicRequestGlobalInterrupt(HalpProcessorIdentity[NTProcessorNumber].LapicId, 0,
APIC_MT_INIT, APIC_TGM_Level, APIC_DSH_Destination);
/* Stall execution for a bit to give APIC time: MPS Spec - B.4 */
KeStallExecutionProcessor(200);
/* Startup IPI */
ApicRequestGlobalInterrupt(HalpProcessorIdentity[NTProcessorNumber].LapicId, (StartupLoc.LowPart) >> 12,
APIC_MT_Startup, APIC_TGM_Edge, APIC_DSH_Destination);
}

23
hal/halx86/apic/processor.c
View file

@ -38,18 +38,6 @@ HalAllProcessorsStarted(VOID)
return TRUE;
}
/*
* @implemented
*/
BOOLEAN
NTAPI
HalStartNextProcessor(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
IN PKPROCESSOR_STATE ProcessorState)
{
/* Ready to start */
return FALSE;
}
/*
* @implemented
*/
@ -62,15 +50,4 @@ HalProcessorIdle(VOID)
__halt();
}
/*
* @implemented
*/
VOID
NTAPI
HalRequestIpi(KAFFINITY TargetProcessors)
{
UNIMPLEMENTED;
__debugbreak();
}
/* EOF */

34
hal/halx86/generic/up.c Normal file
View file

@ -0,0 +1,34 @@
/*
* PROJECT: ReactOS Kernel
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: Core source file for Uniprocessor (UP) alternative functions
* COPYRIGHT: Copyright 2021 Justin Miller <justinmiller100@gmail.com>
*/
/* INCLUDES ******************************************************************/
#include <hal.h>
#define NDEBUG
#include <debug.h>
/* FUNCTIONS *****************************************************************/
VOID
NTAPI
HalRequestIpi(
_In_ KAFFINITY TargetProcessors)
{
/* This should never be called in UP mode */
__debugbreak();
}
BOOLEAN
NTAPI
HalStartNextProcessor(
_In_ PLOADER_PARAMETER_BLOCK LoaderBlock,
_In_ PKPROCESSOR_STATE ProcessorState)
{
/* Always return false on UP systems */
return FALSE;
}

6
hal/halx86/include/halp.h
View file

@ -53,6 +53,12 @@ VOID
#define IDT_INTERNAL 0x11
#define IDT_DEVICE 0x21
#ifdef _M_AMD64
#define HALP_LOW_STUB_SIZE_IN_PAGES 5
#else
#define HALP_LOW_STUB_SIZE_IN_PAGES 3
#endif
/* Conversion functions */
#define BCD_INT(bcd) \
(((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))

12
hal/halx86/include/smp.h
View file

@ -41,3 +41,15 @@ HalpSetupProcessorsTable(
VOID
HalpPrintApicTables(VOID);
/* APIC specific functions inside apic/apicsmp.c */
VOID
ApicStartApplicationProcessor(
_In_ ULONG NTProcessorNumber,
_In_ PHYSICAL_ADDRESS StartupLoc);
VOID
NTAPI
HalpRequestIpi(
_In_ KAFFINITY TargetProcessors);

23
hal/halx86/pic/processor.c
View file

@ -38,18 +38,6 @@ HalAllProcessorsStarted(VOID)
return TRUE;
}
/*
* @implemented
*/
BOOLEAN
NTAPI
HalStartNextProcessor(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
IN PKPROCESSOR_STATE ProcessorState)
{
/* Ready to start */
return FALSE;
}
/*
* @implemented
*/
@ -62,15 +50,4 @@ HalProcessorIdle(VOID)
__halt();
}
/*
* @implemented
*/
VOID
NTAPI
HalRequestIpi(KAFFINITY TargetProcessors)
{
/* Not implemented on UP */
__debugbreak();
}
/* EOF */

18
hal/halx86/smp.cmake
View file

@ -2,8 +2,22 @@
list(APPEND HAL_SMP_SOURCE
generic/buildtype.c
generic/spinlock.c
smp/ipi.c
smp/smp.c)
add_library(lib_hal_smp OBJECT ${HAL_SMP_SOURCE})
add_dependencies(lib_hal_smp bugcodes xdk)
if(ARCH STREQUAL "i386")
list(APPEND HAL_SMP_ASM_SOURCE
smp/i386/apentry.S)
list(APPEND HAL_SMP_SOURCE
smp/i386/spinup.c)
elseif(ARCH STREQUAL "amd64")
list(APPEND HAL_SMP_ASM_SOURCE
smp/amd64/apentry.S)
list(APPEND HAL_SMP_SOURCE
smp/amd64/spinup.c)
endif()
add_asm_files(lib_hal_smp_asm ${HAL_SMP_ASM_SOURCE})
add_library(lib_hal_smp OBJECT ${HAL_SMP_SOURCE} ${lib_hal_smp_asm})
add_dependencies(lib_hal_smp bugcodes asm xdk)
target_compile_definitions(lib_hal_smp PRIVATE CONFIG_SMP)

34
hal/halx86/smp/amd64/apentry.S Normal file
View file

@ -0,0 +1,34 @@
/*
* PROJECT: ReactOS Kernel
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: AMD64 Application Processor (AP) spinup setup
* COPYRIGHT: Copyright 2023 Justin Miller <justin.miller@reactos.org>
*/
#include <asm.inc>
PUBLIC HalpAPEntry16
PUBLIC HalpAPEntryData
PUBLIC HalpAPEntry32
PUBLIC HalpAPEntry16End
.code
HalpAPEntry16:
cli
xor ax, ax
mov ds, ax
mov ss, ax
mov fs, ax
mov gs, ax
hlt
HalpAPEntry16End:
.long HEX(0)
HalpAPEntry32:
.long HEX(0)
HalpAPEntryData:
.long HEX(0)
END

24
hal/halx86/smp/amd64/spinup.c Normal file
View file

@ -0,0 +1,24 @@
/*
* PROJECT: ReactOS Kernel
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: AMD64 Application Processor (AP) spinup setup
* COPYRIGHT: Copyright 2023 Justin Miller <justin.miller@reactos.org>
*/
/* INCLUDES ******************************************************************/
#include <hal.h>
#include <smp.h>
#define NDEBUG
#include <debug.h>
BOOLEAN
NTAPI
HalStartNextProcessor(
_In_ PLOADER_PARAMETER_BLOCK LoaderBlock,
_In_ PKPROCESSOR_STATE ProcessorState)
{
//TODO:
return FALSE;
}

144
hal/halx86/smp/i386/apentry.S Normal file
View file

@ -0,0 +1,144 @@
/*
* PROJECT: ReactOS HAL
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: i386 Application Processor (AP) spinup setup
* COPYRIGHT: Copyright 2021 Victor Perevertkin <victor.perevertkin@reactos.org>
* Copyright 2021-2023 Justin Miller <justin.miller@reactos.org>
*/
#include <asm.inc>
#include <ks386.inc>
#define ZERO_OFFSET(f) (f - _HalpAPEntry16)
#define PS(f) (f - _HalpAPEntryData)
PUBLIC _HalpAPEntry16
PUBLIC _HalpAPEntryData
PUBLIC _HalpAPEntry32
PUBLIC _HalpAPEntry16End
.code16
_HalpAPEntry16:
cli
/* Calculate the flat base address */
mov ebp, cs
shl ebp, 4
/* Use flat addressing */
xor eax, eax
mov ds, eax
#ifdef _USE_ML
data32 lgdt fword ptr cs:[ZERO_OFFSET(Gdtr)]
data32 lidt fword ptr cs:[ZERO_OFFSET(Idtr)]
#else
data32 lgdt cs:[ZERO_OFFSET(Gdtr)]
data32 lidt cs:[ZERO_OFFSET(Idtr)]
#endif
/* Load temp page table */
mov eax, cs:[ZERO_OFFSET(PageTableRoot)]
mov cr3, eax
mov eax, cr0
or eax, HEX(80000001) /* CR0_PG | CR0_PE */
mov cr0, eax
.align 4
/* Long jump, 32bit address */
.byte HEX(66)
.byte HEX(EA)
_HalpAPEntryData:
_APEntryJump32Offset:
.long 0
_APEntryJump32Segment:
.long 8
SelfPtr:
.long 0
PageTableRoot:
.long 0
ProcessorState:
.long 0
Gdtr_Pad:
.short 0 // Pad
Gdtr:
.short 0 // Limit
.long 0 // Base
Idtr_Pad:
.short 0 // Pad
Idtr:
.short 0 // Limit
.long 0 // Base
_HalpAPEntry16End:
.endcode16
.code32
_HalpAPEntry32:
/* Set the Ring 0 DS/ES/SS Segment */
mov ax, HEX(10)
mov ds, ax
mov es, ax
mov ss, ax
mov gs, ax
/* Load ProcessorState pointer */
mov esi, [ebp + ZERO_OFFSET(ProcessorState)]
mov eax, [esi + PsContextFrame + CsSegDs]
mov ds, eax
mov eax, [esi + PsContextFrame + CsSegEs]
mov es, eax
mov eax, [esi + PsContextFrame + CsSegSs]
mov ss, eax
mov eax, [esi + PsContextFrame + CsSegFs]
mov fs, eax
mov eax, [esi + PsContextFrame + CsSegGs]
mov gs, eax
/* Write CR registers with ProcessorState values */
mov eax, [esi + PsSpecialRegisters + SrCr3]
mov cr3, eax
mov eax, [esi + PsSpecialRegisters + SrCr4]
mov cr4, eax
/* Load debug registers */
mov eax, [esi + PsSpecialRegisters + SrKernelDr0]
mov dr0, eax
mov eax, [esi + PsSpecialRegisters + SrKernelDr1]
mov dr1, eax
mov eax, [esi + PsSpecialRegisters + SrKernelDr2]
mov dr2, eax
mov eax, [esi + PsSpecialRegisters + SrKernelDr3]
mov dr3, eax
mov eax, [esi + PsSpecialRegisters + SrKernelDr6]
mov dr6, eax
mov eax, [esi + PsSpecialRegisters + SrKernelDr7]
mov dr7, eax
/* Load TSS */
ltr word ptr [esi + PsSpecialRegisters + SrTr]
/* Load AP Stack */
mov esp, [esi + PsContextFrame + CsEsp]
/* Load Eip and push it as a "return" address */
mov eax, [esi + PsContextFrame + CsEip]
push eax
/* Load flags */
mov eax, [esi + PsContextFrame + CsEflags]
sahf
/* Set up all GP registers */
xor edi, edi
xor esi, esi
xor ebp, ebp
xor ebx, ebx
xor edx, edx
xor ecx, ecx
xor eax, eax
/* Jump into the kernel */
ret
END

121
hal/halx86/smp/i386/spinup.c Normal file
View file

@ -0,0 +1,121 @@
/*
* PROJECT: ReactOS Kernel
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: i386 Application Processor (AP) spinup setup
* COPYRIGHT: Copyright 2021 Victor Perevertkin <victor.perevertkin@reactos.org>
* Copyright 2021-2023 Justin Miller <justin.miller@reactos.org>
*/
/* INCLUDES ******************************************************************/
#include <hal.h>
#include <smp.h>
#define NDEBUG
#include <debug.h>
/* GLOBALS *******************************************************************/
extern PPROCESSOR_IDENTITY HalpProcessorIdentity;
extern PHYSICAL_ADDRESS HalpLowStubPhysicalAddress;
extern PVOID HalpLowStub;
// The data necessary for a boot (stored inside HalpLowStub)
extern PVOID HalpAPEntry16;
extern PVOID HalpAPEntryData;
extern PVOID HalpAPEntry32;
extern PVOID HalpAPEntry16End;
extern HALP_APIC_INFO_TABLE HalpApicInfoTable;
ULONG HalpStartedProcessorCount = 1;
#ifndef Add2Ptr
#define Add2Ptr(P,I) ((PVOID)((PUCHAR)(P) + (I)))
#endif
#ifndef PtrOffset
#define PtrOffset(B,O) ((ULONG)((ULONG_PTR)(O) - (ULONG_PTR)(B)))
#endif
typedef struct _AP_ENTRY_DATA
{
UINT32 Jump32Offset;
ULONG Jump32Segment;
PVOID SelfPtr;
ULONG PageTableRoot;
PKPROCESSOR_STATE ProcessorState;
KDESCRIPTOR Gdtr;
KDESCRIPTOR Idtr;
} AP_ENTRY_DATA, *PAP_ENTRY_DATA;
/* FUNCTIONS *****************************************************************/
static
ULONG
HalpSetupTemporaryMappings(
_In_ PKPROCESSOR_STATE ProcessorState)
{
PMMPDE RootPageTable = Add2Ptr(HalpLowStub, PAGE_SIZE);
PMMPDE LowMapPde = Add2Ptr(HalpLowStub, 2 * PAGE_SIZE);
PMMPTE LowStubPte = MiAddressToPte(HalpLowStub);
PHYSICAL_ADDRESS PhysicalAddress;
ULONG StartPti;
/* Copy current mappings */
RtlCopyMemory(RootPageTable, MiAddressToPde(NULL), PAGE_SIZE);
/* Set up low PDE */
PhysicalAddress = MmGetPhysicalAddress(LowMapPde);
RootPageTable[0].u.Hard.PageFrameNumber = PhysicalAddress.QuadPart >> PAGE_SHIFT;
RootPageTable[0].u.Hard.Valid = 1;
RootPageTable[0].u.Hard.Write = 1;
/* Copy low stub PTEs */
StartPti = MiAddressToPteOffset(HalpLowStubPhysicalAddress.QuadPart);
ASSERT(StartPti + HALP_LOW_STUB_SIZE_IN_PAGES < 1024);
for (ULONG i = 0; i < HALP_LOW_STUB_SIZE_IN_PAGES; i++)
{
LowMapPde[StartPti + i] = LowStubPte[i];
}
PhysicalAddress = MmGetPhysicalAddress(RootPageTable);
ASSERT(PhysicalAddress.QuadPart < 0x100000000);
return (ULONG)PhysicalAddress.QuadPart;
}
BOOLEAN
NTAPI
HalStartNextProcessor(
_In_ PLOADER_PARAMETER_BLOCK LoaderBlock,
_In_ PKPROCESSOR_STATE ProcessorState)
{
if (HalpStartedProcessorCount == HalpApicInfoTable.ProcessorCount)
return FALSE;
// Initalize the temporary page table
// TODO: clean it up after an AP boots successfully
ULONG initialCr3 = HalpSetupTemporaryMappings(ProcessorState);
if (!initialCr3)
return FALSE;
// Put the bootstrap code into low memory
RtlCopyMemory(HalpLowStub, &HalpAPEntry16, (ULONG_PTR)&HalpAPEntry16End - (ULONG_PTR)&HalpAPEntry16);
// Get a pointer to apEntryData
PAP_ENTRY_DATA apEntryData = (PVOID)((ULONG_PTR)HalpLowStub + ((ULONG_PTR)&HalpAPEntryData - (ULONG_PTR)&HalpAPEntry16));
*apEntryData = (AP_ENTRY_DATA){
.Jump32Offset = (ULONG)&HalpAPEntry32,
.Jump32Segment = (ULONG)ProcessorState->ContextFrame.SegCs,
.SelfPtr = (PVOID)apEntryData,
.PageTableRoot = initialCr3,
.ProcessorState = ProcessorState,
.Gdtr = ProcessorState->SpecialRegisters.Gdtr,
.Idtr = ProcessorState->SpecialRegisters.Idtr,
};
ApicStartApplicationProcessor(HalpStartedProcessorCount, HalpLowStubPhysicalAddress);
HalpStartedProcessorCount++;
return TRUE;
}

24
hal/halx86/smp/ipi.c Normal file
View file

@ -0,0 +1,24 @@
/*
* PROJECT: ReactOS Kernel
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: Source file for Inter-Processor Interrupts management
* COPYRIGHT: Copyright 2023 Justin Miller <justin.miller@reactos.org>
*/
/* INCLUDES ******************************************************************/
#include <hal.h>
#include <smp.h>
#define NDEBUG
#include <debug.h>
/* GLOBALS *******************************************************************/
VOID
NTAPI
HalRequestIpi(
_In_ KAFFINITY TargetProcessors)
{
HalpRequestIpi(TargetProcessors);
}

4
hal/halx86/smp/smp.c
View file

@ -2,13 +2,15 @@
* PROJECT: ReactOS Kernel
* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
* PURPOSE: Core source file for SMP management
* COPYRIGHT: Copyright 2021 Justin Miller <justinmiller100@gmail.com>
* COPYRIGHT: Copyright 2021 Victor Perevertkin <victor.perevertkin@reactos.org>
* Copyright 2021-2023 Justin Miller <justin.miller@reactos.org>
*/
/* INCLUDES ******************************************************************/
#include <hal.h>
#include <smp.h>
#define NDEBUG
#include <debug.h>

3
hal/halx86/up.cmake
View file

@ -1,7 +1,8 @@
list(APPEND HAL_UP_SOURCE
generic/buildtype.c
generic/spinlock.c)
generic/spinlock.c
generic/up.c)
add_library(lib_hal_up OBJECT ${HAL_UP_SOURCE})
add_dependencies(lib_hal_up bugcodes xdk)