mirror of
https://github.com/reactos/reactos.git
synced 2024-10-06 09:24:11 +00:00
[usb/usbehci]:
- Reorganization code to put hardware related structures and routines in own source files. - Modify ResetPort to correctly reset the port instead of the controller. - Implement allocating chunks of memory from the Common Buffer for use with the rest of source code. svn path=/trunk/; revision=50223
This commit is contained in:
parent
c1d677d16a
commit
4eef1c1925
275
reactos/drivers/usb/usbehci/hardware.c
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275
reactos/drivers/usb/usbehci/hardware.c
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/*
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* PROJECT: ReactOS Universal Serial Bus Bulk Enhanced Host Controller Interface
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: drivers/usb/usbehci/hardware.c
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* PURPOSE: Hardware related routines.
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* PROGRAMMERS:
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* Michael Martin (michael.martin@reactos.org)
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*/
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#include "hardware.h"
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#define NDEBUG
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#include <debug.h>
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//FORCEINLINE
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VOID
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SetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_ASYNCLISTBASE), PhysicalAddr);
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}
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//FORCEINLINE
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ULONG
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GetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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return READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_ASYNCLISTBASE));
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}
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//FORCEINLINE
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VOID
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SetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_PERIODICLISTBASE), PhysicalAddr);
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}
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//FORCEINLINE
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ULONG
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GetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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return READ_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_PERIODICLISTBASE));
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}
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//FORCEINLINE
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ULONG
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ReadControllerStatus(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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return READ_REGISTER_ULONG ((PULONG) (OpRegisters + EHCI_USBSTS));
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}
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//FORCEINLINE
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VOID
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ClearControllerStatus(PEHCI_HOST_CONTROLLER hcd, ULONG Status)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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WRITE_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBSTS), Status);
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}
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VOID
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ResetPort(PEHCI_HOST_CONTROLLER hcd, UCHAR Port)
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{
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ULONG tmp;
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ULONG OpRegisters = hcd->OpRegisters;
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DPRINT1("Reset Port %x\n", Port);
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tmp = READ_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)));
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if (tmp & 0x400)
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{
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DPRINT1("Non HighSpeed device connected. Releasing ownership.\n");
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WRITE_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)), 0x2000);
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}
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/* Get current port state */
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tmp = READ_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)));
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/* Set reset and clear enable */
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tmp |= 0x100;
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tmp &= ~0x04;
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WRITE_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)), tmp);
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/* USB 2.0 Spec 10.2.8.1, more than 50ms */
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KeStallExecutionProcessor(100);
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/* Clear reset */
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tmp &= ~0x100;
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WRITE_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)), tmp);
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KeStallExecutionProcessor(100);
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tmp = READ_REGISTER_ULONG((PULONG) ((OpRegisters + EHCI_PORTSC) + (4 * Port)));
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if (tmp & 0x100)
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{
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DPRINT1("EHCI ERROR: Port Reset did not complete!\n");
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}
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}
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VOID
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StopEhci(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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PEHCI_USBCMD_CONTENT UsbCmd;
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PEHCI_USBSTS_CONTEXT UsbSts;
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LONG FailSafe;
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LONG tmp;
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DPRINT1("Stopping Ehci controller\n");
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WRITE_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBINTR), 0);
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tmp = READ_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBCMD));
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UsbCmd = (PEHCI_USBCMD_CONTENT) & tmp;
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UsbCmd->Run = FALSE;
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WRITE_REGISTER_ULONG((PULONG) (OpRegisters + EHCI_USBCMD), tmp);
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/* Wait for the device to stop */
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for (FailSafe = 100; FailSafe > 1; FailSafe++)
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{
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KeStallExecutionProcessor(10);
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tmp = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS));
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UsbSts = (PEHCI_USBSTS_CONTEXT)&tmp;
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if (UsbSts->HCHalted)
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{
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break;
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}
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}
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if (!UsbSts->HCHalted)
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DPRINT1("EHCI ERROR: Controller is not responding to Stop request!\n");
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}
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VOID
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StartEhci(PEHCI_HOST_CONTROLLER hcd)
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{
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ULONG OpRegisters = hcd->OpRegisters;
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PEHCI_USBCMD_CONTENT UsbCmd;
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PEHCI_USBSTS_CONTEXT UsbSts;
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LONG FailSafe;
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LONG tmp;
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LONG tmp2;
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DPRINT("Starting Ehci controller\n");
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tmp = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS));
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UsbSts = (PEHCI_USBSTS_CONTEXT)&tmp;
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if (!UsbSts->HCHalted)
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{
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StopEhci(hcd);
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}
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tmp = READ_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBCMD));
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/* Reset the device */
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UsbCmd = (PEHCI_USBCMD_CONTENT) &tmp;
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UsbCmd->HCReset = TRUE;
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WRITE_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Wait for the device to reset */
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for (FailSafe = 100; FailSafe > 1; FailSafe++)
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{
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KeStallExecutionProcessor(10);
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tmp = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD));
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UsbCmd = (PEHCI_USBCMD_CONTENT)&tmp;
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if (!UsbCmd->HCReset)
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{
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break;
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}
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DPRINT("Waiting for reset, USBCMD: %x\n", READ_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBCMD)));
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}
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if (UsbCmd->HCReset)
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{
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DPRINT1("EHCI ERROR: Controller failed to reset! Will attempt to continue.\n");
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}
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UsbCmd = (PEHCI_USBCMD_CONTENT) &tmp;
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/* Disable Interrupts on the device */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBINTR), 0);
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/* Clear the Status */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS), 0x0000001f);
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_CTRLDSSEGMENT), 0);
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SetAsyncListQueueRegister(hcd, hcd->AsyncListQueue->PhysicalAddr | QH_TYPE_QH);
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/* Set the ansync and periodic to disable */
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UsbCmd->PeriodicEnable = FALSE;
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UsbCmd->AsyncEnable = TRUE;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Set the threshold */
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UsbCmd->IntThreshold = 1;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Turn back on interrupts */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBINTR),
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EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR
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/*| EHCI_USBINTR_FLROVR*/ | EHCI_USBINTR_PC);
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBINTR),
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EHCI_USBINTR_INTE | EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR
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/*| EHCI_USBINTR_FLROVR*/ | EHCI_USBINTR_PC);
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UsbCmd->Run = TRUE;
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBCMD), tmp);
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/* Wait for the device to start */
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for (;;)
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{
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KeStallExecutionProcessor(10);
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tmp2 = READ_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_USBSTS));
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UsbSts = (PEHCI_USBSTS_CONTEXT)&tmp2;
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if (!UsbSts->HCHalted)
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{
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break;
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}
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DPRINT("Waiting for start, USBSTS: %x\n", READ_REGISTER_ULONG ((PULONG)(OpRegisters + EHCI_USBSTS)));
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}
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/* Set all port routing to ECHI controller */
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WRITE_REGISTER_ULONG((PULONG)(OpRegisters + EHCI_CONFIGFLAG), 1);
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}
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VOID
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GetCapabilities(PEHCI_CAPS PCap, ULONG CapRegister)
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{
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PEHCI_HCS_CONTENT PHCS;
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LONG i;
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if (!PCap)
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return;
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PCap->Length = READ_REGISTER_UCHAR((PUCHAR)CapRegister);
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PCap->Reserved = READ_REGISTER_UCHAR((PUCHAR)(CapRegister + 1));
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PCap->HCIVersion = READ_REGISTER_USHORT((PUSHORT)(CapRegister + 2));
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PCap->HCSParamsLong = READ_REGISTER_ULONG((PULONG)(CapRegister + 4));
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PCap->HCCParams = READ_REGISTER_ULONG((PULONG)(CapRegister + 8));
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DPRINT1("Length %d\n", PCap->Length);
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DPRINT1("Reserved %d\n", PCap->Reserved);
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DPRINT1("HCIVersion %x\n", PCap->HCIVersion);
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DPRINT1("HCSParams %x\n", PCap->HCSParamsLong);
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DPRINT1("HCCParams %x\n", PCap->HCCParams);
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if (PCap->HCCParams & 0x02)
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DPRINT1("Frame list size is configurable\n");
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if (PCap->HCCParams & 0x01)
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DPRINT1("64bit address mode not supported!\n");
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DPRINT1("Number of Ports: %d\n", PCap->HCSParams.PortCount);
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if (PCap->HCSParams.PortPowerControl)
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DPRINT1("Port Power Control is enabled\n");
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if (!PCap->HCSParams.CHCCount)
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{
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DPRINT1("Number of Companion Host controllers %x\n", PCap->HCSParams.CHCCount);
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DPRINT1("Number of Ports Per CHC: %d\n", PCap->HCSParams.PortPerCHC);
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}
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PHCS = (PEHCI_HCS_CONTENT)&PCap->HCSParams;
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if (PHCS->PortRouteRules)
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{
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for (i = 0; i < PCap->HCSParams.PortCount; i++)
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{
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PCap->PortRoute[i] = READ_REGISTER_UCHAR((PUCHAR) (CapRegister + 12 + i));
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}
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}
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}
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307
reactos/drivers/usb/usbehci/hardware.h
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307
reactos/drivers/usb/usbehci/hardware.h
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#pragma once
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#include <ntddk.h>
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/* USB Command Register */
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#define EHCI_USBCMD 0x00
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#define EHCI_USBSTS 0x04
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#define EHCI_USBINTR 0x08
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#define EHCI_FRINDEX 0x0C
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#define EHCI_CTRLDSSEGMENT 0x10
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#define EHCI_PERIODICLISTBASE 0x14
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#define EHCI_ASYNCLISTBASE 0x18
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#define EHCI_CONFIGFLAG 0x40
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#define EHCI_PORTSC 0x44
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/* USB Interrupt Register Flags 32 Bits */
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#define EHCI_USBINTR_INTE 0x01
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#define EHCI_USBINTR_ERR 0x02
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#define EHCI_USBINTR_PC 0x04
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#define EHCI_USBINTR_FLROVR 0x08
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#define EHCI_USBINTR_HSERR 0x10
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#define EHCI_USBINTR_ASYNC 0x20
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/* Bits 6:31 Reserved */
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/* Status Register Flags 32 Bits */
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#define EHCI_STS_INT 0x01
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#define EHCI_STS_ERR 0x02
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#define EHCI_STS_PCD 0x04
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#define EHCI_STS_FLR 0x08
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#define EHCI_STS_FATAL 0x10
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#define EHCI_STS_IAA 0x20
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/* Bits 11:6 Reserved */
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#define EHCI_STS_HALT 0x1000
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#define EHCI_STS_RECL 0x2000
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#define EHCI_STS_PSS 0x4000
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#define EHCI_STS_ASS 0x8000
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#define EHCI_ERROR_INT ( EHCI_STS_FATAL | EHCI_STS_ERR )
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/* Last bit in QUEUE ELEMENT TRANSFER DESCRIPTOR Next Pointer */
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/* Used for Queue Element Transfer Descriptor Pointers
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and Queue Head Horizontal Link Pointers */
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#define TERMINATE_POINTER 0x01
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/* QUEUE ELEMENT TRANSFER DESCRIPTOR, Token defines and structs */
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/* PIDCodes for QETD_TOKEN
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OR with QUEUE_TRANSFER_DESCRIPTOR Token.PIDCode*/
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#define PID_CODE_OUT_TOKEN 0x00
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#define PID_CODE_IN_TOKEN 0x01
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#define PID_CODE_SETUP_TOKEN 0x02
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/* Split Transaction States
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OR with QUEUE_TRANSFER_DESCRIPTOR Token.SplitTransactionState */
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#define DO_START_SPLIT 0x00
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#define DO_COMPLETE_SPLIT 0x01
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/* Ping States, OR with QUEUE_TRANSFER_DESCRIPTOR Token. */
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#define PING_STATE_DO_OUT 0x00
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#define PING_STATE_DO_PING 0x01
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typedef struct _PERIODICFRAMELIST
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{
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PULONG VirtualAddr;
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PHYSICAL_ADDRESS PhysicalAddr;
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ULONG Size;
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} PERIODICFRAMELIST, *PPERIODICFRAMELIST;
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/* QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN */
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typedef struct _QETD_TOKEN_BITS
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{
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ULONG PingState:1;
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ULONG SplitTransactionState:1;
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ULONG MissedMicroFrame:1;
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ULONG TransactionError:1;
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ULONG BabbleDetected:1;
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||||||
|
ULONG DataBufferError:1;
|
||||||
|
ULONG Halted:1;
|
||||||
|
ULONG Active:1;
|
||||||
|
ULONG PIDCode:2;
|
||||||
|
ULONG ErrorCounter:2;
|
||||||
|
ULONG CurrentPage:3;
|
||||||
|
ULONG InterruptOnComplete:1;
|
||||||
|
ULONG TotalBytesToTransfer:15;
|
||||||
|
ULONG DataToggle:1;
|
||||||
|
} QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
|
||||||
|
|
||||||
|
/* QUEUE ELEMENT TRANSFER DESCRIPTOR */
|
||||||
|
typedef struct _QUEUE_TRANSFER_DESCRIPTOR
|
||||||
|
{
|
||||||
|
//Hardware
|
||||||
|
ULONG NextPointer;
|
||||||
|
ULONG AlternateNextPointer;
|
||||||
|
union
|
||||||
|
{
|
||||||
|
QETD_TOKEN_BITS Bits;
|
||||||
|
ULONG DWord;
|
||||||
|
} Token;
|
||||||
|
ULONG BufferPointer[5];
|
||||||
|
|
||||||
|
//Software
|
||||||
|
ULONG PhysicalAddr;
|
||||||
|
struct _QUEUE_TRANSFER_DESCRIPTOR *PreviousDescriptor;
|
||||||
|
struct _QUEUE_TRANSFER_DESCRIPTOR *NextDescriptor;
|
||||||
|
} QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
|
||||||
|
|
||||||
|
/* EndPointSpeeds of END_POINT_CHARACTERISTICS */
|
||||||
|
#define QH_ENDPOINT_FULLSPEED 0x00
|
||||||
|
#define QH_ENDPOINT_LOWSPEED 0x01
|
||||||
|
#define QH_ENDPOINT_HIGHSPEED 0x02
|
||||||
|
|
||||||
|
typedef struct _END_POINT_CHARACTERISTICS
|
||||||
|
{
|
||||||
|
ULONG DeviceAddress:7;
|
||||||
|
ULONG InactiveOnNextTransaction:1;
|
||||||
|
ULONG EndPointNumber:4;
|
||||||
|
ULONG EndPointSpeed:2;
|
||||||
|
ULONG QEDTDataToggleControl:1;
|
||||||
|
ULONG HeadOfReclamation:1;
|
||||||
|
ULONG MaximumPacketLength:11;
|
||||||
|
ULONG ControlEndPointFlag:1;
|
||||||
|
ULONG NakCountReload:4;
|
||||||
|
} END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
|
||||||
|
|
||||||
|
typedef struct _END_POINT_CAPABILITIES
|
||||||
|
{
|
||||||
|
ULONG InterruptScheduleMask:8;
|
||||||
|
ULONG SplitCompletionMask:8;
|
||||||
|
ULONG HubAddr:6;
|
||||||
|
ULONG PortNumber:6;
|
||||||
|
/* Multi */
|
||||||
|
ULONG NumberOfTransactionPerFrame:2;
|
||||||
|
} END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
|
||||||
|
|
||||||
|
|
||||||
|
/* QUEUE HEAD defines and structs */
|
||||||
|
|
||||||
|
/* QUEUE HEAD Select Types, OR with QUEUE_HEAD HorizontalLinkPointer */
|
||||||
|
#define QH_TYPE_IDT 0x00
|
||||||
|
#define QH_TYPE_QH 0x02
|
||||||
|
#define QH_TYPE_SITD 0x04
|
||||||
|
#define QH_TYPE_FSTN 0x06
|
||||||
|
|
||||||
|
/* QUEUE HEAD */
|
||||||
|
typedef struct _QUEUE_HEAD
|
||||||
|
{
|
||||||
|
//Hardware
|
||||||
|
ULONG HorizontalLinkPointer;
|
||||||
|
END_POINT_CHARACTERISTICS EndPointCharacteristics;
|
||||||
|
END_POINT_CAPABILITIES EndPointCapabilities;
|
||||||
|
/* TERMINATE_POINTER not valid for this member */
|
||||||
|
ULONG CurrentLinkPointer;
|
||||||
|
/* TERMINATE_POINTER valid */
|
||||||
|
ULONG NextPointer;
|
||||||
|
/* TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTER */
|
||||||
|
ULONG AlternateNextPointer;
|
||||||
|
/* Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid */
|
||||||
|
union
|
||||||
|
{
|
||||||
|
QETD_TOKEN_BITS Bits;
|
||||||
|
ULONG DWord;
|
||||||
|
} Token;
|
||||||
|
ULONG BufferPointer[5];
|
||||||
|
|
||||||
|
//Software
|
||||||
|
ULONG PhysicalAddr;
|
||||||
|
struct _QUEUE_HEAD *PreviousQueueHead;
|
||||||
|
struct _QUEUE_HEAD *NextQueueHead;
|
||||||
|
PQUEUE_TRANSFER_DESCRIPTOR TransferDescriptor;
|
||||||
|
PIRP IrpToComplete;
|
||||||
|
PMDL MdlToFree;
|
||||||
|
PKEVENT Event;
|
||||||
|
} QUEUE_HEAD, *PQUEUE_HEAD;
|
||||||
|
|
||||||
|
/* USBCMD register 32 bits */
|
||||||
|
typedef struct _EHCI_USBCMD_CONTENT
|
||||||
|
{
|
||||||
|
ULONG Run : 1;
|
||||||
|
ULONG HCReset : 1;
|
||||||
|
ULONG FrameListSize : 2;
|
||||||
|
ULONG PeriodicEnable : 1;
|
||||||
|
ULONG AsyncEnable : 1;
|
||||||
|
ULONG DoorBell : 1;
|
||||||
|
ULONG LightReset : 1;
|
||||||
|
ULONG AsyncParkCount : 2;
|
||||||
|
ULONG Reserved : 1;
|
||||||
|
ULONG AsyncParkEnable : 1;
|
||||||
|
ULONG Reserved1 : 4;
|
||||||
|
ULONG IntThreshold : 8;
|
||||||
|
ULONG Reserved2 : 8;
|
||||||
|
|
||||||
|
} EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
|
||||||
|
|
||||||
|
typedef struct _EHCI_USBSTS_CONTENT
|
||||||
|
{
|
||||||
|
ULONG USBInterrupt:1;
|
||||||
|
ULONG ErrorInterrupt:1;
|
||||||
|
ULONG DetectChangeInterrupt:1;
|
||||||
|
ULONG FrameListRolloverInterrupt:1;
|
||||||
|
ULONG HostSystemErrorInterrupt:1;
|
||||||
|
ULONG AsyncAdvanceInterrupt:1;
|
||||||
|
ULONG Reserved:6;
|
||||||
|
ULONG HCHalted:1;
|
||||||
|
ULONG Reclamation:1;
|
||||||
|
ULONG PeriodicScheduleStatus:1;
|
||||||
|
ULONG AsynchronousScheduleStatus:1;
|
||||||
|
} EHCI_USBSTS_CONTEXT, *PEHCI_USBSTS_CONTEXT;
|
||||||
|
|
||||||
|
typedef struct _EHCI_USBPORTSC_CONTENT
|
||||||
|
{
|
||||||
|
ULONG CurrentConnectStatus:1;
|
||||||
|
ULONG ConnectStatusChange:1;
|
||||||
|
ULONG PortEnabled:1;
|
||||||
|
ULONG PortEnableChanged:1;
|
||||||
|
ULONG OverCurrentActive:1;
|
||||||
|
ULONG OverCurrentChange:1;
|
||||||
|
ULONG ForcePortResume:1;
|
||||||
|
ULONG Suspend:1;
|
||||||
|
ULONG PortReset:1;
|
||||||
|
ULONG Reserved:1;
|
||||||
|
ULONG LineStatus:2;
|
||||||
|
ULONG PortPower:1;
|
||||||
|
ULONG PortOwner:1;
|
||||||
|
} EHCI_USBPORTSC_CONTENT, *PEHCI_USBPORTSC_CONTENT;
|
||||||
|
|
||||||
|
typedef struct _EHCI_HCS_CONTENT
|
||||||
|
{
|
||||||
|
ULONG PortCount : 4;
|
||||||
|
ULONG PortPowerControl: 1;
|
||||||
|
ULONG Reserved : 2;
|
||||||
|
ULONG PortRouteRules : 1;
|
||||||
|
ULONG PortPerCHC : 4;
|
||||||
|
ULONG CHCCount : 4;
|
||||||
|
ULONG PortIndicator : 1;
|
||||||
|
ULONG Reserved2 : 3;
|
||||||
|
ULONG DbgPortNum : 4;
|
||||||
|
ULONG Reserved3 : 8;
|
||||||
|
|
||||||
|
} EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
|
||||||
|
|
||||||
|
typedef struct _EHCI_HCC_CONTENT
|
||||||
|
{
|
||||||
|
ULONG CurAddrBits : 1;
|
||||||
|
ULONG VarFrameList : 1;
|
||||||
|
ULONG ParkMode : 1;
|
||||||
|
ULONG Reserved : 1;
|
||||||
|
ULONG IsoSchedThreshold : 4;
|
||||||
|
ULONG EECPCapable : 8;
|
||||||
|
ULONG Reserved2 : 16;
|
||||||
|
|
||||||
|
} EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
|
||||||
|
|
||||||
|
typedef struct _EHCI_CAPS {
|
||||||
|
UCHAR Length;
|
||||||
|
UCHAR Reserved;
|
||||||
|
USHORT HCIVersion;
|
||||||
|
union
|
||||||
|
{
|
||||||
|
EHCI_HCS_CONTENT HCSParams;
|
||||||
|
ULONG HCSParamsLong;
|
||||||
|
};
|
||||||
|
ULONG HCCParams;
|
||||||
|
UCHAR PortRoute [8];
|
||||||
|
} EHCI_CAPS, *PEHCI_CAPS;
|
||||||
|
|
||||||
|
typedef struct _EHCI_HOST_CONTROLLER
|
||||||
|
{
|
||||||
|
ULONG OpRegisters;
|
||||||
|
EHCI_CAPS ECHICaps;
|
||||||
|
PVOID CommonBufferVA;
|
||||||
|
PHYSICAL_ADDRESS CommonBufferPA;
|
||||||
|
ULONG CommonBufferSize;
|
||||||
|
PQUEUE_HEAD AsyncListQueue;
|
||||||
|
KSPIN_LOCK Lock;
|
||||||
|
} EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
|
||||||
|
|
||||||
|
ULONG
|
||||||
|
ReadControllerStatus(PEHCI_HOST_CONTROLLER hcd);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
ClearControllerStatus(PEHCI_HOST_CONTROLLER hcd, ULONG Status);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
GetCapabilities(PEHCI_CAPS PCap, ULONG CapRegister);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
ResetPort(PEHCI_HOST_CONTROLLER hcd, UCHAR Port);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
StartEhci(PEHCI_HOST_CONTROLLER hcd);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
StopEhci(PEHCI_HOST_CONTROLLER hcd);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
SetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr);
|
||||||
|
|
||||||
|
ULONG
|
||||||
|
GetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
SetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr);
|
||||||
|
|
||||||
|
ULONG
|
||||||
|
GetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd);
|
||||||
|
|
94
reactos/drivers/usb/usbehci/physmem.c
Normal file
94
reactos/drivers/usb/usbehci/physmem.c
Normal file
|
@ -0,0 +1,94 @@
|
||||||
|
/*
|
||||||
|
* PROJECT: ReactOS Universal Serial Bus Bulk Enhanced Host Controller Interface
|
||||||
|
* LICENSE: GPL - See COPYING in the top level directory
|
||||||
|
* FILE: drivers/usb/usbehci/physmem.c
|
||||||
|
* PURPOSE: Common Buffer routines.
|
||||||
|
* PROGRAMMERS:
|
||||||
|
* Michael Martin (michael.martin@reactos.org)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "physmem.h"
|
||||||
|
#include "debug.h"
|
||||||
|
|
||||||
|
#define SMALL_ALLOCATION_SIZE 32
|
||||||
|
|
||||||
|
VOID
|
||||||
|
DumpPages()
|
||||||
|
{
|
||||||
|
//PMEM_HEADER MemBlock = (PMEM_HEADER)EhciSharedMemory.VirtualAddr;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Returns Virtual Address of Allocated Memory
|
||||||
|
ULONG
|
||||||
|
AllocateMemory(PEHCI_HOST_CONTROLLER hcd, ULONG Size, ULONG *PhysicalAddress)
|
||||||
|
{
|
||||||
|
PMEM_HEADER MemoryPage = (PMEM_HEADER)hcd->CommonBufferVA;
|
||||||
|
ULONG PageCount = 0;
|
||||||
|
ULONG NumberOfPages = hcd->CommonBufferSize / PAGE_SIZE;
|
||||||
|
ULONG BlocksNeeded;
|
||||||
|
ULONG i,j, freeCount;
|
||||||
|
ULONG RetAddr = 0;
|
||||||
|
|
||||||
|
Size = ((Size + SMALL_ALLOCATION_SIZE - 1) / SMALL_ALLOCATION_SIZE) * SMALL_ALLOCATION_SIZE;
|
||||||
|
BlocksNeeded = Size / SMALL_ALLOCATION_SIZE;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
if (MemoryPage->IsFull)
|
||||||
|
{
|
||||||
|
PageCount++;
|
||||||
|
MemoryPage = (PMEM_HEADER)((ULONG)MemoryPage + PAGE_SIZE);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
freeCount = 0;
|
||||||
|
for (i = 0; i < sizeof(MemoryPage->Entry); i++)
|
||||||
|
{
|
||||||
|
if (!MemoryPage->Entry[i].InUse)
|
||||||
|
{
|
||||||
|
freeCount++;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
freeCount = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (freeCount == BlocksNeeded)
|
||||||
|
{
|
||||||
|
for (j = 0; j < freeCount; j++)
|
||||||
|
{
|
||||||
|
MemoryPage->Entry[i-j].InUse = 1;
|
||||||
|
MemoryPage->Entry[i-j].Blocks = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
MemoryPage->Entry[i-freeCount + 1].Blocks = BlocksNeeded;
|
||||||
|
|
||||||
|
RetAddr = (ULONG)MemoryPage + (SMALL_ALLOCATION_SIZE * (i - freeCount + 1)) + sizeof(MEM_HEADER);
|
||||||
|
|
||||||
|
*PhysicalAddress = (ULONG)hcd->CommonBufferPA.LowPart + (RetAddr - (ULONG)hcd->CommonBufferVA);
|
||||||
|
return RetAddr;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
PageCount++;
|
||||||
|
MemoryPage = (PMEM_HEADER)((ULONG)MemoryPage + PAGE_SIZE);
|
||||||
|
} while (PageCount < NumberOfPages);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
VOID
|
||||||
|
ReleaseMemory(ULONG Address)
|
||||||
|
{
|
||||||
|
PMEM_HEADER MemoryPage;
|
||||||
|
ULONG Index, i;
|
||||||
|
|
||||||
|
MemoryPage = (PMEM_HEADER)(Address & ~(PAGE_SIZE - 1));
|
||||||
|
|
||||||
|
Index = (Address - ((ULONG)MemoryPage + sizeof(MEM_HEADER))) / SMALL_ALLOCATION_SIZE;
|
||||||
|
|
||||||
|
for (i = 0; i < MemoryPage->Entry[Index].Blocks; i++)
|
||||||
|
{
|
||||||
|
MemoryPage->Entry[Index + i].InUse = 0;
|
||||||
|
MemoryPage->Entry[Index + i].Blocks = 0;
|
||||||
|
}
|
||||||
|
}
|
25
reactos/drivers/usb/usbehci/physmem.h
Normal file
25
reactos/drivers/usb/usbehci/physmem.h
Normal file
|
@ -0,0 +1,25 @@
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#include "hardware.h"
|
||||||
|
|
||||||
|
typedef struct _MEM_ENTRY
|
||||||
|
{
|
||||||
|
UCHAR InUse:1;
|
||||||
|
UCHAR Blocks:7;
|
||||||
|
} MEM_ENTRY, *PMEM_ENTRY;
|
||||||
|
|
||||||
|
typedef struct _MEM_HEADER
|
||||||
|
{
|
||||||
|
UCHAR IsFull;
|
||||||
|
MEM_ENTRY Entry[127];
|
||||||
|
} MEM_HEADER, *PMEM_HEADER;
|
||||||
|
|
||||||
|
VOID
|
||||||
|
DumpPages();
|
||||||
|
|
||||||
|
ULONG
|
||||||
|
AllocateMemory(PEHCI_HOST_CONTROLLER hcd, ULONG Size, ULONG *PhysicalAddress);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
ReleaseMemory(ULONG Address);
|
||||||
|
|
Loading…
Reference in a new issue