mirror of
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- Commit current work on IRQ rewrite. Currently in a very ugly/dirty state of flux between the new ASM code (with tiny hacks) and the old C code (with giant hacks). I feel that this is a good/stable middle ground before continuing further with the changes.
svn path=/trunk/; revision=23649
This commit is contained in:
Alex Ionescu
parent
746195690d
commit
4e5173d7d0
7 changed files with 715 additions and 276 deletions
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@ -32,6 +32,7 @@
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<define name="__USE_W32API" />
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<file>ipi.c</file>
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<file>irql.c</file>
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<file>irq.S</file>
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<file>processor.c</file>
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<file>resource.c</file>
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<file>spinlock.c</file>
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649
reactos/hal/halx86/generic/irq.S
Normal file
649
reactos/hal/halx86/generic/irq.S
Normal file
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@ -0,0 +1,649 @@
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/*
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* FILE: hal/halx86/generic/irql.S
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* COPYRIGHT: See COPYING in the top level directory
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* PURPOSE: Software, System and Hardware IRQ Management
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* PROGRAMMER: Alex Ionescu (alex@relsoft.net)
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*/
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/* INCLUDES ******************************************************************/
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#include <asm.h>
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#include <internal/i386/asmmacro.S>
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.intel_syntax noprefix
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.extern _Kei386EoiHelper@0
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.extern _KiUnexpectedInterrupt
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/* GLOBALS *******************************************************************/
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PICInitTable:
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/* Master PIC */
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.short 0x20 /* Port */
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.byte 0x11 /* Edge,, cascade, CAI 8, ICW4 */
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.byte 0x40 /* Base */
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.byte 4 /* IRQ 4 connected to slave */
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.byte 1 /* Non buffered, not nested, 8086 */
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/* Slave PIC */
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.short 0xA0 /* Port */
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.byte 0x11 /* Edge, cascade, CAI 8, ICW4 */
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.byte 0x48 /* Base */
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.byte 2 /* Slave ID: Slave 2 */
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.byte 1 /* Non buffered, not nested, 8086 */
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/* End of initialization table */
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.short 0
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.globl _KiI8259MaskTable
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_KiI8259MaskTable:
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.long 0 /* IRQL 0 */
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.long 0 /* IRQL 1 */
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.long 0 /* IRQL 2 */
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.long 0 /* IRQL 3 */
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.long 0xFF800000 /* IRQL 4 */
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.long 0xFFC00000 /* IRQL 5 */
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.long 0xFFE00000 /* IRQL 6 */
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.long 0xFFF00000 /* IRQL 7 */
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.long 0xFFF80000 /* IRQL 8 */
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.long 0xFFFC0000 /* IRQL 9 */
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.long 0xFFFE0000 /* IRQL 10 */
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.long 0xFFFF0000 /* IRQL 11 */
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.long 0xFFFF8000 /* IRQL 12 */
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.long 0xFFFFC000 /* IRQL 13 */
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.long 0xFFFFE000 /* IRQL 14 */
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.long 0xFFFFF000 /* IRQL 15 */
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.long 0xFFFFF800 /* IRQL 16 */
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.long 0xFFFFFC00 /* IRQL 17 */
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.long 0xFFFFFE00 /* IRQL 18 */
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.long 0xFFFFFE00 /* IRQL 19 */
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.long 0xFFFFFE80 /* IRQL 20 */
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.long 0xFFFFFEC0 /* IRQL 21 */
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.long 0xFFFFFEE0 /* IRQL 22 */
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.long 0xFFFFFEF0 /* IRQL 23 */
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.long 0xFFFFFEF8 /* IRQL 24 */
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.long 0xFFFFFEF8 /* IRQL 25 */
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.long 0xFFFFFEFA /* IRQL 26 */
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.long 0xFFFFFFFA /* IRQL 27 */
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.long 0xFFFFFFFB /* IRQL 28 */
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.long 0xFFFFFFFB /* IRQL 29 */
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.long 0xFFFFFFFB /* IRQL 30 */
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.long 0xFFFFFFFB /* IRQL 31 */
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#if 0
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HalpSysIntHandler:
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.rept 8
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.long GenericIRQ /* IRQ 0-7 */
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.endr
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.long IRQ7 /* IRQ 7 */
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.rept 8
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.long GenericIRQ /* IRQ 8-15 */
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.endr
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.long IRQ15 /* IRQ 15 */
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.rept 20
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.long GenericIRQ /* IRQ 16-35 */
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.endr
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#endif
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SoftIntByteTable:
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.byte PASSIVE_LEVEL /* IRR 0 */
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.byte PASSIVE_LEVEL /* IRR 1 */
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.byte APC_LEVEL /* IRR 2 */
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.byte APC_LEVEL /* IRR 3 */
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.byte DISPATCH_LEVEL /* IRR 4 */
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.byte DISPATCH_LEVEL /* IRR 5 */
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.byte DISPATCH_LEVEL /* IRR 6 */
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.byte DISPATCH_LEVEL /* IRR 7 */
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SoftIntHandlerTable:
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.long _KiUnexpectedInterrupt /* PASSIVE_LEVEL */
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.long _HalpApcInterrupt /* APC_LEVEL */
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.long _HalpDispatchInterrupt /* DISPATCH_LEVEL */
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SoftIntHandlerTable2:
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.long _KiUnexpectedInterrupt /* PASSIVE_LEVEL */
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.long _HalpApcInterrupt2ndEntry /* APC_LEVEL */
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.long _HalpDispatchInterrupt2ndEntry /* DISPATCH_LEVEL */
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/* FUNCTIONS *****************************************************************/
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.globl _HalpInitPICs@0
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.func HalpInitPICs@0
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_HalpInitPICs@0:
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/* Save ESI and disable interrupts */
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push esi
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pushf
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cli
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/* Read the init table */
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lea esi, PICInitTable
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lodsw
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InitLoop:
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/* Put the port in EDX */
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movzx edx, ax
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/* Initialize the PIC, using a delay for each command */
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outsb
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jmp $+2
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inc edx
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outsb
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jmp $+2
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outsb
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jmp $+2
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outsb
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jmp $+2
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/* Mask all interrupts */
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mov al, 0xFA // FIXME: Should be 0xFF
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out dx, al
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/* Check if we're done, otherwise initialize next PIC */
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lodsw
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cmp ax, 0
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jnz InitLoop
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/* Restore interrupts and return */
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or dword ptr [esp], EFLAGS_INTERRUPT_MASK
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popf
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pop esi
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ret
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.endfunc
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.globl @HalRequestSoftwareInterrupt@4
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.func @HalRequestSoftwareInterrupt@4
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_@HalRequestSoftwareInterrupt@4:
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@HalRequestSoftwareInterrupt@4:
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/* Get IRR mask */
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mov eax, 1
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shl eax, cl
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/* Disable interrupts */
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pushf
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cli
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/* Set IRR and get IRQL */
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or [fs:KPCR_IRR], eax
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mov cl, [fs:KPCR_IRQL]
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/* Get software IRR mask */
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mov eax, [fs:KPCR_IRR]
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and eax, 3
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/* Get highest pending software interrupt and check if it's higher */
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xor edx, edx
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mov dl, SoftIntByteTable[eax]
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cmp dl, cl
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jbe AfterCall
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/* Call the pending interrupt */
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jmp $
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call SoftIntHandlerTable[edx*4]
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AfterCall:
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/* Retore interrupts and return */
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popf
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ret
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.endfunc
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.globl _HalDisableSystemInterrupt@8
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.func HalDisableSystemInterrupt@8
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_HalDisableSystemInterrupt@8:
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/* Convert to vector */
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movzx ecx, byte ptr [esp+4]
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sub ecx, PRIMARY_VECTOR_BASE
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/* Disable interrupts and set the new IDR */
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mov edx, 1
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shl edx, cl
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cli
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or [fs+KPCR_IDR], edx
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/* Get the current mask */
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xor eax, eax
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in al, 0xA1
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shl eax, 8
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in al, 0x21
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/* Mask off the interrupt and write the new mask */
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or eax, edx
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Return with interrupts enabled */
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in al, 0xA1
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sti
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ret 8
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.endfunc
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#if 0
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.globl _HalEnableSystemInterrupt@12
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.func HalEnableSystemInterrupt@12
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_HalEnableSystemInterrupt@12:
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/* Get the vector and validate it */
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jmp $
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movzx ecx, byte ptr [esp+4]
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sub ecx, PRIMARY_VECTOR_BASE
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jb Invalid
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cmp ecx, CLOCK2_LEVEL
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jnb Invalid
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/* Get the current PCI Edge/Level control registers */
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mov edx, 0x4D1
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in al, dx
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shl ax, 8
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mov eax, 0x4D0
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in al, dx
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mov dx, 1
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shl dx, cl
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/* Check if this is a latched interrupt */
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cmp dword ptr [esp+12], 0
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jnz Latched
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/* Use OR for edge interrupt */
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or ax, dx
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jmp AfterMask
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Latched:
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/* Mask it out for level interrupt */
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not dx
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and ax, dx
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AfterMask:
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/* Set the PCI Edge/Level control registers */
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mov edx, 0x4D0
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out dx, al
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shr ax, 8
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mov edx, 0x4D1
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out dx, al
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/* Calculate the new IDR */
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mov eax, 1
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shl eax, cl
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not eax
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cli
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and [fs:KPCR_IDR], eax
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/* Get the current IRQL and mask the IRQs in the PIC */
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movzx eax, byte ptr [fs:KPCR_IRQL]
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mov eax, _KiI8259MaskTable[eax*4]
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or eax, [fs:KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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Invalid:
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/* Fail, invalid IRQ */
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xor eax, eax
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ret 12
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.endfunc
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.globl _HalBeginSystemInterrupt@12
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.func HalBeginSystemInterrupt@12
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_HalBeginSystemInterrupt@12:
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/* Convert to vector and call the handler */
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movzx ebx, byte ptr [esp+8]
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sub ebx, PRIMARY_VECTOR_BASE
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jmp HalpSysIntHandler[ebx*4]
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IRQ15:
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/* This is IRQ 15, check if it's spurious */
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mov al, 0xB
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out 0xA0, al
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in al, 0xA0
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test al, 0x80
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jnz GenericIRQ
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/* Cascaded interrupt... dismiss it and return FALSE */
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mov al, 0x62
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out 0x20, al
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mov eax, 0
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ret 12
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IRQ7:
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/* This is IRQ 7, check if it's spurious */
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mov al, 0xB
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out 0x20, al
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in al, 0x20
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test al, 0x80
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jnz GenericIRQ
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/* It is, return FALSE */
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mov eax, 0
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ret 12
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GenericIRQ:
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/* Return the current IRQL */
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mov eax, [esp+12]
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movzx ecx, word ptr [fs:KPCR_IRQL]
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mov [eax], cl
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/* Set the new IRQL */
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movzx eax, byte ptr [esp+4]
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mov [fs:KPCR_IRQL], al
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/* Set IRQ mask in the PIC */
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mov eax, _KiI8259MaskTable[eax*4]
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or eax, [fs:KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Check to which PIC the EOI was sent */
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mov eax, ebx
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cmp eax, 8
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jnb Pic1
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/* Write mask to master PIC */
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or al, 0x60
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out 0x20, al
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jmp DoneBegin
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Pic1:
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/* Write mask to slave PIC */
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mov al, 0x20
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out 0xA0, al
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mov al, 0x62
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out 0x20, al
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DoneBegin:
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/* Enable interrupts and return TRUE */
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in al, 0x21
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sti
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mov eax, 1
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ret 12
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.endfunc
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.globl _HalEndSystemInterrupt@8
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.func HalEndSystemInterrupt@8
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_HalEndSystemInterrupt@8:
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/* Get the IRQL and check if it's a software interrupt */
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movzx ecx, byte ptr [esp+4]
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cmp byte ptr [fs:KPCR_IRQL], DISPATCH_LEVEL
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jbe SkipMask2
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/* Hardware interrupt, mask the appropriate IRQs in the PIC */
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mov eax, _KiI8259MaskTable[ecx*4]
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or eax, [fs:KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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SkipMask2:
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/* Set IRQL and check if there are pending software interrupts */
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mov [fs:KPCR_IRQL], cl
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mov eax, [fs:KPCR_IDR]
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mov al, SoftIntByteTable[eax]
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cmp al, cl
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ja DoCall
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ret 8
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DoCall:
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/* There are pending softwate interrupts, call their handlers */
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add esp, 8
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jmp SoftIntHandlerTable2[eax*4]
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.endfunc
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.globl @KfLowerIrql@4
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.func @KfLowerIrql@4
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_@KfLowerIrql@4:
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@KfLowerIrql@4:
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/* Save flags since we'll disable interrupts */
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pushf
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/* Disable interrupts and check if IRQL is below DISPATCH_LEVEL */
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movzx ecx, cl
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cmp byte ptr [fs:KPCR_IRQL], DISPATCH_LEVEL
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cli
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jbe SkipMask
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/* Clear interrupt masks since there's a pending hardware interrupt */
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mov eax, _KiI8259MaskTable[ecx*4]
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or eax, [fs:KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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SkipMask:
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/* Set the new IRQL and check if there's a pending software interrupt */
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mov [fs:KPCR_IRQL], cl
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mov eax, [fs:KPCR_IDR]
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mov al, SoftIntByteTable[eax]
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cmp al, cl
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jbe AfterCall2
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/* There is, call it */
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call SoftIntHandlerTable[eax*4]
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AfterCall2:
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/* Restore interrupts and return */
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popf
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ret
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.endfunc
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#endif
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.globl @KfRaiseIrql@4
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.func @KfRaiseIrql@4
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_@KfRaiseIrql@4:
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@KfRaiseIrql@4:
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/* Get the IRQL and check if it's Software level only */
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xor eax, eax
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mov al, [fs:KPCR_IRQL]
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movzx ecx, cl
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cmp cl, DISPATCH_LEVEL
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jbe SetIrql
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/* Save the current IRQL */
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mov edx, eax
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/* It's a hardware IRQL, so disable interrupts */
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pushf
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cli
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/* Set the new IRQL */
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mov [fs:KPCR_IRQL], cl
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#if 0
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/* Mask the interrupts in the PIC */
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mov eax, _KiI8259MaskTable[ecx*4]
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or eax, [fs:KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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#endif
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/* Restore interrupts and return old IRQL */
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popf
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mov eax, edx
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ret
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SetIrql:
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/* Set the IRQL and return */
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mov [fs:KPCR_IRQL], cl
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ret
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.endfunc
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.globl _KeGetCurrentIrql@0
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.func KeGetCurrentIrql@0
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_KeGetCurrentIrql@0:
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/* Return the IRQL */
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movzx eax, word ptr [fs:KPCR_IRQL]
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ret
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.endfunc
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.globl _KeRaiseIrqlToDpcLevel@0
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.func KeRaiseIrqlToDpcLevel@0
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_KeRaiseIrqlToDpcLevel@0:
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/* Get the current IRQL */
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xor eax, eax
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mov al, [fs:KPCR_IRQL]
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/* Set DISPATCH_LEVEL */
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mov byte ptr [fs:KPCR_IRQL], DISPATCH_LEVEL
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ret
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.endfunc
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.globl _KeRaiseIrqlToSynchLevel@0
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.func KeRaiseIrqlToSynchLevel@0
|
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_KeRaiseIrqlToSynchLevel@0:
|
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|
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/* Disable interrupts */
|
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pushf
|
||||
cli
|
||||
|
||||
/* Mask out interrupts */
|
||||
mov eax, _KiI8259MaskTable + DISPATCH_LEVEL * 2
|
||||
or eax, [fs:KPCR_IDR]
|
||||
out 0x21, al
|
||||
shr eax, 8
|
||||
out 0xA1, al
|
||||
|
||||
/* Return the old IRQL, enable interrupts and set to DISPATCH */
|
||||
mov al, [fs:KPCR_IRQL]
|
||||
mov byte ptr [fs:KPCR_IRQL], DISPATCH_LEVEL
|
||||
popf
|
||||
ret
|
||||
.endfunc
|
||||
|
||||
.globl _HalpApcInterrupt
|
||||
.func HalpApcInterrupt
|
||||
_HalpApcInterrupt:
|
||||
|
||||
/* Create fake interrupt stack */
|
||||
pop eax
|
||||
pushf
|
||||
push cs
|
||||
push eax
|
||||
|
||||
/* Enter interrupt */
|
||||
INT_PROLOG(hapc)
|
||||
.endfunc
|
||||
|
||||
.globl _HalpApcInterrupt2ndEntry
|
||||
.func HalpApcInterrupt2ndEntry
|
||||
_HalpApcInterrupt2ndEntry:
|
||||
|
||||
/* Save current IRQL and set to APC level */
|
||||
push [fs:KPCR_IRQL]
|
||||
mov byte ptr [fs:KPCR_IRQL], APC_LEVEL
|
||||
and dword ptr [fs:KPCR_IRR], ~(1 << APC_LEVEL)
|
||||
|
||||
/* Enable interrupts and check if we came from User/V86 mode */
|
||||
sti
|
||||
mov eax, [ebp+KTRAP_FRAME_CS]
|
||||
and eax, MODE_MASK
|
||||
test dword ptr [ebp+KTRAP_FRAME_EFLAGS], EFLAGS_V86_MASK
|
||||
jz DeliverApc
|
||||
|
||||
/* Set user mode delivery */
|
||||
or eax, UserMode
|
||||
|
||||
DeliverApc:
|
||||
|
||||
/* Deliver the APCs */
|
||||
push ebp
|
||||
push 0
|
||||
push eax
|
||||
call _KiDeliverApc@12
|
||||
|
||||
/* Disable interrupts and end it */
|
||||
cli
|
||||
call _HalpEndSoftwareInterrupt@4
|
||||
jmp _Kei386EoiHelper@0
|
||||
.endfunc
|
||||
|
||||
.globl _HalpDispatchInterrupt
|
||||
.func HalpDispatchInterrupt
|
||||
_HalpDispatchInterrupt:
|
||||
|
||||
/* Create fake interrupt stack */
|
||||
pop eax
|
||||
pushf
|
||||
push cs
|
||||
push eax
|
||||
|
||||
/* Enter interrupt */
|
||||
INT_PROLOG(hapc)
|
||||
.endfunc
|
||||
|
||||
.globl _HalpDispatchInterrupt2ndEntry
|
||||
.func HalpDispatchInterrupt2ndEntry
|
||||
_HalpDispatchInterrupt2ndEntry:
|
||||
|
||||
/* Save current IRQL and set to DPC level */
|
||||
push [fs:KPCR_IRQL]
|
||||
mov byte ptr [fs:KPCR_IRQL], DISPATCH_LEVEL
|
||||
and dword ptr [fs:KPCR_IRR], ~(1 << DISPATCH_LEVEL)
|
||||
|
||||
/* Enable interrupts and let the kernel handle this */
|
||||
sti
|
||||
call _KiDispatchInterrupt@0
|
||||
|
||||
/* Disable interrupts and end it */
|
||||
cli
|
||||
call _HalpEndSoftwareInterrupt@4
|
||||
jmp _Kei386EoiHelper@0
|
||||
.endfunc
|
||||
|
||||
.globl _HalpEndSoftwareInterrupt@4
|
||||
.func HalpEndSoftwareInterrupt@4
|
||||
_HalpEndSoftwareInterrupt@4:
|
||||
|
||||
/* Get the IRQL and check if we're in the software region */
|
||||
movzx ecx, byte ptr [esp+4]
|
||||
cmp byte ptr [fs:KPCR_IRQL], DISPATCH_LEVEL
|
||||
jbe SoftwareInt
|
||||
|
||||
/* Set the right mask in the PIC for the hardware IRQ */
|
||||
mov eax, _KiI8259MaskTable[ecx*4]
|
||||
or eax, [fs:KPCR_IDR]
|
||||
out 0x21, al
|
||||
shr eax, 8
|
||||
out 0xA1, al
|
||||
|
||||
SoftwareInt:
|
||||
/* Check if there are pending software interrupts */
|
||||
mov [fs:KPCR_IRQL], cl
|
||||
mov eax, [fs:KPCR_IDR]
|
||||
mov al, SoftIntByteTable[eax]
|
||||
cmp al, cl
|
||||
ja DoCall2
|
||||
ret 4
|
||||
|
||||
DoCall2:
|
||||
|
||||
/* There are pending softwate interrupts, call their handlers */
|
||||
add esp, 8
|
||||
jmp SoftIntHandlerTable2[eax*4]
|
||||
.endfunc
|
||||
|
|
@ -19,38 +19,16 @@
|
|||
* FIXME: Use EISA_CONTROL STRUCTURE INSTEAD OF HARD-CODED OFFSETS
|
||||
*/
|
||||
|
||||
typedef union
|
||||
UCHAR Table[8] =
|
||||
{
|
||||
USHORT both;
|
||||
struct
|
||||
{
|
||||
BYTE master;
|
||||
BYTE slave;
|
||||
};
|
||||
}
|
||||
PIC_MASK;
|
||||
0, 0,
|
||||
1, 1,
|
||||
2, 2, 2, 2
|
||||
};
|
||||
|
||||
/*
|
||||
* PURPOSE: - Mask for HalEnableSystemInterrupt and HalDisableSystemInterrupt
|
||||
* - At startup enable timer and cascade
|
||||
*/
|
||||
#if defined(__GNUC__)
|
||||
static PIC_MASK pic_mask = {.both = 0xFFFA};
|
||||
#else
|
||||
static PIC_MASK pic_mask = { 0xFFFA };
|
||||
#endif
|
||||
ULONG pic_mask = {0xFFFFFFFA};
|
||||
|
||||
|
||||
/*
|
||||
* PURPOSE: Mask for disabling of acknowledged interrupts
|
||||
*/
|
||||
#if defined(__GNUC__)
|
||||
static PIC_MASK pic_mask_intr = {.both = 0x0000};
|
||||
#else
|
||||
static PIC_MASK pic_mask_intr = { 0 };
|
||||
#endif
|
||||
|
||||
static ULONG HalpPendingInterruptCount[NR_IRQS];
|
||||
static ULONG HalpPendingInterruptCount[NR_IRQS] = {0};
|
||||
|
||||
#define DIRQL_TO_IRQ(x) (PROFILE_LEVEL - x)
|
||||
#define IRQ_TO_DIRQL(x) (PROFILE_LEVEL - x)
|
||||
|
|
@ -60,40 +38,7 @@ KiInterruptDispatch2 (ULONG Irq, KIRQL old_level);
|
|||
|
||||
/* FUNCTIONS ****************************************************************/
|
||||
|
||||
#undef KeGetCurrentIrql
|
||||
KIRQL STDCALL KeGetCurrentIrql (VOID)
|
||||
/*
|
||||
* PURPOSE: Returns the current irq level
|
||||
* RETURNS: The current irq level
|
||||
*/
|
||||
{
|
||||
return(KeGetPcr()->Irql);
|
||||
}
|
||||
|
||||
VOID HalpInitPICs(VOID)
|
||||
{
|
||||
memset(HalpPendingInterruptCount, 0, sizeof(HalpPendingInterruptCount));
|
||||
|
||||
/* Initialization sequence */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20, 0x11);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa0, 0x11);
|
||||
/* Start of hardware irqs (0x24) */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, IRQ_BASE);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, IRQ_BASE + 8);
|
||||
/* 8259-1 is master */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x4);
|
||||
/* 8259-2 is slave */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x2);
|
||||
/* 8086 mode */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x1);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x1);
|
||||
/* Enable interrupts */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, pic_mask.master);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave);
|
||||
|
||||
/* We can now enable interrupts */
|
||||
Ki386EnableInterrupts();
|
||||
}
|
||||
extern ULONG KiI8259MaskTable[];
|
||||
|
||||
VOID HalpEndSystemInterrupt(KIRQL Irql)
|
||||
/*
|
||||
|
|
@ -101,21 +46,16 @@ VOID HalpEndSystemInterrupt(KIRQL Irql)
|
|||
*/
|
||||
{
|
||||
ULONG flags;
|
||||
const USHORT mask[] =
|
||||
{
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0xc000, 0xe000, 0xf000,
|
||||
0xf800, 0xfc00, 0xfe00, 0xff00, 0xff80, 0xffc0, 0xffe0, 0xfff0,
|
||||
0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
|
||||
};
|
||||
ULONG Mask;
|
||||
|
||||
/* Interrupts should be disable while enabling irqs of both pics */
|
||||
Ki386SaveFlags(flags);
|
||||
Ki386DisableInterrupts();
|
||||
|
||||
pic_mask_intr.both &= mask[Irql];
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
Mask = pic_mask | KiI8259MaskTable[Irql];
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)Mask);
|
||||
Mask >>= 8;
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)Mask);
|
||||
|
||||
/* restore flags */
|
||||
Ki386RestoreFlags(flags);
|
||||
|
|
@ -168,9 +108,9 @@ HalpLowerIrql(KIRQL NewIrql)
|
|||
return;
|
||||
}
|
||||
KeGetPcr()->Irql = DISPATCH_LEVEL;
|
||||
if (((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST])
|
||||
if (Table[KeGetPcr()->IRR] >= NewIrql)
|
||||
{
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = FALSE;
|
||||
KeGetPcr()->IRR &= ~4;
|
||||
KiDispatchInterrupt();
|
||||
}
|
||||
KeGetPcr()->Irql = APC_LEVEL;
|
||||
|
|
@ -219,172 +159,36 @@ KfLowerIrql (KIRQL NewIrql)
|
|||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KeLowerIrql
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Restores the irq level on the current processor
|
||||
*
|
||||
* ARGUMENTS
|
||||
* NewIrql = Irql to lower to
|
||||
*
|
||||
* RETURN VALUE
|
||||
* None
|
||||
*
|
||||
* NOTES
|
||||
*/
|
||||
#undef KeLowerIrql
|
||||
VOID STDCALL
|
||||
KeLowerIrql (KIRQL NewIrql)
|
||||
{
|
||||
KfLowerIrql (NewIrql);
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KfRaiseIrql
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Raises the hardware priority (irql)
|
||||
*
|
||||
* ARGUMENTS
|
||||
* NewIrql = Irql to raise to
|
||||
*
|
||||
* RETURN VALUE
|
||||
* previous irq level
|
||||
*
|
||||
* NOTES
|
||||
* Uses fastcall convention
|
||||
*/
|
||||
|
||||
KIRQL FASTCALL
|
||||
KfRaiseIrql (KIRQL NewIrql)
|
||||
{
|
||||
KIRQL OldIrql;
|
||||
|
||||
DPRINT("KfRaiseIrql(NewIrql %d)\n", NewIrql);
|
||||
|
||||
if (NewIrql < KeGetPcr()->Irql)
|
||||
{
|
||||
DbgPrint ("%s:%d CurrentIrql %x NewIrql %x\n",
|
||||
__FILE__,__LINE__,KeGetPcr()->Irql,NewIrql);
|
||||
KEBUGCHECK (0);
|
||||
for(;;);
|
||||
}
|
||||
|
||||
OldIrql = KeGetPcr()->Irql;
|
||||
KeGetPcr()->Irql = NewIrql;
|
||||
return OldIrql;
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KeRaiseIrql
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Raises the hardware priority (irql)
|
||||
*
|
||||
* ARGUMENTS
|
||||
* NewIrql = Irql to raise to
|
||||
* OldIrql (OUT) = Caller supplied storage for the previous irql
|
||||
*
|
||||
* RETURN VALUE
|
||||
* None
|
||||
*
|
||||
* NOTES
|
||||
* Calls KfRaiseIrql
|
||||
*/
|
||||
#undef KeRaiseIrql
|
||||
VOID STDCALL
|
||||
KeRaiseIrql (KIRQL NewIrql,
|
||||
PKIRQL OldIrql)
|
||||
{
|
||||
*OldIrql = KfRaiseIrql (NewIrql);
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KeRaiseIrqlToDpcLevel
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Raises the hardware priority (irql) to DISPATCH level
|
||||
*
|
||||
* ARGUMENTS
|
||||
* None
|
||||
*
|
||||
* RETURN VALUE
|
||||
* Previous irq level
|
||||
*
|
||||
* NOTES
|
||||
* Calls KfRaiseIrql
|
||||
*/
|
||||
|
||||
KIRQL STDCALL
|
||||
KeRaiseIrqlToDpcLevel (VOID)
|
||||
{
|
||||
return KfRaiseIrql (DISPATCH_LEVEL);
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KeRaiseIrqlToSynchLevel
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Raises the hardware priority (irql) to CLOCK2 level
|
||||
*
|
||||
* ARGUMENTS
|
||||
* None
|
||||
*
|
||||
* RETURN VALUE
|
||||
* Previous irq level
|
||||
*
|
||||
* NOTES
|
||||
* Calls KfRaiseIrql
|
||||
*/
|
||||
|
||||
KIRQL STDCALL
|
||||
KeRaiseIrqlToSynchLevel (VOID)
|
||||
{
|
||||
return KfRaiseIrql (CLOCK2_LEVEL);
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalBeginSystemInterrupt (KIRQL Irql,
|
||||
ULONG Vector,
|
||||
PKIRQL OldIrql)
|
||||
{
|
||||
ULONG irq;
|
||||
ULONG Mask;
|
||||
|
||||
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
|
||||
{
|
||||
return(FALSE);
|
||||
}
|
||||
irq = Vector - IRQ_BASE;
|
||||
pic_mask_intr.both |= ((1 << irq) & 0xfffe); // do not disable the timer interrupt
|
||||
|
||||
Mask = pic_mask | KiI8259MaskTable[Irql];
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)Mask);
|
||||
Mask >>= 8;
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)Mask);
|
||||
|
||||
if (irq < 8)
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20, 0x20);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20, 0x60 | irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
/* Send EOI to the PICs */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20,0x20);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20,0x62);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa0,0x20);
|
||||
}
|
||||
|
||||
if (KeGetPcr()->Irql >= Irql)
|
||||
{
|
||||
HalpPendingInterruptCount[irq]++;
|
||||
return(FALSE);
|
||||
}
|
||||
*OldIrql = KeGetPcr()->Irql;
|
||||
KeGetPcr()->Irql = Irql;
|
||||
|
||||
|
|
@ -397,36 +201,11 @@ VOID STDCALL HalEndSystemInterrupt (KIRQL Irql, ULONG Unknown2)
|
|||
* FUNCTION: Finish a system interrupt and restore the specified irq level.
|
||||
*/
|
||||
{
|
||||
//DPRINT1("ENDING: %lx %lx\n", Irql, Unknown2);
|
||||
HalpLowerIrql(Irql);
|
||||
HalpEndSystemInterrupt(Irql);
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
HalDisableSystemInterrupt(
|
||||
ULONG Vector,
|
||||
KIRQL Irql)
|
||||
{
|
||||
ULONG irq;
|
||||
|
||||
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
|
||||
return FALSE;
|
||||
|
||||
irq = Vector - IRQ_BASE;
|
||||
pic_mask.both |= (1 << irq);
|
||||
if (irq < 8)
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.slave));
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
HalEnableSystemInterrupt(
|
||||
|
|
@ -435,42 +214,22 @@ HalEnableSystemInterrupt(
|
|||
KINTERRUPT_MODE InterruptMode)
|
||||
{
|
||||
ULONG irq;
|
||||
ULONG Mask;
|
||||
|
||||
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
|
||||
return FALSE;
|
||||
|
||||
irq = Vector - IRQ_BASE;
|
||||
pic_mask.both &= ~(1 << irq);
|
||||
if (irq < 8)
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
}
|
||||
pic_mask &= ~(1 << irq);
|
||||
|
||||
Mask = pic_mask | KiI8259MaskTable[KeGetPcr()->Irql];
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)Mask);
|
||||
Mask >>= 8;
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)Mask);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
VOID FASTCALL
|
||||
HalRequestSoftwareInterrupt(
|
||||
IN KIRQL Request)
|
||||
{
|
||||
switch (Request)
|
||||
{
|
||||
case APC_LEVEL:
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_APC_REQUEST] = TRUE;
|
||||
break;
|
||||
|
||||
case DISPATCH_LEVEL:
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = TRUE;
|
||||
break;
|
||||
|
||||
default:
|
||||
KEBUGCHECK(0);
|
||||
}
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
|
|
|
|||
|
|
@ -14,9 +14,34 @@
|
|||
|
||||
#undef KeAcquireSpinLock
|
||||
#undef KeReleaseSpinLock
|
||||
#undef KeLowerIrql
|
||||
#undef KeRaiseIrql
|
||||
|
||||
/* FUNCTIONS ***************************************************************/
|
||||
|
||||
/*
|
||||
* @implemented
|
||||
*/
|
||||
VOID
|
||||
NTAPI
|
||||
KeLowerIrql(KIRQL NewIrql)
|
||||
{
|
||||
/* Call the fastcall function */
|
||||
KfLowerIrql(NewIrql);
|
||||
}
|
||||
|
||||
/*
|
||||
* @implemented
|
||||
*/
|
||||
VOID
|
||||
NTAPI
|
||||
KeRaiseIrql(KIRQL NewIrql,
|
||||
PKIRQL OldIrql)
|
||||
{
|
||||
/* Call the fastcall function */
|
||||
*OldIrql = KfRaiseIrql(NewIrql);
|
||||
}
|
||||
|
||||
/*
|
||||
* @implemented
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN
|
|||
VOID HalpInitBusHandlers (VOID);
|
||||
|
||||
/* irql.c */
|
||||
VOID HalpInitPICs(VOID);
|
||||
VOID NTAPI HalpInitPICs(VOID);
|
||||
|
||||
/* udelay.c */
|
||||
VOID HalpCalibrateStallExecution(VOID);
|
||||
|
|
|
|||
|
|
@ -433,8 +433,9 @@ Author:
|
|||
|
||||
//
|
||||
// Vector base
|
||||
// ROS HACK HACK HACK
|
||||
//
|
||||
#define PRIMARY_VECTOR_BASE 0x30
|
||||
#define PRIMARY_VECTOR_BASE 0x40
|
||||
|
||||
//
|
||||
// Kernel Feature Bits
|
||||
|
|
|
|||
|
|
@ -260,6 +260,10 @@ ExecuteRuntimeAsserts(VOID)
|
|||
ASSERT(FIELD_OFFSET(KV86M_TRAP_FRAME, orig_ebp) == TF_ORIG_EBP);
|
||||
ASSERT(FIELD_OFFSET(KPCR, Tib.ExceptionList) == KPCR_EXCEPTION_LIST);
|
||||
ASSERT(FIELD_OFFSET(KPCR, Self) == KPCR_SELF);
|
||||
ASSERT(FIELD_OFFSET(KPCR, IRR) == KPCR_IRR);
|
||||
ASSERT(KeGetPcr()->IRR == 0);
|
||||
ASSERT(FIELD_OFFSET(KPCR, IDR) == KPCR_IDR);
|
||||
ASSERT(FIELD_OFFSET(KPCR, Irql) == KPCR_IRQL);
|
||||
ASSERT(FIELD_OFFSET(KIPCR, PrcbData) + FIELD_OFFSET(KPRCB, CurrentThread) == KPCR_CURRENT_THREAD);
|
||||
ASSERT(FIELD_OFFSET(KIPCR, PrcbData) + FIELD_OFFSET(KPRCB, NpxThread) == KPCR_NPX_THREAD);
|
||||
ASSERT(FIELD_OFFSET(KTSS, Esp0) == KTSS_ESP0);
|
||||
|
|
|
|||
Loading…
Reference in a new issue