diff --git a/reactos/hal/hal.rbuild b/reactos/hal/hal.rbuild index 568dcbdf9d4..588040a58a0 100644 --- a/reactos/hal/hal.rbuild +++ b/reactos/hal/hal.rbuild @@ -25,6 +25,10 @@ + + + + diff --git a/reactos/hal/halamd64/generic/generic.rbuild b/reactos/hal/halamd64/generic/generic.rbuild index 4c14a41f768..2b69e20d3b6 100644 --- a/reactos/hal/halamd64/generic/generic.rbuild +++ b/reactos/hal/halamd64/generic/generic.rbuild @@ -1,10 +1,15 @@ - - ../include - include - - - hal.c - ../include/hal.h - + + + ../include + include + + + halinit.c + irq.S + misc.c + systimer.S + ../include/hal.h + + diff --git a/reactos/hal/halamd64/generic/halinit.c b/reactos/hal/halamd64/generic/halinit.c new file mode 100644 index 00000000000..d3d834bf19a --- /dev/null +++ b/reactos/hal/halamd64/generic/halinit.c @@ -0,0 +1,170 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: GPL - See COPYING in the top level directory + * FILE: hal/halx86/generic/halinit.c + * PURPOSE: HAL Entrypoint and Initialization + * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org) + */ + +/* INCLUDES ******************************************************************/ + +#include +#define NDEBUG +#include + +/* GLOBALS *******************************************************************/ + +BOOLEAN HalpPciLockSettings; + +/* PRIVATE FUNCTIONS *********************************************************/ + +VOID +NTAPI +HalpGetParameters(IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + PCHAR CommandLine; + + /* Make sure we have a loader block and command line */ + if ((LoaderBlock) && (LoaderBlock->LoadOptions)) + { + /* Read the command line */ + CommandLine = LoaderBlock->LoadOptions; + + /* Check if PCI is locked */ + if (strstr(CommandLine, "PCILOCK")) HalpPciLockSettings = TRUE; + + /* Check for initial breakpoint */ + if (strstr(CommandLine, "BREAK")) DbgBreakPoint(); + } +} + +/* FUNCTIONS *****************************************************************/ + +NTSTATUS +NTAPI +DriverEntry( + PDRIVER_OBJECT DriverObject, + PUNICODE_STRING RegistryPath) +{ + UNIMPLEMENTED; + + return STATUS_SUCCESS; +} + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalInitSystem(IN ULONG BootPhase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + PKPRCB Prcb = KeGetCurrentPrcb(); + + /* Check the boot phase */ + if (!BootPhase) + { + /* Phase 0... save bus type */ + HalpBusType = LoaderBlock->u.I386.MachineType & 0xFF; + + /* Get command-line parameters */ + HalpGetParameters(LoaderBlock); + + /* Checked HAL requires checked kernel */ +#if DBG + if (!(Prcb->BuildType & PRCB_BUILD_DEBUG)) + { + /* No match, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 1, 0); + } +#else + /* Release build requires release HAL */ + if (Prcb->BuildType & PRCB_BUILD_DEBUG) + { + /* No match, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0); + } +#endif + +#ifdef CONFIG_SMP + /* SMP HAL requires SMP kernel */ + if (Prcb->BuildType & PRCB_BUILD_UNIPROCESSOR) + { + /* No match, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0); + } +#endif + + /* Validate the PRCB */ + if (Prcb->MajorVersion != PRCB_MAJOR_VERSION) + { + /* Validation failed, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 1, Prcb->MajorVersion, 1, 0); + } +DPRINT1("HalInitSystem 2\n"); + /* Initialize the PICs */ + HalpInitPICs(); +DPRINT1("HalInitSystem 3\n"); + /* Force initial PIC state */ + KfRaiseIrql(KeGetCurrentIrql()); +DPRINT1("HalInitSystem 4\n"); + /* Initialize the clock */ + HalpInitializeClock(); +DPRINT1("HalInitSystem 5\n"); + /* Setup busy waiting */ + //HalpCalibrateStallExecution(); + + /* Fill out the dispatch tables */ + HalQuerySystemInformation = HaliQuerySystemInformation; + HalSetSystemInformation = HaliSetSystemInformation; + HalInitPnpDriver = NULL; // FIXME: TODO +// HalGetDmaAdapter = HalpGetDmaAdapter; + HalGetInterruptTranslator = NULL; // FIXME: TODO +// HalResetDisplay = HalpBiosDisplayReset; +DPRINT1("HalInitSystem 6\n"); + /* Initialize the hardware lock (CMOS) */ + KeInitializeSpinLock(&HalpSystemHardwareLock); + + /* Do some HAL-specific initialization */ + HalpInitPhase0(LoaderBlock); + } + else if (BootPhase == 1) + { + /* Initialize the default HAL stubs for bus handling functions */ + HalpInitNonBusHandler(); + + /* Enable the clock interrupt */ + PKIDTENTRY64 IdtEntry = &((PKIPCR)KeGetPcr())->IdtBase[0x30]; + IdtEntry->OffsetLow = (((ULONG_PTR)HalpClockInterrupt) & 0xFFFF); + IdtEntry->OffsetMiddle = (((ULONG_PTR)HalpClockInterrupt >> 16) & 0xFFFF); + IdtEntry->OffsetHigh = ((ULONG_PTR)HalpClockInterrupt >> 32); +// HalEnableSystemInterrupt(0x30, CLOCK_LEVEL, Latched); + + /* Initialize DMA. NT does this in Phase 0 */ + HalpInitDma(); + + /* Do some HAL-specific initialization */ + HalpInitPhase1(); + } + + /* All done, return */ + return TRUE; +} + +/* + * @unimplemented + */ +VOID +NTAPI +HalReportResourceUsage(VOID) +{ + /* Initialize PCI bus. */ + HalpInitializePciBus(); + + /* FIXME: This is done in ReactOS MP HAL only*/ + //HaliReconfigurePciInterrupts(); + + /* FIXME: Report HAL Usage to kernel */ +} + +/* EOF */ diff --git a/reactos/hal/halamd64/generic/irq.S b/reactos/hal/halamd64/generic/irq.S new file mode 100644 index 00000000000..dc1f6d44b5b --- /dev/null +++ b/reactos/hal/halamd64/generic/irq.S @@ -0,0 +1,93 @@ +/* + * FILE: hal/halx86/generic/irq.S + * COPYRIGHT: See COPYING in the top level directory + * PURPOSE: Software, System and Hardware IRQ Management + * PROGRAMMER: Alex Ionescu (alex@relsoft.net) + */ + +/* INCLUDES ******************************************************************/ + +#include +#include +.intel_syntax noprefix + +.macro UNIMPLEMENTED func + jmp 2f +1: + .ascii "Sory, asm function " + .ascii func + .ascii " is unimplemented!\n\0" +2: + movabs rcx, offset 1b + call _DbgPrint + ret +.endm + + + +/* GLOBALS *******************************************************************/ + + + +/* FUNCTIONS *****************************************************************/ + +.globl _HalpInitPICs +.func _HalpInitPICs +_HalpInitPICs: +UNIMPLEMENTED "HalpInitPICs" + +.endfunc + +.globl _HalClearSoftwareInterrupt +.func _HalClearSoftwareInterrupt +_HalClearSoftwareInterrupt: + + /* Get IRR mask */ + mov eax, 1 + shl eax, cl + not eax + + /* Set IRR */ +// and gs:[KPCR_IRR], eax + ret +.endfunc + +.globl _HalRequestSoftwareInterrupt +.func _HalRequestSoftwareInterrupt +_HalRequestSoftwareInterrupt: +UNIMPLEMENTED "HalRequestSoftwareInterrupt" +.endfunc + +.globl _HalBeginSystemInterrupt +.func _HalBeginSystemInterrupt +_HalBeginSystemInterrupt: +UNIMPLEMENTED "HalBeginSystemInterrupt" +.endfunc + +.globl _HalpApcInterrupt +.func _HalpApcInterrupt +//TRAP_FIXUPS hapc_a, hapc_t, DoFixupV86, DoFixupAbios +_HalpApcInterrupt: +UNIMPLEMENTED "HalpApcInterrupt" +.endfunc + +.globl _HalpApcInterrupt2ndEntry +.func _HalpApcInterrupt2ndEntry +_HalpApcInterrupt2ndEntry: +UNIMPLEMENTED "HalpApcInterrupt2ndEntry" +.endfunc + +.globl _HalpDispatchInterrupt +.func _HalpDispatchInterrupt +//TRAP_FIXUPS hdpc_a, hdpc_t, DoFixupV86, DoFixupAbios +_HalpDispatchInterrupt: +UNIMPLEMENTED "HalpDispatchInterrupt" +.endfunc + + +.globl _HalpDispatchInterrupt2ndEntry +.func _HalpDispatchInterrupt2ndEntry +_HalpDispatchInterrupt2ndEntry: +UNIMPLEMENTED "HalpDispatchInterrupt2ndEntry" +.endfunc + diff --git a/reactos/hal/halamd64/generic/misc.c b/reactos/hal/halamd64/generic/misc.c new file mode 100644 index 00000000000..7eb1d9170f9 --- /dev/null +++ b/reactos/hal/halamd64/generic/misc.c @@ -0,0 +1,105 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: GPL - See COPYING in the top level directory + * FILE: hal/halx86/generic/misc.c + * PURPOSE: Miscellanous Routines + * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org) + * Eric Kohl (ekohl@abo.rhein-zeitung.de) + */ + +/* INCLUDES ******************************************************************/ + +#include +#define NDEBUG +#include + +/* PRIVATE FUNCTIONS *********************************************************/ + +VOID +NTAPI +HalpCheckPowerButton(VOID) +{ + /* Nothing to do on non-ACPI */ + return; +} + +PVOID +NTAPI +HalpMapPhysicalMemory64(IN PHYSICAL_ADDRESS PhysicalAddress, + IN ULONG NumberPage) +{ + /* Use kernel memory manager I/O map facilities */ + return MmMapIoSpace(PhysicalAddress, + NumberPage << PAGE_SHIFT, + MmNonCached); +} + +VOID +NTAPI +HalpUnmapVirtualAddress(IN PVOID VirtualAddress, + IN ULONG NumberPages) +{ + /* Use kernel memory manager I/O map facilities */ + MmUnmapIoSpace(VirtualAddress, NumberPages << PAGE_SHIFT); +} + +/* FUNCTIONS *****************************************************************/ + +/* + * @implemented + */ +VOID +NTAPI +HalHandleNMI(IN PVOID NmiInfo) +{ + UCHAR ucStatus; + + /* Get the NMI Flag */ + ucStatus = READ_PORT_UCHAR((PUCHAR)0x61); + + /* Display NMI failure string */ + HalDisplayString ("\n*** Hardware Malfunction\n\n"); + HalDisplayString ("Call your hardware vendor for support\n\n"); + + /* Check for parity error */ + if (ucStatus & 0x80) + { + /* Display message */ + HalDisplayString ("NMI: Parity Check / Memory Parity Error\n"); + } + + /* Check for I/O failure */ + if (ucStatus & 0x40) + { + /* Display message */ + HalDisplayString ("NMI: Channel Check / IOCHK\n"); + } + + /* Halt the system */ + HalDisplayString("\n*** The system has halted ***\n"); + //KeEnterKernelDebugger(); +} + +/* + * @implemented + */ +BOOLEAN +FASTCALL +HalSystemVectorDispatchEntry(IN ULONG Vector, + OUT PKINTERRUPT_ROUTINE **FlatDispatch, + OUT PKINTERRUPT_ROUTINE *NoConnection) +{ + /* Not implemented on x86 */ + return FALSE; +} + +/* + * @implemented + */ +VOID +NTAPI +KeFlushWriteBuffer(VOID) +{ + /* Not implemented on x86 */ + return; +} diff --git a/reactos/hal/halamd64/generic/systimer.S b/reactos/hal/halamd64/generic/systimer.S new file mode 100644 index 00000000000..298cea2619f --- /dev/null +++ b/reactos/hal/halamd64/generic/systimer.S @@ -0,0 +1,258 @@ +/* + * FILE: hal/halx86/generic/timer.S + * COPYRIGHT: See COPYING in the top level directory + * PURPOSE: System Timer Interrupt and Management + * PROGRAMMER: Alex Ionescu (alex@relsoft.net) + */ + +/* INCLUDES ******************************************************************/ + +#include +#include +.intel_syntax noprefix + +/* GLOBALS *******************************************************************/ + +_HalpLastPerfCounterLow: .long 0 +_HalpLastPerfCounterHigh: .long 0 +_HalpPerfCounterLow: .long 0 +_HalpPerfCounterHigh: .long 0 + +_UnhandledMsg: + .asciz "\n\x7\x7!!! Unhandled or Unexpected Code at line: %lx!!!\n" + +/* FUNCTIONS *****************************************************************/ + +.globl _KeStallExecutionProcessor +.func KeStallExecutionProcessor +_KeStallExecutionProcessor: + + /* Get the number of microseconds required */ + jecxz Done + + /* Multiply by the stall factor */ + mov eax, gs:[KPCR_STALL_SCALE_FACTOR] + mul ecx + + /* Align to 16 bytes */ + .align 16 + + /* Jump to subtraction loop */ + jmp SubtractLoop + + /* Align to 16 bytes */ + .align 16 + + /* Subtract one count */ +SubtractLoop: + sub eax, 1 + jnz SubtractLoop + +Done: + /* Return */ + ret 4 +.endfunc + +.global _KeQueryPerformanceCounter +.func KeQueryPerformanceCounter +_KeQueryPerformanceCounter: + + /* Check if we were called too early */ + cmp dword ptr _HalpCurrentRollOver, 0 + je NoCount + + /* Save volatiles */ + push rbx + push rsi + +LoopPreInt: + + /* Disable interrupts */ + pushf + cli + +LoopPostInt: + + /* Get the current value */ + mov ebx, _HalpPerfCounterLow + mov esi, _HalpPerfCounterHigh + + /* Read 8254 timer */ + mov al, 0 + out 0x43, al + jmp $+2 + in al, 0x40 + jmp $+2 + movzx ecx, al + in al, 0x40 + mov ch, al + + /* Enable interrupts and do a short wait */ + popf + nop + jmp $+2 + + /* Disable them again */ + pushf + cli + + /* Get the counter value again */ + mov eax, _HalpPerfCounterLow + mov edx, _HalpPerfCounterHigh + + /* Check if someone updated the counter */ + cmp eax, ebx + jnz LoopPostInt + cmp edx, esi + jnz LoopPostInt + + /* Check if the current 8254 value causes rollover */ + neg ecx + add ecx, _HalpCurrentRollOver + jnb DoRollOver + +SetSum: + + /* Calculate the sum */ + add eax, ecx + adc edx, 0 + + /* Check if we're above or below the last high value */ + cmp edx, _HalpLastPerfCounterHigh + jb short BelowHigh + jnz short BelowLow + + /* Check if we're above or below the last low value */ + cmp eax, _HalpLastPerfCounterLow + jb BelowHigh + +BelowLow: + + /* Update the last value and bring back interrupts */ + mov _HalpLastPerfCounterLow, eax + mov _HalpLastPerfCounterHigh, edx + popf + + /* Check if caller wants frequency */ + cmp dword ptr [esp+12], 0 + jz ReturnNoFreq + + /* Save hard-coded frequency */ + mov ecx, dword ptr [esp+12] + mov dword ptr [ecx], 1193182 + mov dword ptr [ecx+4], 0 + +ReturnNoFreq: + + /* Restore volatiles */ + pop rsi + pop rbx + ret 4 + +NoCount: + + /* Return empty, called too soon */ + mov eax, 0 + mov edx, 0 + ret 4 + +DoRollOver: + + /* We might have an incoming interrupt, save EFLAGS and reset rollover */ + mov esi, [esp] + mov ecx, _HalpCurrentRollOver + popf + + /* Check if interrupts were enabled and try again */ + test esi, EFLAGS_INTERRUPT_MASK + jnz LoopPreInt + + /* They're not, continue where we left */ + pushf + jmp SetSum + +BelowHigh: + + /* Get the last counter values */ + mov ebx, _HalpLastPerfCounterLow + mov esi, _HalpLastPerfCounterHigh + + /* Check if the previous value was 0 and go back if yes */ + mov ecx, ebx + or ecx, esi + jz BelowLow + + /* Make sure that the count is still valid */ + sub ebx, eax + sbb esi, edx + jnz InvalidCount + cmp ebx, _HalpCurrentRollOver + jg InvalidCount + + /* Fixup the count with the last known value */ + sub eax, ebx + sbb edx, esi + + /* We might have an incoming interrupt, save EFLAGS */ + mov ecx, [esp] + popf + + /* Check if interrupts were enabled and try again */ + test ecx, EFLAGS_INTERRUPT_MASK + jnz LoopPreInt + + /* They're not, continue where we left */ + pushf + jmp BelowLow + +InvalidCount: + popf + xor eax, eax + mov _HalpLastPerfCounterLow, eax + mov _HalpLastPerfCounterHigh, eax + jmp LoopPreInt +.endfunc + +.globl _HalpClockInterrupt +.func HalpClockInterrupt +//TRAP_FIXUPS hci_a, hci_t, DoFixupV86, DoFixupAbios +_HalpClockInterrupt: + + /* Enter trap */ +// INT_PROLOG hci_a, hci_t, DoPushFakeErrorCode + + /* Push vector and make stack for IRQL */ + push 0x30 + sub esp, 4 + + /* Begin the interrupt */ + push rsp + push 0x30 + push CLOCK_LEVEL +// call _HalBeginSystemInterrupt + + /* Check if it's spurious */ + or al, al + jz Spurious + + /* Update the performance counter */ + xor ebx, ebx + mov eax, _HalpCurrentRollOver + add _HalpPerfCounterLow, eax + adc _HalpPerfCounterHigh, ebx + + /* Get the time increment and check if someone changed the clock rate */ + mov eax, _HalpCurrentTimeIncrement + cmp _HalpClockSetMSRate, ebx + jz _KeUpdateSystemTime + + /* FIXME: Someone did! */ + int 3 + +Spurious: + + /* Exit the interrupt */ + add esp, 8 +// jmp _Kei386EoiHelper +.endfunc + diff --git a/reactos/hal/halamd64/include/bus.h b/reactos/hal/halamd64/include/bus.h new file mode 100644 index 00000000000..9f58d4055e0 --- /dev/null +++ b/reactos/hal/halamd64/include/bus.h @@ -0,0 +1,296 @@ +#ifndef __INTERNAL_HAL_BUS_H +#define __INTERNAL_HAL_BUS_H + +// +// Helper Macros +// +#define PASTE2(x,y) x ## y +#define POINTER_TO_(x) PASTE2(P,x) +#define READ_FROM(x) PASTE2(READ_PORT_, x) +#define WRITE_TO(x) PASTE2(WRITE_PORT_, x) + +// +// Declares a PCI Register Read/Write Routine +// +#define TYPE_DEFINE(x, y) \ + ULONG \ + NTAPI \ + x( \ + IN PPCIPBUSDATA BusData, \ + IN y PciCfg, \ + IN PUCHAR Buffer, \ + IN ULONG Offset \ + ) +#define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS); +#define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS); + +// +// Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue +// +#define TYPE1_START(x, y) \ + TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS) \ +{ \ + ULONG i = Offset % sizeof(ULONG); \ + PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG); \ + WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG); +#define TYPE1_END(y) \ + return sizeof(y); } +#define TYPE2_END TYPE1_END + +// +// PCI Register Read Type 1 Routine +// +#define TYPE1_READ(x, y) \ + TYPE1_START(x, y) \ + *((POINTER_TO_(y))Buffer) = \ + READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \ + TYPE1_END(y) + +// +// PCI Register Write Type 1 Routine +// +#define TYPE1_WRITE(x, y) \ + TYPE1_START(x, y) \ + WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \ + *((POINTER_TO_(y))Buffer)); \ + TYPE1_END(y) + +// +// Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue +// +#define TYPE2_START(x, y) \ + TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS) \ +{ \ + PciCfg->u.bits.RegisterNumber = (USHORT)Offset; + +// +// PCI Register Read Type 2 Routine +// +#define TYPE2_READ(x, y) \ + TYPE2_START(x, y) \ + *((POINTER_TO_(y))Buffer) = \ + READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \ + TYPE2_END(y) + +// +// PCI Register Write Type 2 Routine +// +#define TYPE2_WRITE(x, y) \ + TYPE2_START(x, y) \ + WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \ + *((POINTER_TO_(y))Buffer)); \ + TYPE2_END(y) + +typedef struct _PCIPBUSDATA +{ + PCIBUSDATA CommonData; + union + { + struct + { + PULONG Address; + ULONG Data; + } Type1; + struct + { + PUCHAR CSE; + PUCHAR Forward; + ULONG Base; + } Type2; + } Config; + ULONG MaxDevice; +} PCIPBUSDATA, *PPCIPBUSDATA; + +typedef ULONG +(NTAPI *FncConfigIO)( + IN PPCIPBUSDATA BusData, + IN PVOID State, + IN PUCHAR Buffer, + IN ULONG Offset +); + +typedef VOID +(NTAPI *FncSync)( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PKIRQL Irql, + IN PVOID State +); + +typedef VOID +(NTAPI *FncReleaseSync)( + IN PBUS_HANDLER BusHandler, + IN KIRQL Irql +); + +typedef struct _PCI_CONFIG_HANDLER +{ + FncSync Synchronize; + FncReleaseSync ReleaseSynchronzation; + FncConfigIO ConfigRead[3]; + FncConfigIO ConfigWrite[3]; +} PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER; + +typedef struct _PCI_REGISTRY_INFO_INTERNAL +{ + UCHAR MajorRevision; + UCHAR MinorRevision; + UCHAR NoBuses; + UCHAR HardwareMechanism; + ULONG ElementCount; + PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY]; +} PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL; + +/* FUNCTIONS *****************************************************************/ + +VOID +NTAPI +HalpPCISynchronizeType1( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PKIRQL Irql, + IN PPCI_TYPE1_CFG_BITS PciCfg +); + +VOID +NTAPI +HalpPCIReleaseSynchronzationType1( + IN PBUS_HANDLER BusHandler, + IN KIRQL Irql +); + +VOID +NTAPI +HalpPCISynchronizeType2( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PKIRQL Irql, + IN PPCI_TYPE2_ADDRESS_BITS PciCfg +); + +VOID +NTAPI +HalpPCIReleaseSynchronizationType2( + IN PBUS_HANDLER BusHandler, + IN KIRQL Irql +); + +TYPE1_DEFINE(HalpPCIReadUcharType1); +TYPE1_DEFINE(HalpPCIReadUshortType1); +TYPE1_DEFINE(HalpPCIReadUlongType1); +TYPE2_DEFINE(HalpPCIReadUcharType2); +TYPE2_DEFINE(HalpPCIReadUshortType2); +TYPE2_DEFINE(HalpPCIReadUlongType2); +TYPE1_DEFINE(HalpPCIWriteUcharType1); +TYPE1_DEFINE(HalpPCIWriteUshortType1); +TYPE1_DEFINE(HalpPCIWriteUlongType1); +TYPE2_DEFINE(HalpPCIWriteUcharType2); +TYPE2_DEFINE(HalpPCIWriteUshortType2); +TYPE2_DEFINE(HalpPCIWriteUlongType2); + +BOOLEAN +NTAPI +HalpValidPCISlot( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot +); + +VOID +NTAPI +HalpReadPCIConfig( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length +); + +VOID +NTAPI +HalpWritePCIConfig( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length +); + +ULONG +NTAPI +HalpGetSystemInterruptVector( + ULONG BusNumber, + ULONG BusInterruptLevel, + ULONG BusInterruptVector, + PKIRQL Irql, + PKAFFINITY Affinity +); + +ULONG +NTAPI +HalpGetCmosData( + IN ULONG BusNumber, + IN ULONG SlotNumber, + IN PVOID Buffer, + IN ULONG Length +); + +ULONG +NTAPI +HalpSetCmosData( + IN ULONG BusNumber, + IN ULONG SlotNumber, + IN PVOID Buffer, + IN ULONG Length +); + +ULONG +NTAPI +HalpGetPCIData( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootBusHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PUCHAR Buffer, + IN ULONG Offset, + IN ULONG Length +); + +ULONG +NTAPI +HalpSetPCIData( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootBusHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PUCHAR Buffer, + IN ULONG Offset, + IN ULONG Length +); + +NTSTATUS +NTAPI +HalpAssignPCISlotResources( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN PUNICODE_STRING RegistryPath, + IN PUNICODE_STRING DriverClassName OPTIONAL, + IN PDRIVER_OBJECT DriverObject, + IN PDEVICE_OBJECT DeviceObject OPTIONAL, + IN ULONG Slot, + IN OUT PCM_RESOURCE_LIST *pAllocatedResources +); + +VOID +NTAPI +HalpInitializePciBus( + VOID +); + +extern ULONG HalpBusType; +extern BOOLEAN HalpPCIConfigInitialized; +extern BUS_HANDLER HalpFakePciBusHandler; +extern ULONG HalpMinPciBus, HalpMaxPciBus; + +#endif /* __INTERNAL_HAL_BUS_H */ + +/* EOF */ + + diff --git a/reactos/hal/halamd64/include/hal.h b/reactos/hal/halamd64/include/hal.h index e16859b753f..c793782d06a 100644 --- a/reactos/hal/halamd64/include/hal.h +++ b/reactos/hal/halamd64/include/hal.h @@ -1,9 +1,9 @@ /* - * PROJECT: ReactOS HAL - * LICENSE: BSD - See COPYING.ARM in the top level directory - * FILE: hal/halarm/include/hal.h - * PURPOSE: Hardware Abstraction Layer Header - * PROGRAMMERS: ReactOS Portable Systems Group + * COPYRIGHT: See COPYING in the top level directory + * PROJECT: ReactOS Hardware Abstraction Layer + * FILE: hal/halx86/include/hal.h + * PURPOSE: HAL Header + * PROGRAMMER: Alex Ionescu (alex@relsoft.net) */ /* INCLUDES ******************************************************************/ @@ -28,14 +28,23 @@ #include #include #include -#include #include #include #include #include +/* Internal kernel headers */ +#include "internal/pci.h" +#include "internal/i386/intrin_i.h" + /* Internal HAL Headers */ +//#include "apic.h" +#include "bus.h" +//#include "halirq.h" +//#include "haldma.h" #include "halp.h" +//#include "mps.h" +//#include "ioapic.h" /* Helper Header */ #include diff --git a/reactos/hal/halamd64/include/halp.h b/reactos/hal/halamd64/include/halp.h index 9428bbd370c..e1b91270914 100644 --- a/reactos/hal/halamd64/include/halp.h +++ b/reactos/hal/halamd64/include/halp.h @@ -1,16 +1,162 @@ +/* + * + */ + #ifndef __INTERNAL_HAL_HAL_H #define __INTERNAL_HAL_HAL_H -// -// amd64 Headers -// -#include -#include +#define HAL_APC_REQUEST 0 +#define HAL_DPC_REQUEST 1 +/* CMOS Registers and Ports */ +#define CMOS_CONTROL_PORT (PUCHAR)0x70 +#define CMOS_DATA_PORT (PUCHAR)0x71 +#define RTC_REGISTER_A 0x0A +#define RTC_REGISTER_B 0x0B +#define RTC_REG_A_UIP 0x80 +#define RTC_REGISTER_CENTURY 0x32 + +/* Timer Registers and Ports */ +#define TIMER_CONTROL_PORT 0x43 +#define TIMER_DATA_PORT0 0x40 +#define TIMER_SC0 0 +#define TIMER_BOTH 0x30 +#define TIMER_MD2 0x4 + +/* Conversion functions */ +#define BCD_INT(bcd) \ + (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F)) +#define INT_BCD(int) \ + (UCHAR)(((int / 10) << 4) + (int % 10)) + +/* adapter.c */ +PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses); + +/* bus.c */ +VOID NTAPI HalpInitNonBusHandler (VOID); + +/* irql.c */ +VOID NTAPI HalpInitPICs(VOID); + +/* udelay.c */ +VOID NTAPI HalpInitializeClock(VOID); + +/* pci.c */ +VOID HalpInitPciBus (VOID); + +/* dma.c */ +VOID HalpInitDma (VOID); + +/* Non-generic initialization */ +VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock); +VOID HalpInitPhase1(VOID); +VOID NTAPI HalpClockInterrupt(VOID); // -// WDK Hack +// KD Support // -#define KdComPortInUse _KdComPortInUse +VOID +NTAPI +HalpCheckPowerButton( + VOID +); + +VOID +NTAPI +HalpRegisterKdSupportFunctions( + VOID +); + +NTSTATUS +NTAPI +HalpSetupPciDeviceForDebugging( + IN PVOID LoaderBlock, + IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice +); + +NTSTATUS +NTAPI +HalpReleasePciDeviceForDebugging( + IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice +); + +// +// Memory routines +// +PVOID +NTAPI +HalpMapPhysicalMemory64( + IN PHYSICAL_ADDRESS PhysicalAddress, + IN ULONG NumberPage +); + +VOID +NTAPI +HalpUnmapVirtualAddress( + IN PVOID VirtualAddress, + IN ULONG NumberPages +); + +/* sysinfo.c */ +NTSTATUS +NTAPI +HaliQuerySystemInformation( + IN HAL_QUERY_INFORMATION_CLASS InformationClass, + IN ULONG BufferSize, + IN OUT PVOID Buffer, + OUT PULONG ReturnedLength +); + +NTSTATUS +NTAPI +HaliSetSystemInformation( + IN HAL_SET_INFORMATION_CLASS InformationClass, + IN ULONG BufferSize, + IN OUT PVOID Buffer +); + +// +// BIOS Routines +// +BOOLEAN +NTAPI +HalpBiosDisplayReset( + VOID +); + +ULONG +NTAPI +HalpBorrowTss( + VOID +); + +ULONG +NTAPI +HalpReturnTss( + ULONG SavedTss +); + +VOID +NTAPI +HalpBiosCall( + VOID +); + +VOID +NTAPI +HalpTrap0D( + VOID +); + +VOID +NTAPI +HalpTrap06( + VOID +); + +extern PVOID HalpRealModeStart; +extern PVOID HalpRealModeEnd; + +extern KSPIN_LOCK HalpSystemHardwareLock; #endif /* __INTERNAL_HAL_HAL_H */ diff --git a/reactos/hal/halamd64/up/halup.rbuild b/reactos/hal/halamd64/up/halup.rbuild index 8308980b26a..eaa56d7f133 100644 --- a/reactos/hal/halamd64/up/halup.rbuild +++ b/reactos/hal/halamd64/up/halup.rbuild @@ -1,14 +1,17 @@ - - + + - ../include + ../include include - halamd64_generic + hal_generic_amd64 + hal_generic_pc + hal_generic ntoskrnl halinit_up.c halup.rc + processor.c diff --git a/reactos/hal/halamd64/up/processor.c b/reactos/hal/halamd64/up/processor.c new file mode 100644 index 00000000000..669c82b5910 --- /dev/null +++ b/reactos/hal/halamd64/up/processor.c @@ -0,0 +1,87 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: GPL - See COPYING in the top level directory + * FILE: hal/halamd64/up/processor.c + * PURPOSE: HAL Processor Routines + * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org) + */ + +/* INCLUDES ******************************************************************/ + +#include +#define NDEBUG +#include + +LONG HalpActiveProcessors; +KAFFINITY HalpDefaultInterruptAffinity; + +/* FUNCTIONS *****************************************************************/ + +/* + * @implemented + */ +VOID +NTAPI +HalInitializeProcessor(IN ULONG ProcessorNumber, + IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + /* Set default IDR and stall count */ +// KeGetPcr()->IDR = 0xFFFFFFFB; + KeGetPcr()->StallScaleFactor = INITIAL_STALL_COUNT; + + /* Update the interrupt affinity and processor mask */ + InterlockedBitTestAndSet(&HalpActiveProcessors, ProcessorNumber); + InterlockedBitTestAndSet((PLONG)&HalpDefaultInterruptAffinity, + ProcessorNumber); + + /* Register routines for KDCOM */ + HalpRegisterKdSupportFunctions(); +} + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalAllProcessorsStarted(VOID) +{ + /* Do nothing */ + return TRUE; +} + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalStartNextProcessor(IN PLOADER_PARAMETER_BLOCK LoaderBlock, + IN PKPROCESSOR_STATE ProcessorState) +{ + /* Ready to start */ + return FALSE; +} + +/* + * @implemented + */ +VOID +NTAPI +HalProcessorIdle(VOID) +{ + /* Enable interrupts and halt the processor */ + _enable(); + Ke386HaltProcessor(); +} + +/* + * @implemented + */ +VOID +NTAPI +HalRequestIpi(KAFFINITY TargetSet) +{ + /* Not implemented on NT */ + __debugbreak(); +} + +/* EOF */ diff --git a/reactos/hal/halx86/hal_generic_amd64.rbuild b/reactos/hal/halx86/hal_generic_amd64.rbuild new file mode 100644 index 00000000000..c3d5e5b121d --- /dev/null +++ b/reactos/hal/halx86/hal_generic_amd64.rbuild @@ -0,0 +1,28 @@ + + + + + include + include + + + + beep.c + bus.c + cmos.c + dma.c + drive.c + display.c + profil.c + reboot.c + sysinfo.c + timer.c + + + + + + hal.h + + +