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- Add roothub status operations.
- Ports count is correctly detected now. - Added all necessary stubs for HCD interface, so that usbdriver can work further. svn path=/trunk/; revision=30596
This commit is contained in:
Aleksey Bragin
parent
9a0b86e617
commit
418e0cc05a
2 changed files with 255 additions and 17 deletions
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@ -39,8 +39,13 @@ VOID ohci_init_hcd_interface(POHCI_DEV ohci);
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// shared with EHCI
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NTSTATUS ehci_dispatch_irp(IN PDEVICE_OBJECT DeviceObject, IN PIRP irp);
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PUSB_DEV_MANAGER ehci_get_dev_mgr(PHCD hcd);
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VOID ehci_set_dev_mgr(PHCD hcd, PUSB_DEV_MANAGER dev_mgr);
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VOID ehci_set_id(PHCD hcd, UCHAR id);
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UCHAR ehci_get_id(PHCD hcd);
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UCHAR ehci_alloc_addr(PHCD hcd);
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VOID ehci_free_addr(PHCD hcd, UCHAR addr);
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BOOLEAN NTAPI ehci_cal_cpu_freq(PVOID context);
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extern USB_DEV_MANAGER g_dev_mgr;
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@ -57,6 +62,31 @@ extern USB_DEV_MANAGER g_dev_mgr;
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#define OHCI_READ_PORT_USHORT( psh ) ( *psh )
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#define OHCI_WRITE_PORT_USHORT( psh, src ) ( *psh = ( USHORT )src )
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/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
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* The erratum (#4) description is incorrect. AMD's workaround waits
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* till some bits (mostly reserved) are clear; ok for all revs.
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*/
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#define read_roothub(hc, register, mask) ({ \
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ULONG temp = OHCI_READ_PORT_ULONG(&((hc)->regs->roothub.register)); \
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if (temp == -1) \
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/*disable (hc)*/; \
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/*else if (hc->flags & OHCI_QUIRK_AMD756) \
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while (temp & mask) \
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temp = ohci_readl (hc, &hc->regs->roothub.register); */ \
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temp; })
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static ULONG roothub_a (POHCI_DEV hc)
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{ return read_roothub (hc, a, 0xfc0fe000); }
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/*
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static inline u32 roothub_b (struct ohci_hcd *hc)
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{ return ohci_readl (hc, &hc->regs->roothub.b); }
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static inline u32 roothub_status (struct ohci_hcd *hc)
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{ return ohci_readl (hc, &hc->regs->roothub.status); }
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static u32 roothub_portstatus (struct ohci_hcd *hc, int i)
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{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
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*/
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VOID
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ohci_wait_ms(POHCI_DEV ohci, LONG ms)
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{
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@ -261,6 +291,7 @@ ohci_alloc(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path, ULONG bus_addr, PU
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//before we connect the interrupt, we have to init ohci
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pdev_ext->ohci->pdev_ext = pdev_ext;
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pdev_ext->ohci->regs = (POHCI_REGS)pdev_ext->ohci->port_base;
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KeInitializeTimer(&pdev_ext->ohci->reset_timer);
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@ -292,6 +323,23 @@ ohci_alloc(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path, ULONG bus_addr, PU
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//ohci_usb_reset (ohci);
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}
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/* Disable HC interrupts */
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OHCI_WRITE_PORT_ULONG((PULONG)(pdev_ext->ohci->port_base + OHCI_INTRDISABLE), OHCI_INTR_MIE);
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// flush the writes
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(VOID)OHCI_READ_PORT_ULONG((PULONG)(pdev_ext->ohci->port_base + OHCI_CONTROL));
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/* Read the number of ports unless overridden */
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pdev_ext->ohci->num_ports = roothub_a(pdev_ext->ohci) & RH_A_NDP;
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DbgPrint("OHCI: %d ports\n", pdev_ext->ohci->num_ports);
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//ohci->hcca = dma_alloc_coherent (ohci_to_hcd(ohci)->self.controller,
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// sizeof *ohci->hcca, &ohci->hcca_dma, 0);
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//if (!ohci->hcca)
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// return -ENOMEM;
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//if ((ret = ohci_mem_init (ohci)) < 0)
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// ohci_stop (ohci_to_hcd(ohci));
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#if 0
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//init ehci_caps
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@ -413,30 +461,217 @@ ohci_create_device(PDRIVER_OBJECT drvr_obj, PUSB_DEV_MANAGER dev_mgr)
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return pdev;
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}
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BOOLEAN
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ohci_start(PHCD hcd)
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{
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//ULONG tmp;
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//PBYTE base;
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//PEHCI_USBCMD_CONTENT usbcmd;
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//POHCI_DEV ohci;
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if (hcd == NULL)
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return FALSE;
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return TRUE;
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#if 0
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ehci = struct_ptr(hcd, EHCI_DEV, hcd_interf);
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base = ehci->port_base;
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// stop the controller
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tmp = EHCI_READ_PORT_ULONG((PULONG) (base + EHCI_USBCMD));
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usbcmd = (PEHCI_USBCMD_CONTENT) & tmp;
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usbcmd->run_stop = 0;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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// wait the controller stop( ehci spec, 16 microframe )
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usb_wait_ms_dpc(2);
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// reset the controller
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usbcmd = (PEHCI_USBCMD_CONTENT) & tmp;
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usbcmd->hcreset = TRUE;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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for(;;)
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{
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// interval.QuadPart = -100 * 10000; // 10 ms
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// KeDelayExecutionThread( KernelMode, FALSE, &interval );
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KeStallExecutionProcessor(10);
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tmp = EHCI_READ_PORT_ULONG((PULONG) (base + EHCI_USBCMD));
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if (!usbcmd->hcreset)
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break;
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}
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// prepare the registers
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_CTRLDSSEGMENT), 0);
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// turn on all the int
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBINTR),
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EHCI_USBINTR_INTE | EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR
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// EHCI_USBINTR_FLROVR | \ // it is noisy
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// EHCI_USBINTR_PC // we detect it by polling
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);
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// write the list base reg
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_PERIODICLISTBASE), ehci->frame_list_phys_addr.LowPart);
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_ASYNCLISTBASE), ehci->skel_async_qh->phys_addr & ~(0x1f));
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usbcmd->int_threshold = 1;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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// let's rock
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usbcmd->run_stop = 1;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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// set the configuration flag
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_CONFIGFLAG), 1);
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// enable the list traversaling
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usbcmd->async_enable = 1;
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usbcmd->periodic_enable = 1;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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#endif
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return TRUE;
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}
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ULONG
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ohci_get_type(PHCD hcd)
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{
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return HCD_TYPE_OHCI; // ( hcd->flags & HCD_TYPE_MASK );
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}
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NTSTATUS
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ohci_submit_urb2(PHCD hcd, PUSB_DEV pdev, PUSB_ENDPOINT pendp, PURB purb)
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{
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return STATUS_UNSUCCESSFUL;
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}
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PUSB_DEV
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ohci_get_root_hub(PHCD hcd)
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{
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return ohci_from_hcd(hcd)->root_hub;
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}
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VOID
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ohci_set_root_hub(PHCD hcd, PUSB_DEV root_hub)
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{
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if (hcd == NULL || root_hub == NULL)
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return;
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ohci_from_hcd(hcd)->root_hub = root_hub;
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return;
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}
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BOOLEAN
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ohci_remove_device2(PHCD hcd, PUSB_DEV pdev)
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{
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if (hcd == NULL || pdev == NULL)
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return FALSE;
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return FALSE;
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//return ehci_remove_device(ehci_from_hcd(hcd), pdev);
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}
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BOOLEAN
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ohci_hcd_release(PHCD hcd)
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{
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POHCI_DEV ohci;
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POHCI_DEVICE_EXTENSION pdev_ext;
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if (hcd == NULL)
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return FALSE;
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ohci = ohci_from_hcd(hcd);
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pdev_ext = ohci->pdev_ext;
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return FALSE;//ehci_release(pdev_ext->pdev_obj);
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}
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NTSTATUS
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ohci_cancel_urb2(PHCD hcd, PUSB_DEV pdev, PUSB_ENDPOINT pendp, PURB purb)
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{
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POHCI_DEV ohci;
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if (hcd == NULL)
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return STATUS_INVALID_PARAMETER;
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ohci = ohci_from_hcd(hcd);
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return STATUS_UNSUCCESSFUL;//ehci_cancel_urb(ehci, pdev, pendp, purb);
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}
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VOID
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ohci_generic_urb_completion(PURB purb, PVOID context)
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{
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}
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BOOLEAN
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ohci_rh_reset_port(PHCD hcd, UCHAR port_idx)
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{
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//ULONG i;
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POHCI_DEV ohci;
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//ULONG status;
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//UCHAR port_count;
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if (hcd == NULL)
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return FALSE;
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ohci = ohci_from_hcd(hcd);
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//port_count = (UCHAR) ((PEHCI_HCS_CONTENT) & ehci->ehci_caps.hcs_params)->port_count;
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//if (port_idx < 1 || port_idx > port_count)
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// return FALSE;
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//usb_dbg_print(DBGLVL_MAXIMUM, ("ohci_rh_reset_port(): status after written=0x%x\n", status));
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return TRUE;
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}
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NTSTATUS
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ohci_hcd_dispatch(PHCD hcd, LONG disp_code, PVOID param)
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{
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POHCI_DEV ohci;
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if (hcd == NULL)
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return STATUS_INVALID_PARAMETER;
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ohci = ohci_from_hcd(hcd);
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#if 0
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switch (disp_code)
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{
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case HCD_DISP_READ_PORT_COUNT:
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{
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if (param == NULL)
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return STATUS_INVALID_PARAMETER;
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*((PUCHAR) param) = (UCHAR) HCS_N_PORTS(ehci->ehci_caps.hcs_params);
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return STATUS_SUCCESS;
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}
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case HCD_DISP_READ_RH_DEV_CHANGE:
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{
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if (ehci_rh_get_dev_change(hcd, param) == FALSE)
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return STATUS_INVALID_PARAMETER;
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return STATUS_SUCCESS;
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}
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}
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#endif
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return STATUS_NOT_IMPLEMENTED;
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}
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VOID
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ohci_init_hcd_interface(POHCI_DEV ohci)
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{
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ohci->hcd_interf.hcd_set_dev_mgr = ehci_set_dev_mgr;
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#if 0
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ohci->hcd_interf.hcd_get_dev_mgr = ehci_get_dev_mgr;
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ohci->hcd_interf.hcd_get_type = ehci_get_type;
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#endif
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ohci->hcd_interf.hcd_get_type = ohci_get_type;
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ohci->hcd_interf.hcd_set_id = ehci_set_id;
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#if 0
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ohci->hcd_interf.hcd_get_id = ehci_get_id;
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ohci->hcd_interf.hcd_alloc_addr = ehci_alloc_addr;
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ohci->hcd_interf.hcd_free_addr = ehci_free_addr;
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ohci->hcd_interf.hcd_submit_urb = ehci_submit_urb2;
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ohci->hcd_interf.hcd_generic_urb_completion = ehci_generic_urb_completion;
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ohci->hcd_interf.hcd_get_root_hub = ehci_get_root_hub;
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ohci->hcd_interf.hcd_set_root_hub = ehci_set_root_hub;
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ohci->hcd_interf.hcd_remove_device = ehci_remove_device2;
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ohci->hcd_interf.hcd_rh_reset_port = ehci_rh_reset_port;
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ohci->hcd_interf.hcd_release = ehci_hcd_release;
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ohci->hcd_interf.hcd_cancel_urb = ehci_cancel_urb2;
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ohci->hcd_interf.hcd_start = ehci_start;
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ohci->hcd_interf.hcd_dispatch = ehci_hcd_dispatch;
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#endif
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ohci->hcd_interf.hcd_submit_urb = ohci_submit_urb2;
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ohci->hcd_interf.hcd_generic_urb_completion = ohci_generic_urb_completion;
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ohci->hcd_interf.hcd_get_root_hub = ohci_get_root_hub;
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ohci->hcd_interf.hcd_set_root_hub = ohci_set_root_hub;
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ohci->hcd_interf.hcd_remove_device = ohci_remove_device2;
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ohci->hcd_interf.hcd_rh_reset_port = ohci_rh_reset_port;
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ohci->hcd_interf.hcd_release = ohci_hcd_release;
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ohci->hcd_interf.hcd_cancel_urb = ohci_cancel_urb2;
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ohci->hcd_interf.hcd_start = ohci_start;
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ohci->hcd_interf.hcd_dispatch = ohci_hcd_dispatch;
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ohci->hcd_interf.flags = HCD_TYPE_OHCI; //hcd types | hcd id
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}
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@ -119,7 +119,7 @@
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* You must use readl() and writel() (in <asm/io.h>) to access these fields!!
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* Layout is in section 7 (and appendix B) of the spec.
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*/
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struct _OHCI_REGS
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typedef struct _OHCI_REGS
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{
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/* control and status registers (section 7.1) */
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ULONG revision;
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@ -164,6 +164,9 @@ typedef struct _OHCI_DEV
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PHYSICAL_ADDRESS ohci_reg_base; // io space
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BOOLEAN port_mapped;
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PBYTE port_base; // note: added by ehci_caps.length, operational regs base addr, not the actural base
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struct _OHCI_REGS *regs;
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USHORT num_ports;
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KTIMER reset_timer; //used to reset the host controller
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struct _OHCI_DEVICE_EXTENSION *pdev_ext;
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@ -193,6 +196,6 @@ typedef struct _OHCI_DEVICE_EXTENSION
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KDPC ohci_dpc;
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} OHCI_DEVICE_EXTENSION, *POHCI_DEVICE_EXTENSION;
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#define ohci_from_hcd( hCD ) ( struct_ptr( ( hCD ), OHCI_DEV, hcd_interf ) )
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#endif /* __OHCI_H__ */
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