- Add support for Cyrix CPUs by checking and applying a workaround for the Cyrix 6x COMA bug (description here: http://gwyn.tux.org/~balsa/linux/cyrix/p11.html).
See issue #5610 for more details.

svn path=/trunk/; revision=48801
This commit is contained in:
Aleksey Bragin 2010-09-18 09:14:45 +00:00
parent becc9ed282
commit 41106fa541

View file

@ -105,6 +105,17 @@ RDMSR(IN ULONG Register)
return __readmsr(Register);
}
/* NSC/Cyrix CPU configuration register index */
#define CX86_CCR1 0xc1
/* NSC/Cyrix CPU indexed register access macros */
#define getCx86(reg) ({ WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22,(reg)); READ_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23); })
#define setCx86(reg, data) do { \
WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22,(reg)); \
WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23,(data)); \
} while (0)
/* FUNCTIONS *****************************************************************/
VOID
@ -241,7 +252,7 @@ KiGetFeatureBits(VOID)
PKPRCB Prcb = KeGetCurrentPrcb();
ULONG Vendor;
ULONG FeatureBits = KF_WORKING_PTE;
ULONG Reg[4], Dummy;
ULONG Reg[4], Dummy, Ccr1;
BOOLEAN ExtendedCPUID = TRUE;
ULONG CpuFeatures = 0;
@ -352,7 +363,22 @@ KiGetFeatureBits(VOID)
/* Cyrix CPUs */
case CPU_CYRIX:
/* FIXME: CMPXCGH8B */
/* Workaround the "COMA" bug on 6x family of Cyrix CPUs */
if (Prcb->CpuType == 6 &&
Prcb->CpuStep <= 1)
{
/* Get CCR1 value */
Ccr1 = getCx86(CX86_CCR1);
/* Enable the NO_LOCK bit */
Ccr1 |= 0x10;
/* Set the new CCR1 value */
setCx86(CX86_CCR1, Ccr1);
}
/* Set the current features */
CpuFeatures = Reg[3];
break;