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- Fix HalGetAdapter for ISA adapters.

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- Fix layout of EISA_CONTROL structure.

svn path=/trunk/; revision=12003
This commit is contained in:
Filip Navara 2004-12-10 19:05:33 +00:00
parent 821da7d6f9
commit 40d1739c83
2 changed files with 6 additions and 7 deletions
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9
reactos/hal/halx86/generic/dma.c
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@ -1,4 +1,4 @@
/* $Id: dma.c,v 1.1 2004/12/03 20:10:43 gvg Exp $ /* $Id: dma.c,v 1.2 2004/12/10 19:05:33 navaraf Exp $
* *
* COPYRIGHT: See COPYING in the top level directory * COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel * PROJECT: ReactOS kernel
@ -154,9 +154,8 @@ HalGetAdapter (PDEVICE_DESCRIPTION DeviceDescription,
} }
/* Devices that support Scatter/Gather do not need Map Registers */ /* Devices that support Scatter/Gather do not need Map Registers */
if (DeviceDescription->ScatterGather && if (DeviceDescription->ScatterGather ||
(DeviceDescription->InterfaceType == Eisa || DeviceDescription->InterfaceType == PCIBus) {
DeviceDescription->InterfaceType == PCIBus)) {
*NumberOfMapRegisters = 0; *NumberOfMapRegisters = 0;
} }
@ -176,7 +175,7 @@ HalGetAdapter (PDEVICE_DESCRIPTION DeviceDescription,
ChannelSelect = DeviceDescription->DmaChannel & 0x03; ChannelSelect = DeviceDescription->DmaChannel & 0x03;
/* Get the Controller Setup */ /* Get the Controller Setup */
Controller = (DeviceDescription->DmaChannel & 0x04) ? 1 : 2; Controller = (DeviceDescription->DmaChannel & 0x04) ? 2 : 1;
/* Get the Adapter Object */ /* Get the Adapter Object */
if (HalpEisaAdapter[DeviceDescription->DmaChannel] != NULL) { if (HalpEisaAdapter[DeviceDescription->DmaChannel] != NULL) {

4
reactos/hal/halx86/include/hal.h
View file

@ -284,10 +284,10 @@ typedef struct _EISA_CONTROL {
UCHAR Reserved9[30]; /* 0A2h-0BFh */ UCHAR Reserved9[30]; /* 0A2h-0BFh */
/* DMA Controller 2 */ /* DMA Controller 2 */
DMA1_CONTROL DmaController2; /* 0C0h-0DFh */ DMA1_CONTROL DmaController2; /* 0C0h-0CFh */
/* System Reserved Ports */ /* System Reserved Ports */
UCHAR SystemReserved[800]; /* 0E0h-3FFh */ UCHAR SystemReserved[816]; /* 0D0h-3FFh */
/* Extended DMA Registers, Controller 1 */ /* Extended DMA Registers, Controller 1 */
UCHAR DmaHighByteCount1[8]; /* 400h-407h */ UCHAR DmaHighByteCount1[8]; /* 400h-407h */