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[NTOS]: Use SYSTEM_PD_SIZE instead of assuming that this is PAGE_SIZE, since this is not the case on (future) ARM and (current) AMD64 ports.

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[NTOS]: Remove some magic numbers in the pool code, using PTE_COUNT, MiAddressToPde, when needed. Also, the expansion code uses PDEs, not PTEs, so differentiate this, because on some systems (ARM), there are different structures for both.
[NTOS]: Use MI_WRITE_INVALID_PTE.
ARM3 paged pool now works, the expansion bug has been fixed (and the code is more portable). Expect to see it gradually enabled soon.

svn path=/trunk/; revision=48939
This commit is contained in:
Sir Richard 2010-09-30 03:26:13 +00:00
parent 39ab07fe2a
commit 40ba0f9329
2 changed files with 32 additions and 32 deletions
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7
reactos/ntoskrnl/mm/ARM3/pagfault.c
View file

@ -107,16 +107,11 @@ MiCheckPdeForPagedPool(IN PVOID Address)
#ifdef _M_AMD64 #ifdef _M_AMD64
ASSERT(FALSE); ASSERT(FALSE);
#else #else
/* This seems to be making the assumption that one PDE is one page long */
C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT)));
// //
// Copy it from our double-mapped system page directory // Copy it from our double-mapped system page directory
// //
InterlockedExchangePte(PointerPde, InterlockedExchangePte(PointerPde,
MmSystemPagePtes[((ULONG_PTR)PointerPde & MmSystemPagePtes[(ULONG_PTR)PointerPde & (SYSTEM_PD_SIZE - 1)].u.Long);
(PAGE_SIZE - 1)) /
sizeof(MMPTE)].u.Long);
#endif #endif
} }

53
reactos/ntoskrnl/mm/ARM3/pool.c
View file

@ -377,7 +377,10 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
KIRQL OldIrql; KIRQL OldIrql;
PLIST_ENTRY NextEntry, NextHead, LastHead; PLIST_ENTRY NextEntry, NextHead, LastHead;
PMMPTE PointerPte, StartPte; PMMPTE PointerPte, StartPte;
PMMPDE PointerPde;
ULONG EndAllocation;
MMPTE TempPte; MMPTE TempPte;
MMPDE TempPde;
PMMPFN Pfn1; PMMPFN Pfn1;
PVOID BaseVa, BaseVaStart; PVOID BaseVa, BaseVaStart;
PMMFREE_POOL_ENTRY FreeEntry; PMMFREE_POOL_ENTRY FreeEntry;
@ -409,7 +412,7 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
// //
// Get the page bit count // Get the page bit count
// //
i = ((SizeInPages - 1) / 1024) + 1; i = ((SizeInPages - 1) / PTE_COUNT) + 1;
DPRINT1("Paged pool expansion: %d %x\n", i, SizeInPages); DPRINT1("Paged pool expansion: %d %x\n", i, SizeInPages);
// //
@ -450,15 +453,15 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
} }
// //
// Get the template PTE we'll use to expand // Get the template PDE we'll use to expand
// //
TempPte = ValidKernelPte; TempPde = ValidKernelPde;
// //
// Get the first PTE in expansion space // Get the first PTE in expansion space
// //
PointerPte = MmPagedPoolInfo.NextPdeForPagedPoolExpansion; PointerPde = MmPagedPoolInfo.NextPdeForPagedPoolExpansion;
BaseVa = MiPteToAddress(PointerPte); BaseVa = MiPteToAddress(PointerPde);
BaseVaStart = BaseVa; BaseVaStart = BaseVa;
// //
@ -470,11 +473,13 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
// //
// It should not already be valid // It should not already be valid
// //
ASSERT(PointerPte->u.Hard.Valid == 0); ASSERT(PointerPde->u.Hard.Valid == 0);
/* Request a page */ /* Request a page */
DPRINT1("Requesting %d PDEs\n", i);
PageFrameNumber = MiRemoveAnyPage(MI_GET_NEXT_COLOR()); PageFrameNumber = MiRemoveAnyPage(MI_GET_NEXT_COLOR());
TempPte.u.Hard.PageFrameNumber = PageFrameNumber; TempPde.u.Hard.PageFrameNumber = PageFrameNumber;
DPRINT1("We have a PDE: %lx\n", PageFrameNumber);
#if (_MI_PAGING_LEVELS >= 3) #if (_MI_PAGING_LEVELS >= 3)
/* On PAE/x64 systems, there's no double-buffering */ /* On PAE/x64 systems, there's no double-buffering */
@ -483,24 +488,23 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
// //
// Save it into our double-buffered system page directory // Save it into our double-buffered system page directory
// //
/* This seems to be making the assumption that one PDE is one page long */ MmSystemPagePtes[(ULONG_PTR)PointerPde & (SYSTEM_PD_SIZE - 1)] = TempPde;
C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT)));
MmSystemPagePtes[(ULONG_PTR)PointerPte & (PAGE_SIZE - 1) /
sizeof(MMPTE)] = TempPte;
/* Initialize the PFN */ /* Initialize the PFN */
MiInitializePfnForOtherProcess(PageFrameNumber, MiInitializePfnForOtherProcess(PageFrameNumber,
PointerPte, PointerPde,
MmSystemPageDirectory[(PointerPte - (PMMPTE)PDE_BASE) / PDE_COUNT]); MmSystemPageDirectory[(PointerPde - MiAddressToPde(NULL)) / PDE_COUNT]);
/* Write the actual PTE now */ /* Write the actual PDE now */
MI_WRITE_VALID_PTE(PointerPte++, TempPte); MI_WRITE_VALID_PTE(PointerPde, TempPde);
#endif #endif
// //
// Move on to the next expansion address // Move on to the next expansion address
// //
PointerPde++;
BaseVa = (PVOID)((ULONG_PTR)BaseVa + PAGE_SIZE); BaseVa = (PVOID)((ULONG_PTR)BaseVa + PAGE_SIZE);
} while (--i > 0); i--;
} while (i > 0);
// //
// Release the PFN database lock // Release the PFN database lock
@ -510,11 +514,12 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
// //
// These pages are now available, clear their availablity bits // These pages are now available, clear their availablity bits
// //
RtlClearBits(MmPagedPoolInfo.PagedPoolAllocationMap, EndAllocation = (MmPagedPoolInfo.NextPdeForPagedPoolExpansion -
(MmPagedPoolInfo.NextPdeForPagedPoolExpansion -
MiAddressToPte(MmPagedPoolInfo.FirstPteForPagedPool)) * MiAddressToPte(MmPagedPoolInfo.FirstPteForPagedPool)) *
1024, PTE_COUNT;
SizeInPages * 1024); RtlClearBits(MmPagedPoolInfo.PagedPoolAllocationMap,
EndAllocation,
SizeInPages * PTE_COUNT);
// //
// Update the next expansion location // Update the next expansion location
@ -553,7 +558,8 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
// Update the end bitmap so we know the bounds of this allocation when // Update the end bitmap so we know the bounds of this allocation when
// the time comes to free it // the time comes to free it
// //
RtlSetBit(MmPagedPoolInfo.EndOfPagedPoolBitmap, i + SizeInPages - 1); EndAllocation = i + SizeInPages - 1;
RtlSetBit(MmPagedPoolInfo.EndOfPagedPoolBitmap, EndAllocation);
// //
// Now we can release the lock (it mainly protects the bitmap) // Now we can release the lock (it mainly protects the bitmap)
@ -583,9 +589,8 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
// //
// Write the demand zero PTE and keep going // Write the demand zero PTE and keep going
// //
ASSERT(PointerPte->u.Hard.Valid == 0); MI_WRITE_INVALID_PTE(PointerPte, TempPte);
*PointerPte++ = TempPte; } while (++PointerPte < StartPte);
} while (PointerPte < StartPte);
// //
// Return the allocation address to the caller // Return the allocation address to the caller