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Add simple GDB stub.

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Fix reported kernel address returned to reactos.c
Make MachVtbl fully formed for all subarch
Add simple gdb stub at this layer, wired to exception handlers
Simplify and unkludge trap handlers
Adapt trap frame to gdb style
Add proper swapping to image.c
Adapt other code for the more general trap handler now available in ppcmmu.

svn path=/trunk/; revision=29588
This commit is contained in:
Art Yerkes 2007-10-14 23:09:12 +00:00
parent 3016e207ca
commit 4039f862ec
16 changed files with 868 additions and 283 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
reactos/ReactOS-ppc.rbuild
View file

@ -9,6 +9,7 @@
<xi:include href="ReactOS-generic.rbuild" />
<property name="MKHIVE_OPTIONS" value="-be" />
<property name="OFWLDR_LINKFORMAT" value="-L$(INTERMEDIATE)/lib/ppcmmu -lppcmmu_code -nostdlib -nostartfiles -lgcc -Wl,-e,__start -Wl,-Ttext,0xe00000 -N"/>
<property name="NTOSKRNL_SHARED" value="-Wl,--file-alignment,0x1000 -Wl,--section-alignment,0x1000 -nostartfiles"/>

4
reactos/boot/freeldr/freeldr/arch/powerpc/loader.c
View file

@ -96,11 +96,13 @@ LdrPEGetExportByName(PVOID BaseAddress,
BaseAddress = (PVOID)((ULONG_PTR)BaseAddress - KSEG0_BASE + (ULONG)KernelMemory);
}
DbgPrint("Exports: RtlImageDirectoryEntryToData\n");
ExportDir = (PIMAGE_EXPORT_DIRECTORY)
RtlImageDirectoryEntryToData(BaseAddress,
TRUE,
IMAGE_DIRECTORY_ENTRY_EXPORT,
&ExportDirSize);
DbgPrint("RtlImageDirectoryEntryToData done\n");
if (!ExportDir)
{
DbgPrint("LdrPEGetExportByName(): no export directory!\n");
@ -324,11 +326,13 @@ LdrPEFixupImports(IN PVOID DllBase,
printf("Fixing up %x (%s)\n", DllBase, DllName);
/* Process each import module */
DbgPrint("FixupImports: RtlImageDirectoryEntryToData\n");
ImportModuleDirectory = (PIMAGE_IMPORT_DESCRIPTOR)
RtlImageDirectoryEntryToData(DllBase,
TRUE,
IMAGE_DIRECTORY_ENTRY_IMPORT,
&Size);
DbgPrint("RtlImageDirectoryEntryToData done\n");
while (ImportModuleDirectory && ImportModuleDirectory->Name)
{
/* Check to make sure that import lib is kernel */

58
reactos/boot/freeldr/freeldr/arch/powerpc/mach.c
View file

@ -287,6 +287,20 @@ VOID PpcVideoPrepareForReactOS(BOOLEAN Setup) {
}
}
int mmu_initialized = 0;
int mem_range_end;
VOID PpcInitializeMmu(int max_mem)
{
if(!mmu_initialized)
{
MmuInit();
MmuDbgInit(0, 0x800003f8);
MmuSetMemorySize(mem_range_end > max_mem ? mem_range_end : max_mem);
//MmuDbgEnter(0x20);
mmu_initialized = 1;
}
}
/*
* Get memory the proper openfirmware way
*/
@ -321,6 +335,14 @@ ULONG PpcGetMemoryMap( PBIOS_MEMORY_MAP BiosMemoryMap,
i,
(int)BiosMemoryMap[slots].BaseAddress,
(int)BiosMemoryMap[slots].Length);
// Track end of ram
if (BiosMemoryMap[slots].BaseAddress + BiosMemoryMap[slots].Length >
mem_range_end)
{
mem_range_end =
BiosMemoryMap[slots].BaseAddress + BiosMemoryMap[slots].Length;
}
/* Hack for pearpc */
if( kernel_mem ) {
@ -378,6 +400,8 @@ BOOLEAN PpcDiskGetSystemVolume( char *SystemPath,
RemainingPath[0] = 0;
}
*Device = 0;
// Hack to be a bit easier on ram
CacheSizeLimit = 64 * 1024;
return MachDiskGetBootVolume(DriveNumber, StartSector, SectorCount, FsType);
}
@ -492,28 +516,11 @@ BOOLEAN PpcDiskNormalizeSystemPath(char *SystemPath, unsigned Size) {
extern int _bss;
typedef unsigned int uint32_t;
void PpcOfwInit()
void PpcDefaultMachVtbl()
{
chosen_package = ofw_finddevice( "/chosen" );
ofw_getprop(chosen_package, "bootargs",
CmdLine, sizeof(CmdLine));
ofw_getprop( chosen_package, "stdin",
(char *)&stdin_handle, sizeof(stdin_handle) );
ofw_getprop( chosen_package, "stdout",
(char *)&stdout_handle, sizeof(stdout_handle) );
ofw_getprop( chosen_package, "mmu",
(char *)&mmu_handle, sizeof(mmu_handle) );
MachVtbl.ConsPutChar = PpcOfwPutChar;
MachVtbl.ConsKbHit = PpcConsKbHit;
MachVtbl.ConsGetCh = PpcConsGetCh;
printf( "chosen_package %x, stdin_handle is %x\n",
chosen_package, stdin_handle );
printf("virt2phys (0xe00000,D) -> %x\n", PpcVirt2phys(0xe00000,0));
printf("virt2phys (0xe01000,D) -> %x\n", PpcVirt2phys(0xe01000,0));
MachVtbl.VideoClearScreen = PpcVideoClearScreen;
MachVtbl.VideoSetDisplayMode = PpcVideoSetDisplayMode;
MachVtbl.VideoGetDisplaySize = PpcVideoGetDisplaySize;
@ -545,6 +552,20 @@ void PpcOfwInit()
MachVtbl.RTCGetCurrentDateTime = PpcRTCGetCurrentDateTime;
MachVtbl.HwDetect = PpcHwDetect;
}
void PpcOfwInit()
{
chosen_package = ofw_finddevice( "/chosen" );
ofw_getprop(chosen_package, "bootargs",
CmdLine, sizeof(CmdLine));
ofw_getprop( chosen_package, "stdin",
(char *)&stdin_handle, sizeof(stdin_handle) );
ofw_getprop( chosen_package, "stdout",
(char *)&stdout_handle, sizeof(stdout_handle) );
ofw_getprop( chosen_package, "mmu",
(char *)&mmu_handle, sizeof(mmu_handle) );
// Allow forcing prep for broken OFW
if(!strncmp(CmdLine, "bootprep", 8))
@ -561,6 +582,7 @@ void PpcOfwInit()
void PpcInit( of_proxy the_ofproxy ) {
ofproxy = the_ofproxy;
PpcDefaultMachVtbl();
if(ofproxy) PpcOfwInit();
else PpcPrepInit();
}

19
reactos/boot/freeldr/freeldr/arch/powerpc/mboot.c
View file

@ -90,6 +90,8 @@ NTAPI
LdrPEFixupImports(IN PVOID DllBase,
IN PCHAR DllName);
VOID PpcInitializeMmu(int max);
/* FUNCTIONS *****************************************************************/
/*++
@ -111,10 +113,10 @@ LdrPEFixupImports(IN PVOID DllBase,
typedef void (*KernelEntryFn)( void * );
int MmuPageMiss(int inst, ppc_trap_frame_t *trap)
int MmuPageMiss(int trapCode, ppc_trap_frame_t *trap)
{
int i;
printf("inst %x\n", inst);
printf("TRAP %x\n", trapCode);
for( i = 0; i < 40; i++ )
printf("r[%d] %x\n", i, trap->gpr[i]);
printf("HALT!\n");
@ -143,6 +145,8 @@ FrLdrStartup(ULONG Magic)
(PCHAR)reactos_modules[i].String);
}
PpcInitializeMmu(0);
/* We'll use vsid 1 for freeldr (expendable) */
MmuAllocVsid(1, 0xff);
MmuSetVsid(0, 8, 1);
@ -150,7 +154,8 @@ FrLdrStartup(ULONG Magic)
MmuAllocVsid(0, 0xff00);
MmuSetVsid(8, 16, 0);
MmuSetPageCallback(MmuPageMiss);
MmuSetTrapHandler(3, MmuPageMiss);
MmuSetTrapHandler(4, MmuPageMiss);
info = MmAllocateMemory((KernelMemorySize >> PAGE_SHIFT) * sizeof(*info));
@ -420,6 +425,10 @@ FrLdrMapModule(FILE *KernelImage, PCHAR ImageName, PCHAR MemLoadAddr, ULONG Kern
printf("No peheader section encountered :-(\n");
return 0;
}
else
{
printf("DOS SIG: %s\n", (PCHAR)MemLoadAddr);
}
/* Save the Image Base */
NtHeader->OptionalHeader.ImageBase = SWAPD(KernelAddr);
@ -673,7 +682,7 @@ FrLdrLoadModule(FILE *ModuleImage,
*ModuleSize = LocalModuleSize;
}
return(ModuleData->ModStart);
return NextModuleBase;
}
PVOID
@ -685,7 +694,7 @@ FrLdrMapImage(IN FILE *Image, IN PCHAR ShortName, IN ULONG ImageType)
if (ImageType == 1)
{
if(FrLdrMapKernel(Image))
return (PVOID)KernelBase;
return (PVOID)KernelMemory;
else
return NULL;
}

11
reactos/boot/freeldr/freeldr/arch/powerpc/prep.c
View file

@ -66,7 +66,7 @@ void PpcPrepVideoPrepareForReactOS(BOOLEAN setup)
pci_setup(&pci1_desc);
}
int mmu_initialized = 0;
VOID PpcInitializeMmu(int max);
ULONG PpcPrepGetMemoryMap( PBIOS_MEMORY_MAP BiosMemoryMap,
ULONG MaxMemoryMapSize )
@ -75,12 +75,7 @@ ULONG PpcPrepGetMemoryMap( PBIOS_MEMORY_MAP BiosMemoryMap,
BiosMemoryMap[0].Type = 1;
BiosMemoryMap[0].BaseAddress = 0xe80000;
BiosMemoryMap[0].Length = (64 * 1024 * 1024) - BiosMemoryMap[0].BaseAddress;
if(!mmu_initialized)
{
MmuInit();
mmu_initialized = 1;
}
MmuSetMemorySize(BiosMemoryMap[0].Length + BiosMemoryMap[0].BaseAddress);
PpcInitializeMmu(BiosMemoryMap[0].BaseAddress + BiosMemoryMap[0].Length);
return 1;
}
@ -93,7 +88,7 @@ void PpcPrepInit()
ide_setup( &ide1_desc );
MachVtbl.DiskReadLogicalSectors = PpcPrepDiskReadLogicalSectors;
MachVtbl.ConsKbHit = PpcPrepConsKbHit;
MachVtbl.ConsGetCh = PpcPrepConsGetCh;

80
reactos/include/reactos/libs/ppcmmu/mmu.h
View file

@ -1,6 +1,8 @@
#ifndef PPCMMU_H
#define PPCMMU_H
#include <string.h>
/* PPC MMU object --
* Always called from kernel mode, maps the first 16 megabytes and uses 16
* bytes per page between 0x30000 and 16 megs. Maximum memory size is 3 gig.
@ -13,25 +15,37 @@
* 0x30000 -- Full map
*
* Actions:
* 00 -- Initialize
*
* 1** -- MMU Related
*
* 100 -- Initialize
* -- No arguments
* 01 -- Map page
* 101 -- Map page
* r4 -- virtual address
* r5 -- ppc_map_info_t
* 02 -- Erase page
* 102 -- Erase page
* r4 -- virtual address
* 03 -- Set segment VSID
* 103 -- Set segment VSID
* r4 -- Start seg
* r5 -- End seg
* r6 -- Vsid
* 04 -- Set page miss callback
* r4 -- Callback address (VA)
* 05 -- Query page
* 104 -- Set trap callback
* r4 -- Trap number
* r5 -- Callback address (VA)
* 105 -- Query page
* r4 -- Page addr
* r5 -- Address of info struct
* 06 -- Unit Test
* 07 -- Turn on paging
* 08 -- Unmap process
* 106 -- Unit Test
* 107 -- Turn on paging
* 108 -- Unmap process
*
* 2** -- Debug Stub and Interrupt Vectoring
*
* 200 -- GDB Initialize
* r4 -- Device type
* r4 -- Serial port addr
* 201 -- GDB Enter
* r4 -- Signal number
*/
#define MMUCODE 0x10000
@ -91,10 +105,11 @@ typedef struct _ppc_map_info_t {
typedef struct _ppc_trap_frame_t {
unsigned long gpr[32];
unsigned long lr, cr, ctr, srr0, srr1, dsisr, dar, xer;
unsigned long long fpr[32];
unsigned long srr0, srr1, cr, lr, ctr, xer, mq, dsisr, dar;
} ppc_trap_frame_t;
typedef int (*MmuPageCallback)(int inst, ppc_trap_frame_t *trap);
typedef int (*MmuTrapHandler)(int trapid, ppc_trap_frame_t *trap);
#include "mmuutil.h"
@ -160,69 +175,80 @@ static inline int PPCMMU(int action, void *arg1, void *arg2, void *arg3)
*/
static inline void _MmuInit(void *_start, void *_end)
{
int target = MMUCODE;
int target = MMUCODE, copy;
int *start = (int *)_start;
while(start < (int *)_end)
{
SetPhys(target, *start++);
memcpy(&copy, start++, sizeof(int));
SetPhys(target, copy);
target += sizeof(int);
}
PPCMMU(0, 0, 0, 0);
PPCMMU(0x100, 0, 0, 0);
}
static inline void MmuMapPage(ppc_map_info_t *info, int count)
{
PPCMMU(1, info, (void *)count, 0);
PPCMMU(0x101, info, (void *)count, 0);
}
static inline void MmuUnmapPage(ppc_map_info_t *info, int count)
{
PPCMMU(2, info, (void *)count, 0);
PPCMMU(0x102, info, (void *)count, 0);
}
static inline void MmuSetVsid(int start, int end, int vsid)
{
PPCMMU(3, (void *)start, (void *)end, (void *)vsid);
PPCMMU(0x103, (void *)start, (void *)end, (void *)vsid);
}
static inline MmuPageCallback MmuSetPageCallback(MmuPageCallback cb)
static inline MmuTrapHandler MmuSetTrapHandler(int trap, MmuTrapHandler cb)
{
return (MmuPageCallback)PPCMMU(4, (void *)cb, 0, 0);
return (MmuTrapHandler)PPCMMU(0x104, (void *)trap, (void *)cb, 0);
}
static inline void MmuInqPage(ppc_map_info_t *info, int count)
{
PPCMMU(5, info, (void *)count, 0);
PPCMMU(0x105, info, (void *)count, 0);
}
static inline int MmuUnitTest()
{
return PPCMMU(6, 0, 0, 0);
return PPCMMU(0x106, 0, 0, 0);
}
static inline int MmuTurnOn(void *fun, void *arg)
{
return PPCMMU(7, fun, arg, 0);
return PPCMMU(0x107, fun, arg, 0);
}
static inline void MmuSetMemorySize(paddr_t size)
{
PPCMMU(8, (void *)size, 0, 0);
PPCMMU(0x108, (void *)size, 0, 0);
}
static inline paddr_t MmuGetFirstPage()
{
return (paddr_t)PPCMMU(9, 0, 0, 0);
return (paddr_t)PPCMMU(0x109, 0, 0, 0);
}
static inline void *MmuAllocVsid(int vsid, int mask)
{
return (void *)PPCMMU(10, (void *)vsid, (void *)mask, 0);
return (void *)PPCMMU(0x10a, (void *)vsid, (void *)mask, 0);
}
static inline void MmuRevokeVsid(int vsid, int mask)
{
PPCMMU(11, (void *)vsid, (void *)mask, 0);
PPCMMU(0x10b, (void *)vsid, (void *)mask, 0);
}
static inline void MmuDbgInit(int deviceType, int devicePort)
{
PPCMMU(0x200, (void *)deviceType, (void *)devicePort, 0);
}
static inline void MmuDbgEnter(int signal)
{
PPCMMU(0x201, (void *)signal, 0, 0);
}
#endif/*PPCMMU_H*/

146
reactos/lib/ppcmmu/devint.s Normal file
View file

@ -0,0 +1,146 @@
/* PowerPC Trap Handler first Half */
.text
.globl mmumain
.globl _mmumain
.globl oldstack
mmumain:
lis 7,oldstack@ha
addi 7,7,oldstack@l
mflr 0
stw 1,0(7)
lis 1,2
subi 1,1,16
stw 0,0(1)
bl _mmumain
lis 7,oldstack@ha
addi 7,7,oldstack@l
lwz 0,0(1)
lwz 1,0(7)
mtlr 0
blr
oldstack:
.long 0
.globl trap_start
.globl trap_end
trap_start:
mtsprg1 1
lis 1,2
subi 1,1,432
stw 0,0(1)
mfsprg1 0
stw 0,4(1)
stw 2,8(1)
stw 3,12(1)
stw 4,16(1)
stw 5,20(1)
stw 6,24(1)
stw 7,28(1)
stw 8,32(1)
stw 9,36(1)
stw 10,40(1)
stw 11,44(1)
stw 12,48(1)
stw 13,52(1)
stw 14,56(1)
stw 15,60(1)
stw 16,64(1)
stw 17,68(1)
stw 18,72(1)
stw 19,76(1)
stw 20,80(1)
stw 21,84(1)
stw 22,88(1)
stw 23,92(1)
stw 24,96(1)
stw 25,100(1)
stw 26,104(1)
stw 27,108(1)
stw 28,112(1)
stw 29,116(1)
stw 30,120(1)
stw 31,124(1)
mfsrr0 0
stw 0,384(1)
mfsrr1 0
stw 0,388(1)
mfcr 0
stw 0,392(1)
mflr 0
stw 0,396(1)
mfctr 0
stw 0,400(1)
mfxer 0
stw 0,404(1)
xor 0,0,0
stw 0,408(1)
mfdsisr 0
stw 0,412(1)
mfdar 0
stw 0,416(1)
bl 1f
1: mflr 5
mr 4,1
rlwinm 3,5,24,0xff
lwz 5,36(5)
mtctr 5
lis 5,trap_finish_start@ha
addi 5,5,trap_finish_start@l
mtlr 5
bctr
trap_end:
.space 4
.globl trap_finish_start
trap_finish_start:
lwz 2,8(1)
lwz 3,12(1)
lwz 4,16(1)
lwz 5,20(1)
lwz 6,24(1)
lwz 7,28(1)
lwz 8,32(1)
lwz 9,36(1)
lwz 10,40(1)
lwz 11,44(1)
lwz 12,48(1)
lwz 13,52(1)
lwz 14,56(1)
lwz 15,60(1)
lwz 16,64(1)
lwz 17,68(1)
lwz 18,72(1)
lwz 19,76(1)
lwz 20,80(1)
lwz 21,84(1)
lwz 22,88(1)
lwz 23,92(1)
lwz 24,96(1)
lwz 25,100(1)
lwz 26,104(1)
lwz 27,108(1)
lwz 28,112(1)
lwz 29,116(1)
lwz 30,120(1)
lwz 31,124(1)
lwz 0,384(1)
mtsrr0 0
lwz 0,388(1)
mtsrr1 0
lwz 0,392(1)
mtcr 0
lwz 0,396(1)
mtlr 0
lwz 0,400(1)
mtctr 0
lwz 0,404(1)
mtxer 0
lwz 0,412(1)
mtdsisr 0
lwz 0,416(1)
mtdar 0
lwz 0,0(1)
mtsprg1 0
lwz 0,0(1)
mfsprg1 1
rfi

440
reactos/lib/ppcmmu/gdblib.c Normal file
View file

@ -0,0 +1,440 @@
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
/****************************************************************************
* Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
*
* Module name: remcom.c $
* Revision: 1.34 $
* Date: 91/03/09 12:29:49 $
* Contributor: Lake Stevens Instrument Division$
*
* Description: low level support for gdb debugger. $
*
* Considerations: only works on target hardware $
*
* Written by: Glenn Engel $
* ModuleState: Experimental $
*
* NOTES: See Below $
*
* Modified for 386 by Jim Kingdon, Cygnus Support.
* Modified for ReactOS by Casper S. Hornstrup <chorns@users.sourceforge.net>
*
* To enable debugger support, two things need to happen. One, setting
* up a routine so that it is in the exception path, is necessary in order
* to allow any breakpoints or error conditions to be properly intercepted
* and reported to gdb.
* Two, a breakpoint needs to be generated to begin communication.
ER*
* Because gdb will sometimes write to the stack area to execute function
* calls, this program cannot rely on using the supervisor stack so it
* uses it's own stack area.
*
*************
*
* The following gdb commands are supported:
*
* command function Return value
*
* g return the value of the CPU Registers hex data or ENN
* G set the value of the CPU Registers OK or ENN
*
* mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
* MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
*
* c Resume at current address SNN ( signal NN)
* cAA..AA Continue at address AA..AA SNN
*
* s Step one instruction SNN
* sAA..AA Step one instruction from AA..AA SNN
*
* k kill
*
* ? What was the last sigval ? SNN (signal NN)
*
* All commands and responses are sent with a packet which includes a
* Checksum. A packet consists of
*
* $<packet info>#<Checksum>.
*
* where
* <packet info> :: <characters representing the command or response>
* <Checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
*
* When a packet is received, it is first acknowledged with either '+' or '-'.
* '+' indicates a successful transfer. '-' indicates a failed transfer.
*
* Example:
*
* Host: Reply:
* $m0,10#2a +$00010203040506070809101112131415#42
*
****************************************************************************/
#include "ppcmmu/mmu.h"
typedef struct _BREAKPOINT {
int OldCode;
int *Address;
} BREAKPOINT, *PBREAKPOINT;
BREAKPOINT BreakPoints[64];
char DataOutBuffer[1024];
volatile int DataOutAddr, DataOutCsum;
char DataInBuffer[128];
volatile int DataInAddr, ParseState = 0, ComputedCsum, ActualCsum;
volatile int PacketSent = 0, SendSignal = 0;
volatile int Continue = 0, Signal = 0;
volatile ppc_trap_frame_t RegisterSaves, *RegisterSaveArea = &RegisterSaves;
char *hex = "0123456789abcdef";
#define RCV 0
#define THR 0
#define BAUDLOW 0
#define BAUDHIGH 1
#define IER 1
#define FCR 2
#define ISR 2
#define LCR 3
#define MCR 4
#define LSR 5
#define MSR 6
#define SPR 7
extern void send(char *serport, char c);
extern char recv(char *serport);
extern void setup(char *serport, int baud);
char *serport = (char *)0x800003f8;
int isxdigit(int ch)
{
return
(ch >= 'A' && ch <= 'F') ||
(ch >= 'a' && ch <= 'f') ||
(ch >= '0' && ch <= '9');
}
void sync() {
__asm__("eieio\n\t"
"sync");
}
void send(char *serport, char c) {
/* Wait for Clear to Send */
while( !(serport[LSR] & 0x20) ) sync();
serport[THR] = c;
sync();
}
int rdy(char *serport)
{
sync();
return (serport[LSR] & 0x20);
}
char recv(char *serport) {
char c;
while( !(serport[LSR] & 1) ) sync();
c = serport[RCV];
sync();
return c;
}
void setup(char *serport, int baud) {
int x = 115200 / baud;
serport[LCR] = 128;
sync();
serport[BAUDLOW] = x & 255;
sync();
serport[BAUDHIGH] = x >> 8;
sync();
serport[LCR] = 3;
sync();
serport[IER] = 1;
sync();
}
void SerialSetUp(int deviceType, void *deviceAddr, int baud)
{
int i;
serport = deviceAddr;
setup(serport, baud);
}
extern void SerialInterrupt();
void Wait()
{
while(!Continue) if (rdy(serport)) SerialInterrupt();
}
void SerialWrite(int ch)
{
send(serport, ch);
}
int SerialRead()
{
return recv(serport);
}
int hex2int(int ch)
{
if (ch >= 'a' && ch <= 'f') return ch + 10 - 'a';
else if (ch >= 'A' && ch <= 'F') return ch + 10 - 'A';
else return ch - '0';
}
int PacketReadHexNumber(int dig)
{
int i;
int result = 0;
for (i = 0; i < dig && isxdigit(DataInBuffer[DataInAddr]); i++)
{
result <<= 4;
result |= hex2int(DataInBuffer[DataInAddr++]);
}
return result;
}
void PacketWriteChar(int ch)
{
DataOutCsum += ch;
DataOutBuffer[DataOutAddr++] = ch;
}
int PacketWriteHexNumber(int hnum, int dig)
{
int i;
hnum <<= (8 - dig) * 4;
for (i = 0; i < dig; i++)
{
PacketWriteChar(hex[(hnum >> 28) & 15]);
hnum <<= 4;
}
return i;
}
void PacketStart()
{
DataOutCsum = 0;
DataOutAddr = 0;
}
void PacketFinish()
{
int i, ch;
PacketSent = 0;
do {
SerialWrite('$');
for (i = 0; i < DataOutAddr; i++)
{
SerialWrite(DataOutBuffer[i]);
}
SerialWrite('#');
SerialWrite(hex[(DataOutCsum >> 4) & 15]);
SerialWrite(hex[DataOutCsum & 15]);
while(!rdy(serport));
if (SerialRead() == '+') break;
} while(PacketSent != 1);
}
void PacketWriteString(char *str)
{
while(*str) PacketWriteChar(*str++);
}
void PacketOk()
{
PacketStart();
PacketWriteString("OK");
PacketFinish();
}
void PacketEmpty()
{
PacketStart();
PacketFinish();
}
void PacketWriteSignal(int code)
{
PacketStart();
PacketWriteChar('S');
PacketWriteHexNumber(code, 2);
PacketFinish();
}
void PacketWriteError(int code)
{
PacketStart();
PacketWriteChar('E');
PacketWriteHexNumber(code, 2);
PacketFinish();
}
void GotPacket()
{
int i, memaddr, memsize;
switch (DataInBuffer[DataInAddr++])
{
case 'g':
PacketStart();
for (i = 0; i < 108; i++)
{
PacketWriteHexNumber(((int *)RegisterSaveArea)[i], 8);
}
PacketFinish();
break;
case 'G':
for (i = 0; i < 108; i++)
{
((int *)RegisterSaveArea)[i] = PacketReadHexNumber(8);
}
PacketOk();
break;
case 'm':
memaddr = PacketReadHexNumber(8);
DataInAddr++;
memsize = PacketReadHexNumber(8);
PacketStart();
while(memsize-- > 0)
{
PacketWriteHexNumber(*((char *)memaddr++), 2);
}
PacketFinish();
break;
case 'M':
memaddr = PacketReadHexNumber(8);
DataInAddr++;
memsize = PacketReadHexNumber(8);
DataInAddr++;
while(memsize-- > 0)
{
*((char *)memaddr++) = PacketReadHexNumber(2);
}
PacketOk();
break;
case '?':
PacketWriteSignal(Signal);
break;
case 'c':
PacketOk();
Continue = 1;
break;
case 's':
RegisterSaveArea->srr1 |= 16;
PacketOk();
Continue = 1;
break;
case 'q':
switch (DataInBuffer[1])
{
case 'S': /*upported => nothing*/
PacketEmpty();
break;
case 'O': /*ffsets*/
PacketEmpty();
break;
}
break;
default:
PacketEmpty();
break;
}
}
void SerialInterrupt()
{
int ch = SerialRead();
if (ch == '+')
{
PacketSent = 1;
}
else if (ch == '-')
{
PacketSent = -1;
}
else if (ch == '$')
{
DataInAddr = 0;
ParseState = 0;
ComputedCsum = 0;
ActualCsum = 0;
}
else if (ch == '#' && ParseState == 0)
{
ParseState = 2;
}
else if (ParseState == 0)
{
ComputedCsum += ch;
DataInBuffer[DataInAddr++] = ch;
}
else if (ParseState == 2)
{
ActualCsum = ch;
ParseState++;
}
else if (ParseState == 3)
{
ActualCsum = hex2int(ch) | (hex2int(ActualCsum) << 4);
ComputedCsum &= 255;
ParseState = -1;
if (ComputedCsum == ActualCsum)
{
ComputedCsum = 0;
DataInBuffer[DataInAddr] = 0;
DataInAddr = 0;
Continue = 0;
SerialWrite('+');
GotPacket();
}
else
SerialWrite('-');
}
}
void TakeException(int n, int *tf)
{
Signal = n;
RegisterSaveArea = tf;
if (SendSignal)
PacketWriteSignal(Signal);
SendSignal = 0;
Continue = 0;
Wait();
}
/* EOF */

297
reactos/lib/ppcmmu/mmuobject.c
View file

@ -40,7 +40,7 @@ Actions:
11 revoke vsid
*/
MmuPageCallback callback;
MmuTrapHandler callback[0x30];
typedef struct _MmuFreePage {
int page;
struct _MmuFreePage *next;
@ -59,7 +59,7 @@ typedef struct _MmuVsidInfo {
MmuFreePage *FreeList;
// Pages are allocated one by one until NextPage == RamSize >> PPC_PAGE_SHIFT
// Then we take only from the free list
int Clock = 0, TreeAlloc = 0;
int Clock = 0, TreeAlloc = 0, GdbAttach = 0;
paddr_t RamSize, FirstUsablePage, NextPage;
MmuVsidTree *NextTreePage = 0;
MmuFreeTree *FreeTree;
@ -67,146 +67,8 @@ MmuVsidInfo *Segs[16], *VsidHead = 0;
extern void fmtout(const char *fmt, ...);
int ptegreload(ppc_trap_frame_t *frame, vaddr_t addr);
__asm__(".text\n\t"
".globl mmumain\n\t"
".globl _mmumain\n\t"
".globl oldstack\n\t"
"mmumain:\n\t"
"lis 7,oldstack@ha\n\t"
"addi 7,7,oldstack@l\n\t"
"mflr 0\n\t"
"stw 1,0(7)\n\t"
"lis 1,2\n\t"
"subi 1,1,16\n\t"
"stw 0,0(1)\n\t"
"bl _mmumain\n\t"
"lis 7,oldstack@ha\n\t"
"addi 7,7,oldstack@l\n\t"
"lwz 0,0(1)\n\t"
"lwz 1,0(7)\n\t"
"mtlr 0\n\t"
"blr\n"
"oldstack:\n\t"
".long 0\n\t");
__asm__(".text\n\t"
".globl data_miss_finish_start\n"
"data_miss_finish_start:\n\t"
"lwz 2,8(1)\n\t"
"lwz 3,12(1)\n\t"
"lwz 4,16(1)\n\t"
"lwz 5,20(1)\n\t"
"lwz 6,24(1)\n\t"
"lwz 7,28(1)\n\t"
"lwz 8,32(1)\n\t"
"lwz 9,36(1)\n\t"
"lwz 10,40(1)\n\t"
"lwz 11,44(1)\n\t"
"lwz 12,48(1)\n\t"
"lwz 13,52(1)\n\t"
"lwz 14,56(1)\n\t"
"lwz 15,60(1)\n\t"
"lwz 16,64(1)\n\t"
"lwz 17,68(1)\n\t"
"lwz 18,72(1)\n\t"
"lwz 19,76(1)\n\t"
"lwz 20,80(1)\n\t"
"lwz 21,84(1)\n\t"
"lwz 22,88(1)\n\t"
"lwz 23,92(1)\n\t"
"lwz 24,96(1)\n\t"
"lwz 25,100(1)\n\t"
"lwz 26,104(1)\n\t"
"lwz 27,108(1)\n\t"
"lwz 28,112(1)\n\t"
"lwz 29,116(1)\n\t"
"lwz 30,120(1)\n\t"
"lwz 31,124(1)\n\t"
"lwz 0,128(1)\n\t"
"mtlr 0\n\t"
"lwz 0,132(1)\n\t"
"mtcr 0\n\t"
"lwz 0,136(1)\n\t"
"mtctr 0\n\t"
"lwz 0,0(1)\n\t"
"mfsprg1 1\n\t"
"rfi\n\t");
/*
* Trap frame:
* r0 .. r32
* lr, ctr, srr0, srr1, dsisr
*/
__asm__(".text\n\t"
".globl data_miss_start\n\t"
".globl data_miss_end\n\t"
"data_miss_start:\n\t"
"mtsprg1 1\n\t"
"lis 1,2\n\t"
"subi 1,1,256\n\t"
"stw 0,0(1)\n\t"
"mfsprg1 0\n\t"
"stw 0,4(1)\n\t"
"stw 2,8(1)\n\t"
"stw 3,12(1)\n\t"
"stw 4,16(1)\n\t"
"stw 5,20(1)\n\t"
"stw 6,24(1)\n\t"
"stw 7,28(1)\n\t"
"stw 8,32(1)\n\t"
"stw 9,36(1)\n\t"
"stw 10,40(1)\n\t"
"stw 11,44(1)\n\t"
"stw 12,48(1)\n\t"
"stw 13,52(1)\n\t"
"stw 14,56(1)\n\t"
"stw 15,60(1)\n\t"
"stw 16,64(1)\n\t"
"stw 17,68(1)\n\t"
"stw 18,72(1)\n\t"
"stw 19,76(1)\n\t"
"stw 20,80(1)\n\t"
"stw 21,84(1)\n\t"
"stw 22,88(1)\n\t"
"stw 23,92(1)\n\t"
"stw 24,96(1)\n\t"
"stw 25,100(1)\n\t"
"stw 26,104(1)\n\t"
"stw 27,108(1)\n\t"
"stw 28,112(1)\n\t"
"stw 29,116(1)\n\t"
"stw 30,120(1)\n\t"
"stw 31,124(1)\n\t"
"mflr 0\n\t"
"stw 0,128(1)\n\t"
"mfcr 0\n\t"
"stw 0,132(1)\n\t"
"mfctr 0\n\t"
"stw 0,136(1)\n\t"
"mfsrr0 0\n\t"
"stw 0,140(1)\n\t"
"mfsrr1 0\n\t"
"stw 0,144(1)\n\t"
"mfdsisr 0\n\t"
"stw 0,148(1)\n\t"
"mfdar 0\n\t"
"stw 0,152(1)\n\t"
"mfxer 0\n\t"
"stw 0,156(1)\n\t"
"li 3,100\n\t"
"mr 4,1\n\t"
"lis 5,data_miss_finish_start@ha\n\t"
"addi 5,5,data_miss_finish_start@l\n\t"
"mtlr 5\n\t"
"lis 5,_mmumain@ha\n\t"
"addi 5,5,_mmumain@l\n\t"
"mtctr 5\n\t"
"bctr\n"
"data_miss_end:\n\t"
".space 4");
extern int data_miss_end, data_miss_start;
void SerialSetUp(int deviceType, void *deviceAddr, int baud);
void TakeException(int n, int *tf);
int _mmumain(int action, void *arg1, void *arg2, void *arg3)
{
@ -216,30 +78,62 @@ int _mmumain(int action, void *arg1, void *arg2, void *arg3)
switch(action)
{
case 0:
initme();
break;
case 1:
ret = mmuaddpage(arg1, (int)arg2);
break;
case 2:
mmudelpage(arg1, (int)arg2);
break;
/* Trap Handlers */
case 3:
mmusetvsid((int)arg1, (int)arg2, (int)arg3);
if(!ptegreload(trap_frame, trap_frame->dar))
{
__asm__("mfmsr 3\n\tori 3,3,0x30\n\tmtmsr 3\n\t");
if (!callback[action](action,arg1)) hang(action, arg1);
}
break;
case 4:
/* Miss callback = arg1 */
ret = (int)callback;
callback = arg1;
if(!ptegreload(trap_frame, trap_frame->srr0))
{
__asm__("mfmsr 3\n\tori 3,3,0x30\n\tmtmsr 3\n\t");
if (!callback[action](action,arg1)) hang(action, arg1);
}
break;
case 0:
case 2:
case 5:
case 6:
case 7:
case 8:
case 9:
case 0xa:
if (!callback[action](action,arg1)) hang(action, arg1);
break;
case 0x20:
// Single step
TakeException(action, arg1);
break;
/* MMU Functions */
case 0x100:
initme();
break;
case 0x101:
ret = mmuaddpage(arg1, (int)arg2);
break;
case 0x102:
mmudelpage(arg1, (int)arg2);
break;
case 0x103:
mmusetvsid((int)arg1, (int)arg2, (int)arg3);
break;
case 0x104:
ret = (int)callback[(int)arg1];
callback[(int)arg1] = (MmuTrapHandler)arg2;
break;
case 0x105:
mmugetpage(arg1, (int)arg2);
break;
case 6:
case 0x106:
ret = mmunitest();
break;
case 7:
case 0x107:
__asm__("mfmsr 3\n\t"
"ori 3,3,0x30\n\t"
"mtmsr 3\n\t"
@ -251,31 +145,25 @@ int _mmumain(int action, void *arg1, void *arg2, void *arg3)
: : "r" (HTABORG), "r" (arg2), "r" (fun));
/* BYE ! */
break;
case 8:
case 0x108:
mmusetramsize((paddr_t)arg1);
break;
case 9:
case 0x109:
return FirstUsablePage;
case 10:
case 0x10a:
mmuallocvsid((int)arg1, (int)arg2);
break;
case 11:
case 0x10b:
mmufreevsid((int)arg1, (int)arg2);
break;
case 100:
if(!ptegreload(trap_frame, trap_frame->dar))
{
__asm__("mfmsr 3\n\tori 3,3,0x30\n\tmtmsr 3\n\t");
callback(0,arg1);
}
break;
case 101:
if(!ptegreload(trap_frame, trap_frame->srr0))
{
__asm__("mfmsr 3\n\tori 3,3,0x30\n\tmtmsr 3\n\t");
callback(1,arg1);
}
break;
case 0x200:
SerialSetUp((int)arg1, arg2, 9600);
break;
case 0x201:
TakeException((int)arg1, (int *)arg2);
break;
default:
while(1);
}
@ -351,27 +239,66 @@ void mmusetramsize(paddr_t ramsize)
}
}
int ignore(int trapCode, ppc_trap_frame_t *trap)
{
return 1;
}
int hang(int trapCode, ppc_trap_frame_t *trap)
{
if (!GdbAttach)
{
GdbAttach = 1;
SerialSetUp(0, (void *)0x800003f8, 9600);
}
TakeException(trapCode, (int *)trap);
return 1;
}
int fpenable(int trapCode, ppc_trap_frame_t *trap)
{
/* Turn on FP */
trap->srr0 |= 8192;
return 1;
}
extern int trap_start[], trap_end[];
void copy_trap_handler(int trap)
{
int i;
paddr_t targetArea = trap * 0x100;
/* Set target addr */
trap_end[0] = (int)_mmumain;
for (i = 0; i <= trap_end - trap_start; i++)
{
SetPhys(targetArea + (i * sizeof(int)), trap_start[i]);
}
}
void initme()
{
int i;
int *target, *start;
for(i = 0; i < HTABSIZ / sizeof(int); i++)
{
((int *)HTABORG)[i] = 0;
}
for(target = (int *)0x300, start = &data_miss_start; start < &data_miss_end; start++, target++)
/* Default to hang on unknown exception */
for(i = 0; i < 30; i++)
{
SetPhys((paddr_t)target, *start);
}
(&data_miss_start)[50]++;
for(target = (int *)0x400, start = &data_miss_start; start < &data_miss_end; start++, target++)
{
SetPhys((paddr_t)target, *start);
callback[i] = hang;
if (i != 1) /* Preserve reset handler */
copy_trap_handler(i);
}
/* Floating point exception */
callback[8] = fpenable;
/* Ignore decrementer and EE */
callback[9] = ignore;
}
ppc_map_t *allocpage()

1
reactos/lib/ppcmmu/mmuobject.h
View file

@ -1,7 +1,6 @@
#ifndef _LIBMMU_MMUOBJECT_H
#define _LIBMMU_MMUOBJECT_H
MmuPageCallback callback;
void initme();
void mmusetramsize(paddr_t size);
int mmuaddpage(ppc_map_info_t *info, int count);

11
reactos/lib/ppcmmu/ppcmmu.mak
View file

@ -5,17 +5,24 @@ AR=powerpc-unknown-elf-ar
OBJCOPY=powerpc-unknown-elf-objcopy
LDSCRIPT=-Wl,-T,$S/ldscript
PPCMMU_TARGETS=$O/libppcmmu_code.a
MMUOBJECT_OBJS=$O/devint.o $O/mmuobject.o $O/mmuutil_object.o $O/mmutest.o $O/gdblib.o
$O/mmuutil_object.o: $S/mmuutil.c | $O
$(CC) -Iinclude/reactos/libs -g -c -o $@ $S/mmuutil.c
$O/libppcmmu_code.a: $O/mmuobject.o $O/mmuutil_object.o $O/mmutest.o | $O
$(CC) -Wl,-N -nostartfiles -nostdlib -o $O/mmuobject -Ttext=0x10000 $(LDSCRIPT) -Wl,-u,mmumain -Wl,-u,data_miss_start -Wl,-u,data_miss_end $O/mmuobject.o $O/mmuutil_object.o $O/mmutest.o
$O/libppcmmu_code.a: $(MMUOBJECT_OBJS) | $O
$(CC) -Wl,-N -nostartfiles -nostdlib -o $O/mmuobject -Ttext=0x10000 $(LDSCRIPT) -Wl,-u,mmumain -Wl,-u,data_miss_start -Wl,-u,data_miss_end $(MMUOBJECT_OBJS)
$(OBJCOPY) -O binary $O/mmuobject mmucode
$(OBJCOPY) -I binary -O elf32-powerpc -B powerpc:common mmucode $O/mmucode.o
mkdir -p `dirname $@`
$(AR) cr $@ $O/mmucode.o
$O/gdblib.o: $S/gdblib.c | $O
$(CC) -Iinclude/reactos -Iinclude/reactos/libs -g -c -o $@ $S/gdblib.c
$O/devint.o: $S/devint.s | $O
$(CC) -Iinclude/reactos -Iinclude/reactos/libs -g -c -o $@ $S/devint.s
$O/mmuobject.o: $S/mmuobject.c $S/mmuobject.h | $O
$(CC) -Iinclude/reactos -Iinclude/reactos/libs -g -c -o $@ $S/mmuobject.c

62
reactos/lib/rtl/image.c
View file

@ -37,16 +37,16 @@ RtlImageNtHeader (IN PVOID BaseAddress)
PIMAGE_NT_HEADERS NtHeader;
PIMAGE_DOS_HEADER DosHeader = (PIMAGE_DOS_HEADER)BaseAddress;
if (DosHeader && DosHeader->e_magic != IMAGE_DOS_SIGNATURE)
if (DosHeader && SWAPW(DosHeader->e_magic) != IMAGE_DOS_SIGNATURE)
{
DPRINT1("DosHeader->e_magic %x\n", DosHeader->e_magic);
DPRINT1("NtHeader 0x%lx\n", ((ULONG_PTR)BaseAddress + DosHeader->e_lfanew));
DPRINT1("DosHeader->e_magic %x\n", SWAPW(DosHeader->e_magic));
DPRINT1("NtHeader 0x%lx\n", ((ULONG_PTR)BaseAddress + SWAPD(DosHeader->e_lfanew)));
}
if (DosHeader && DosHeader->e_magic == IMAGE_DOS_SIGNATURE)
if (DosHeader && SWAPW(DosHeader->e_magic) == IMAGE_DOS_SIGNATURE)
{
NtHeader = (PIMAGE_NT_HEADERS)((ULONG_PTR)BaseAddress + DosHeader->e_lfanew);
if (NtHeader->Signature == IMAGE_NT_SIGNATURE)
NtHeader = (PIMAGE_NT_HEADERS)((ULONG_PTR)BaseAddress + SWAPD(DosHeader->e_lfanew));
if (SWAPD(NtHeader->Signature) == IMAGE_NT_SIGNATURE)
return NtHeader;
}
@ -79,16 +79,16 @@ RtlImageDirectoryEntryToData(PVOID BaseAddress,
if (NtHeader == NULL)
return NULL;
if (Directory >= NtHeader->OptionalHeader.NumberOfRvaAndSizes)
if (Directory >= SWAPD(NtHeader->OptionalHeader.NumberOfRvaAndSizes))
return NULL;
Va = NtHeader->OptionalHeader.DataDirectory[Directory].VirtualAddress;
Va = SWAPD(NtHeader->OptionalHeader.DataDirectory[Directory].VirtualAddress);
if (Va == 0)
return NULL;
*Size = NtHeader->OptionalHeader.DataDirectory[Directory].Size;
*Size = SWAPD(NtHeader->OptionalHeader.DataDirectory[Directory].Size);
if (MappedAsImage || Va < NtHeader->OptionalHeader.SizeOfHeaders)
if (MappedAsImage || Va < SWAPD(NtHeader->OptionalHeader.SizeOfHeaders))
return (PVOID)((ULONG_PTR)BaseAddress + Va);
/* image mapped as ordinary file, we must find raw pointer */
@ -111,14 +111,14 @@ RtlImageRvaToSection (
ULONG Va;
ULONG Count;
Count = NtHeader->FileHeader.NumberOfSections;
Count = SWAPW(NtHeader->FileHeader.NumberOfSections);
Section = (PIMAGE_SECTION_HEADER)((ULONG)&NtHeader->OptionalHeader +
NtHeader->FileHeader.SizeOfOptionalHeader);
SWAPW(NtHeader->FileHeader.SizeOfOptionalHeader));
while (Count)
{
Va = Section->VirtualAddress;
Va = SWAPD(Section->VirtualAddress);
if ((Va <= Rva) &&
(Rva < Va + Section->SizeOfRawData))
(Rva < Va + SWAPD(Section->SizeOfRawData)))
return Section;
Section++;
}
@ -144,8 +144,8 @@ RtlImageRvaToVa (
Section = *SectionHeader;
if (Section == NULL ||
Rva < Section->VirtualAddress ||
Rva >= Section->VirtualAddress + Section->SizeOfRawData)
Rva < SWAPD(Section->VirtualAddress) ||
Rva >= SWAPD(Section->VirtualAddress) + SWAPD(Section->SizeOfRawData))
{
Section = RtlImageRvaToSection (NtHeader, BaseAddress, Rva);
if (Section == NULL)
@ -157,8 +157,8 @@ RtlImageRvaToVa (
return (PVOID)((ULONG_PTR)BaseAddress +
Rva +
Section->PointerToRawData -
(ULONG_PTR)Section->VirtualAddress);
SWAPD(Section->PointerToRawData) -
(ULONG_PTR)SWAPD(Section->VirtualAddress));
}
PIMAGE_BASE_RELOCATION
@ -178,8 +178,8 @@ LdrProcessRelocationBlockLongLong(
for (i = 0; i < Count; i++)
{
Offset = *TypeOffset & 0xFFF;
Type = *TypeOffset >> 12;
Offset = SWAPW(*TypeOffset) & 0xFFF;
Type = SWAPW(*TypeOffset) >> 12;
ShortPtr = (PUSHORT)(RVA(Address, Offset));
/*
@ -204,19 +204,19 @@ LdrProcessRelocationBlockLongLong(
break;
case IMAGE_REL_BASED_LOW:
*ShortPtr += LOWORD(Delta);
*ShortPtr = SWAPW(*ShortPtr) + LOWORD(Delta);
break;
case IMAGE_REL_BASED_HIGHLOW:
LongPtr = (PULONG)RVA(Address, Offset);
*LongPtr += (ULONG)Delta;
*LongPtr = SWAPD(*LongPtr) + (ULONG)Delta;
break;
case IMAGE_REL_BASED_HIGHADJ:
case IMAGE_REL_BASED_MIPS_JMPADDR:
default:
DPRINT1("Unknown/unsupported fixup type %hu.\n", Type);
DPRINT1("Address %x, Current %d, Count %d, *TypeOffset %x\n", Address, i, Count, *TypeOffset);
DPRINT1("Address %x, Current %d, Count %d, *TypeOffset %x\n", Address, i, Count, SWAPW(*TypeOffset));
return (PIMAGE_BASE_RELOCATION)NULL;
}
@ -250,27 +250,27 @@ LdrRelocateImageWithBias(
if (NtHeaders == NULL)
return Invalid;
if (NtHeaders->FileHeader.Characteristics & IMAGE_FILE_RELOCS_STRIPPED)
if (SWAPW(NtHeaders->FileHeader.Characteristics) & IMAGE_FILE_RELOCS_STRIPPED)
{
return Conflict;
}
RelocationDDir = &NtHeaders->OptionalHeader.DataDirectory[IMAGE_DIRECTORY_ENTRY_BASERELOC];
if (RelocationDDir->VirtualAddress == 0 || RelocationDDir->Size == 0)
if (SWAPD(RelocationDDir->VirtualAddress) == 0 || SWAPD(RelocationDDir->Size) == 0)
{
return Success;
}
Delta = (ULONG_PTR)BaseAddress - NtHeaders->OptionalHeader.ImageBase + AdditionalBias;
RelocationDir = (PIMAGE_BASE_RELOCATION)((ULONG_PTR)BaseAddress + RelocationDDir->VirtualAddress);
RelocationEnd = (PIMAGE_BASE_RELOCATION)((ULONG_PTR)RelocationDir + RelocationDDir->Size);
Delta = (ULONG_PTR)BaseAddress - SWAPD(NtHeaders->OptionalHeader.ImageBase) + AdditionalBias;
RelocationDir = (PIMAGE_BASE_RELOCATION)((ULONG_PTR)BaseAddress + SWAPD(RelocationDDir->VirtualAddress));
RelocationEnd = (PIMAGE_BASE_RELOCATION)((ULONG_PTR)RelocationDir + SWAPD(RelocationDDir->Size));
while (RelocationDir < RelocationEnd &&
RelocationDir->SizeOfBlock > 0)
SWAPW(RelocationDir->SizeOfBlock) > 0)
{
Count = (RelocationDir->SizeOfBlock - sizeof(IMAGE_BASE_RELOCATION)) / sizeof(USHORT);
Address = (ULONG_PTR)RVA(BaseAddress, RelocationDir->VirtualAddress);
Count = (SWAPW(RelocationDir->SizeOfBlock) - sizeof(IMAGE_BASE_RELOCATION)) / sizeof(USHORT);
Address = (ULONG_PTR)RVA(BaseAddress, SWAPD(RelocationDir->VirtualAddress));
TypeOffset = (PUSHORT)(RelocationDir + 1);
RelocationDir = LdrProcessRelocationBlockLongLong(Address,

8
reactos/lib/rtl/rtlp.h
View file

@ -16,6 +16,14 @@ extern VOID FASTCALL CHECK_PAGED_CODE_RTL(char *file, int line);
#define PAGED_CODE_RTL()
#endif
#ifdef _PPC_
#define SWAPD(x) ((((x)&0xff)<<24)|(((x)&0xff00)<<8)|(((x)>>8)&0xff00)|(((x)>>24)&0xff))
#define SWAPW(x) ((((x)&0xff)<<8)|(((x)>>8)&0xff))
#else
#define SWAPD(x) x
#define SWAPW(x) x
#endif
VOID
NTAPI
RtlpGetStackLimits(PULONG_PTR StackBase,

5
reactos/ntoskrnl/ke/powerpc/kiinit.c
View file

@ -218,7 +218,7 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
for(;;);
}
extern int KiPageFaultHandler(int inst, ppc_trap_frame_t *frame);
extern int KiPageFaultHandler(int trap, ppc_trap_frame_t *frame);
/* Use this for early boot additions to the page table */
VOID
@ -233,7 +233,8 @@ KiSystemStartup(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
__asm__("mr 13,%0" : : "r" (KPCR_BASE));
/* Set the page fault handler to the kernel */
MmuSetPageCallback(KiPageFaultHandler);
MmuSetTrapHandler(3,KiPageFaultHandler);
MmuSetTrapHandler(4,KiPageFaultHandler);
// Make 0xf... special
MmuAllocVsid(2, 0x8000);

6
reactos/ntoskrnl/mm/powerpc/pfault.c
View file

@ -35,7 +35,7 @@ VOID MmpPpcTrapFrameToTrapFrame(ppc_trap_frame_t *frame, PKTRAP_FRAME Tf)
Tf->Dr3 = frame->dsisr;
}
int KiPageFaultHandler(int inst, ppc_trap_frame_t *frame)
int KiPageFaultHandler(int trap, ppc_trap_frame_t *frame)
{
NTSTATUS Status = STATUS_SUCCESS;
KPROCESSOR_MODE Mode;
@ -46,9 +46,9 @@ int KiPageFaultHandler(int inst, ppc_trap_frame_t *frame)
PVOID TrapInfo = NULL;
/* get the faulting address */
if (inst)
if (trap == 4) /* Instruction miss */
VirtualAddr = frame->srr0;
else
else /* Data miss */
VirtualAddr = frame->dar;
/* MSR_PR */

2
reactos/ntoskrnl/ntoskrnl_powerpc.lnk
View file

@ -22,7 +22,7 @@ SECTIONS
}
.rodata :
{
*(.rodata)
*(.rodata*)
*(.got2)
*(.eh_frame)
}