mirror of
https://github.com/reactos/reactos.git
synced 2024-10-08 02:13:56 +00:00
Update UniATA Driver to Version 0.3.9f. It works well in ROS.
thx to Samuel Serapión aka encoded. svn path=/trunk/; revision=32763
This commit is contained in:
parent
5830d67c51
commit
39f5b70ba0
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@ -86,19 +86,20 @@ ScsiDebugPrint(
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#define PRINT_PREFIX 0,
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#define KdPrint3(_x_) ScsiDebugPrint _x_ {;}
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#define KdPrint2(_x_) {ScsiDebugPrint("%x: ", PsGetCurrentThread()) ; ScsiDebugPrint _x_ ; }
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#define KdPrint(_x_) ScsiDebugPrint _x_
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#define KdPrint(_x_) ScsiDebugPrint _x_ {;}
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#else // SCSI_PORT_DBG_PRINT
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#ifndef USE_DBGPRINT_LOGGER
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ULONG
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_cdecl
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DbgPrint(
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const CHAR * Format,
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...
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);
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#endif // USE_DBGPRINT_LOGGER
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//#ifndef USE_DBGPRINT_LOGGER
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//ULONG
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//_cdecl
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//DbgPrint(
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// PCH Format,
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// ...
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// );
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//#endif // USE_DBGPRINT_LOGGER
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#define PRINT_PREFIX
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@ -107,6 +108,7 @@ DbgPrint(
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//#define LOG_ON_RAISED_IRQL_W2K TRUE
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//#define LOG_ON_RAISED_IRQL_W2K FALSE
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#define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
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#define KdPrint2(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
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#define KdPrint(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
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/*
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@ -136,8 +138,12 @@ DbgPrint(
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#else // _DEBUG
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#define KdPrint2(_x_)
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#define KdPrint(_x_)
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#define PRINT_PREFIX "UniATA: "
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//#define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
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#define KdPrint3(_x_) {;}
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#define KdPrint2(_x_) {;}
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#define KdPrint(_x_) {;}
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#define Connect_DbgPrint() {;}
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#define AtapiStallExecution(dt) ScsiPortStallExecution(dt)
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@ -235,6 +241,9 @@ typedef struct _IDE_REGISTERS_2 {
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#define DFLAGS_RCACHE_ENABLED 0x1000 // Indicates that we use read cache
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#define DFLAGS_ORIG_GEOMETRY 0x2000 //
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#define DFLAGS_REINIT_DMA 0x4000 //
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#define DFLAGS_HIDDEN 0x8000 // Hidden device, available only with special IOCTLs
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// via communication virtual device
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//#define DFLAGS_ 0x10000 //
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//
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// Used to disable 'advanced' features.
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//
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@ -287,6 +296,7 @@ typedef struct _MODE_PARAMETER_HEADER_10 {
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#define IDE_COMMAND_ATAPI_RESET 0x08
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#define IDE_COMMAND_RECALIBRATE 0x10
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#define IDE_COMMAND_READ 0x20
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#define IDE_COMMAND_READ_NO_RETR 0x21
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#define IDE_COMMAND_READ48 0x24
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#define IDE_COMMAND_READ_DMA48 0x25
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#define IDE_COMMAND_READ_DMA_Q48 0x26
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@ -296,6 +306,7 @@ typedef struct _MODE_PARAMETER_HEADER_10 {
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#define IDE_COMMAND_READ_STREAM48 0x2B
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#define IDE_COMMAND_READ_LOG48 0x2f
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#define IDE_COMMAND_WRITE 0x30
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#define IDE_COMMAND_WRITE_NO_RETR 0x31
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#define IDE_COMMAND_WRITE48 0x34
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#define IDE_COMMAND_WRITE_DMA48 0x35
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#define IDE_COMMAND_WRITE_DMA_Q48 0x36
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@ -849,8 +860,10 @@ NATIVE_MODE_CONTROLLER_INFORMATION const NativeModeAdapters[] = {
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AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);
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#define SelectDrive(chan, unit) \
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AtapiWritePort1(chan, IDX_IO1_o_DriveSelect, (unit) ? IDE_DRIVE_SELECT_2 : IDE_DRIVE_SELECT_1);
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#define SelectDrive(chan, unit) { \
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if(chan && chan->lun[unit] && chan->lun[unit]->DeviceFlags & DFLAGS_ATAPI_CHANGER) KdPrint3((" Select %d\n", unit)); \
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AtapiWritePort1(chan, IDX_IO1_o_DriveSelect, (unit) ? IDE_DRIVE_SELECT_2 : IDE_DRIVE_SELECT_1); \
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}
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#define ReadBuffer(chan, Buffer, Count, timing) \
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@ -1054,10 +1067,12 @@ CheckDevice(
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IN BOOLEAN ResetBus
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);
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#define UNIATA_FIND_DEV_UNHIDE 0x01
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BOOLEAN
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FindDevices(
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IN PVOID HwDeviceExtension,
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IN BOOLEAN AtapiOnly,
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IN ULONG Flags,
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IN ULONG Channel
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);
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@ -1154,8 +1169,10 @@ AtapiDisableInterrupts(
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IN ULONG c
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);
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#define CHAN_NOT_SPECIFIED (0xffffffffL)
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#define DEVNUM_NOT_SPECIFIED (0xffffffffL)
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#define CHAN_NOT_SPECIFIED (0xffffffffL)
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#define CHAN_NOT_SPECIFIED_CHECK_CABLE (0xfffffffeL)
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#define DEVNUM_NOT_SPECIFIED (0xffffffffL)
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#define IOMODE_NOT_SPECIFIED (0xffffffffL)
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extern ULONG
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AtapiRegCheckDevValue(
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@ -78,7 +78,8 @@ Revision History:
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// define PIO timings in nanoseconds
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#define PIO0_TIMING 600
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#define UniataGetPioTiming(LunExt) ((LunExt->TransferMode <= ATA_PIO0) ? PIO0_TIMING : 0)
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//#define UniataGetPioTiming(LunExt) ((LunExt->TransferMode <= ATA_PIO0) ? PIO0_TIMING : 0)
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#define UniataGetPioTiming(LunExt) 0 //ktp
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#ifndef __IDE_BUSMASTER_DEVICES_H__
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#define __IDE_BUSMASTER_DEVICES_H__
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@ -101,6 +102,7 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
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CHAR channel;
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// CHAR numOfChannes;
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CHAR MasterDev;
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BOOLEAN Known;
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#ifndef USER_MODE
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CHAR ChanInitOk; // 0x01 - primary, 0x02 - secondary
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BOOLEAN Isr2Enable;
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@ -198,6 +200,9 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
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#define ATA_NATIONAL_ID 0x100b
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#define ATA_SC1100 0x0502100b
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#define ATA_NETCELL_ID 0x169c
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#define ATA_NETCELL_SR 0x0044169c
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#define ATA_NVIDIA_ID 0x10de
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#define ATA_NFORCE1 0x01bc10de
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#define ATA_NFORCE2 0x006510de
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@ -354,6 +359,7 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
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#define UNIATA_NO_DPC 0x08000000
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#define UNIATA_NO_DPC_ATAPI 0x04000000
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#define UNIATA_AHCI 0x02000000
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#define UNIATA_NO80CHK 0x01000000
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#define ATPOLD 0x0100
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BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
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PCI_DEV_HW_SPEC_BM( 0005, 1191, 0x00, ATA_UDMA2, "Acard ATP850" , ATPOLD | UNIATA_SIMPLEX_ONLY ),
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PCI_DEV_HW_SPEC_BM( 0006, 1191, 0x00, ATA_UDMA4, "Acard ATP860A" , 0 ),
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PCI_DEV_HW_SPEC_BM( 0007, 1191, 0x00, ATA_UDMA4, "Acard ATP860R" , 0 ),
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PCI_DEV_HW_SPEC_BM( 0008, 1191, 0x00, ATA_UDMA6, "Acard ATP865A" , 0 ),
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PCI_DEV_HW_SPEC_BM( 0009, 1191, 0x00, ATA_UDMA6, "Acard ATP865R" , 0 ),
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PCI_DEV_HW_SPEC_BM( 0006, 1191, 0x00, ATA_UDMA4, "Acard ATP860A" , UNIATA_NO80CHK ),
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PCI_DEV_HW_SPEC_BM( 0007, 1191, 0x00, ATA_UDMA4, "Acard ATP860R" , UNIATA_NO80CHK ),
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PCI_DEV_HW_SPEC_BM( 0008, 1191, 0x00, ATA_UDMA6, "Acard ATP865A" , UNIATA_NO80CHK ),
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PCI_DEV_HW_SPEC_BM( 0009, 1191, 0x00, ATA_UDMA6, "Acard ATP865R" , UNIATA_NO80CHK ),
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PCI_DEV_HW_SPEC_BM( 5289, 10b9, 0x00, ATA_SA150, "ALI M5289" , UNIATA_SATA | UNIATA_NO_SLAVE ),
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PCI_DEV_HW_SPEC_BM( 5288, 10b9, 0x00, ATA_SA300, "ALI M5288" , UNIATA_SATA | UNIATA_NO_SLAVE ),
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PCI_DEV_HW_SPEC_BM( 5229, 10b9, 0x20, ATA_UDMA2, "ALI M5229 UDMA2" , ALIOLD ),
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PCI_DEV_HW_SPEC_BM( 5229, 10b9, 0x00, ATA_WDMA2, "ALI M5229 WDMA2" , ALIOLD ),
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PCI_DEV_HW_SPEC_BM( 7409, 1022, 0x00, ATA_UDMA4, "AMD 756" , AMDNVIDIA | 0x00 ),
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PCI_DEV_HW_SPEC_BM( 7411, 1022, 0x00, ATA_UDMA5, "AMD 766" , AMDNVIDIA | AMDCABLE|AMDBUG ),
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PCI_DEV_HW_SPEC_BM( 7441, 1022, 0x00, ATA_UDMA5, "AMD 768" , AMDNVIDIA | AMDCABLE ),
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PCI_DEV_HW_SPEC_BM( 7469, 1022, 0x00, ATA_UDMA6, "AMD 8111" , AMDNVIDIA | AMDCABLE ),
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PCI_DEV_HW_SPEC_BM( 7401, 1022, 0x00, ATA_UDMA2, "AMD 755" , AMDNVIDIA | 0x00 ),
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PCI_DEV_HW_SPEC_BM( 7409, 1022, 0x00, ATA_UDMA4, "AMD 756" , AMDNVIDIA | UNIATA_NO80CHK ),
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PCI_DEV_HW_SPEC_BM( 7411, 1022, 0x00, ATA_UDMA5, "AMD 766" , AMDNVIDIA | AMDBUG ),
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PCI_DEV_HW_SPEC_BM( 7441, 1022, 0x00, ATA_UDMA5, "AMD 768" , AMDNVIDIA ),
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PCI_DEV_HW_SPEC_BM( 7469, 1022, 0x00, ATA_UDMA6, "AMD 8111" , AMDNVIDIA ),
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PCI_DEV_HW_SPEC_BM( 4349, 1002, 0x00, ATA_UDMA5, "ATI IXP200" , 0 ),
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PCI_DEV_HW_SPEC_BM( 4369, 1002, 0x00, ATA_UDMA6, "ATI IXP300" , 0 ),
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@ -520,6 +527,10 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
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PCI_DEV_HW_SPEC_BM( 2825, 8086, 0x00, ATA_SA300, "Intel ICH8" , UNIATA_SATA | UNIATA_AHCI ),
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PCI_DEV_HW_SPEC_BM( 2829, 8086, 0x00, ATA_SA300, "Intel ICH8M" , UNIATA_SATA | UNIATA_AHCI ),
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PCI_DEV_HW_SPEC_BM( 282a, 8086, 0x00, ATA_SA300, "Intel ICH8M" , UNIATA_SATA | UNIATA_AHCI ),
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PCI_DEV_HW_SPEC_BM( 2920, 8086, 0x00, ATA_SA300, "Intel ICH9" , UNIATA_SATA | UNIATA_AHCI ),
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PCI_DEV_HW_SPEC_BM( 2926, 8086, 0x00, ATA_SA300, "Intel ICH9" , UNIATA_SATA | UNIATA_AHCI ),
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PCI_DEV_HW_SPEC_BM( 2923, 8086, 0x00, ATA_SA300, "Intel ICH9" , UNIATA_SATA | UNIATA_AHCI ),
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PCI_DEV_HW_SPEC_BM( 2922, 8086, 0x00, ATA_SA300, "Intel ICH9" , UNIATA_SATA | UNIATA_AHCI ),
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// PCI_DEV_HW_SPEC_BM( 3200, 8086, 0x00, ATA_SA150, "Intel 31244" , UNIATA_SATA ),
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PCI_DEV_HW_SPEC_BM( 01bc, 10de, 0x00, ATA_UDMA5, "nVidia nForce" , AMDNVIDIA ),
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@ -690,6 +701,8 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
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PCI_DEV_HW_SPEC_BM( 8172, 1283, 0x00, ATA_UDMA2, "IT8172" , 0 ),
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PCI_DEV_HW_SPEC_BM( 8212, 1283, 0x00, ATA_UDMA6, "IT8212F" , ITE_133 ),
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PCI_DEV_HW_SPEC_BM( 0044, 169c, 0x00, ATA_UDMA2, "Netcell SR3000/5000", 0 ),
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PCI_DEV_HW_SPEC_BM( 8013, 3388, 0x00, ATA_DMA, "HiNT VXII EIDE" , 0 ),
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// Terminator
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@ -77,8 +77,6 @@ Revision History:
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#define PCI_ADDRESS_IOMASK 0xfffffff0
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#define ATA_BM_OFFSET1 0x08
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#define ATA_DMA_ENTRIES 256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
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#define ATA_DMA_EOT 0x80000000
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#define ATA_IOSIZE 0x08
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#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
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#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
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@ -87,6 +85,9 @@ Revision History:
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#define ATA_PC98_BANKIOSIZE 0x01
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#define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
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#define ATA_DMA_ENTRIES 256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
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#define ATA_DMA_EOT 0x80000000
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#define DEV_BSIZE 512
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#define ATAPI_MAGIC_LSB 0x14
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@ -348,6 +349,34 @@ typedef struct _IDE_SATA_REGISTERS {
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#define IDX_MAX_REG (IDX_SATA_IO+IDX_SATA_IO_SZ)
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typedef union _AHCI_IS_REG {
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struct {
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ULONG DHRS:1;// Device to Host Register FIS Interrupt
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ULONG PSS:1; // PIO Setup FIS Interrupt
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ULONG DSS:1; // DMA Setup FIS Interrupt
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ULONG SDBS:1;// Set Device Bits Interrupt
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ULONG UFS:1; // Unknown FIS Interrupt
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ULONG DPS:1; // Descriptor Processed
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ULONG PCS:1; // Port Connect Change Status
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ULONG DMPS:1;// Device Mechanical Presence Status
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ULONG Reserved_8_21:14;
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ULONG PRCS:1;// PhyRdy Change Status
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ULONG IPMS:1;// Incorrect Port Multiplier Status
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ULONG OFS:1; // Overflow Status
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ULONG Reserved_25:1;
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ULONG INFS:1;// Interface Non-fatal Error Status
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ULONG IFS:1; // Interface Fatal Error Status
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ULONG HBDS:1;// Host Bus Data Error Status
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ULONG HBFS:1;// Host Bus Fatal Error Status
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ULONG TFES:1;// Task File Error Status
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ULONG CPDS:1;// Cold Port Detect Status
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};
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ULONG Reg;
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} AHCI_IS_REG, *PAHCI_IS_REG;
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typedef struct _IDE_AHCI_PORT_REGISTERS {
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union {
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struct {
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@ -366,31 +395,9 @@ typedef struct _IDE_AHCI_PORT_REGISTERS {
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};
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union {
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ULONG Reg; // interrupt status
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struct {
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ULONG DHRS:1;// Device to Host Register FIS Interrupt
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ULONG PSS:1; // PIO Setup FIS Interrupt
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ULONG DSS:1; // DMA Setup FIS Interrupt
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ULONG SDBS:1;// Set Device Bits Interrupt
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ULONG UFS:1; // Unknown FIS Interrupt
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ULONG DPS:1; // Descriptor Processed
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ULONG PCS:1; // Port Connect Change Status
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ULONG DMPS:1;// Device Mechanical Presence Status
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ULONG Reserved_8_21:14;
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ULONG PRCS:1;// PhyRdy Change Status
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ULONG IPMS:1;// Incorrect Port Multiplier Status
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ULONG OFS:1; // Overflow Status
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ULONG Reserved_25:1;
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ULONG INFS:1;// Interface Non-fatal Error Status
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ULONG IFS:1; // Interface Fatal Error Status
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ULONG HBDS:1;// Host Bus Data Error Status
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ULONG HBFS:1;// Host Bus Fatal Error Status
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ULONG TFES:1;// Task File Error Status
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ULONG CPDS:1;// Cold Port Detect Status
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};
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} IS;
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ULONG IS_Reg; // interrupt status
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AHCI_IS_REG IS;
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};
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union {
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ULONG Reg; // interrupt enable
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@ -513,13 +520,19 @@ typedef struct _IDE_AHCI_PORT_REGISTERS {
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} IDE_AHCI_PORT_REGISTERS, *PIDE_AHCI_PORT_REGISTERS;
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#define IDX_AHCI_P_IS (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
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#define IDX_AHCI_P_CI (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
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typedef struct _IDE_AHCI_PRD_ENTRY {
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union {
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ULONG base;
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ULONGLONG base64;
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struct {
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ULONG DBA;
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ULONG DBAU;
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union {
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ULONG DBAU;
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ULONG baseu;
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};
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};
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};
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ULONG Reserved1;
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@ -530,6 +543,22 @@ typedef struct _IDE_AHCI_PRD_ENTRY {
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} IDE_AHCI_PRD_ENTRY, *PIDE_AHCI_PRD_ENTRY;
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#define ATA_AHCI_DMA_ENTRIES (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
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typedef struct _IDE_AHCI_CMD {
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UCHAR cfis[64];
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UCHAR acmd[32];
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UCHAR Reserved[32];
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IDE_AHCI_PRD_ENTRY prd_tab[ATA_AHCI_DMA_ENTRIES];
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} IDE_AHCI_CMD, *PIDE_AHCI_CMD;
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typedef struct _IDE_AHCI_CMD_LIST {
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USHORT cmd_flags;
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USHORT prd_length; /* PRD entries */
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ULONG bytecount;
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ULONGLONG cmd_table_phys; /* 128byte aligned */
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} IDE_AHCI_CMD_LIST, *PIDE_AHCI_CMD_LIST;
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#define IsBusMaster(pciData) \
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( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \
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(PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/))
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@ -545,31 +574,52 @@ typedef struct _IDE_AHCI_PRD_ENTRY {
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//#define INT_Q_SIZE 32
|
||||
#define MIN_REQ_TTL 4
|
||||
|
||||
struct _ATA_REQ;
|
||||
union _ATA_REQ;
|
||||
|
||||
typedef struct _ATA_REQ {
|
||||
typedef union _ATA_REQ {
|
||||
// ULONG reqId; // serial
|
||||
struct _ATA_REQ* next_req;
|
||||
struct _ATA_REQ* prev_req;
|
||||
struct {
|
||||
|
||||
PSCSI_REQUEST_BLOCK Srb; // Current request on controller.
|
||||
union {
|
||||
|
||||
PUSHORT DataBuffer; // Data buffer pointer.
|
||||
ULONG WordsLeft; // Data words left.
|
||||
ULONG TransferLength; // Originally requested transfer length
|
||||
LONGLONG lba;
|
||||
ULONG bcount;
|
||||
struct {
|
||||
union _ATA_REQ* next_req;
|
||||
union _ATA_REQ* prev_req;
|
||||
|
||||
UCHAR retry;
|
||||
UCHAR ttl;
|
||||
// UCHAR tag;
|
||||
UCHAR Flags;
|
||||
UCHAR ReqState;
|
||||
PSCSI_REQUEST_BLOCK Srb; // Current request on controller.
|
||||
|
||||
PSCSI_REQUEST_BLOCK OriginalSrb; // Mechanism Status Srb Data
|
||||
PUSHORT DataBuffer; // Data buffer pointer.
|
||||
ULONG WordsLeft; // Data words left.
|
||||
ULONG TransferLength; // Originally requested transfer length
|
||||
LONGLONG lba;
|
||||
ULONG WordsTransfered;// Data words already transfered.
|
||||
ULONG bcount;
|
||||
|
||||
ULONG dma_base;
|
||||
BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
|
||||
UCHAR retry;
|
||||
UCHAR ttl;
|
||||
// UCHAR tag;
|
||||
UCHAR Flags;
|
||||
UCHAR ReqState;
|
||||
|
||||
PSCSI_REQUEST_BLOCK OriginalSrb; // Mechanism Status Srb Data
|
||||
|
||||
ULONG dma_entries;
|
||||
union {
|
||||
ULONG dma_base;
|
||||
ULONGLONG ahci_base64; // for AHCI
|
||||
};
|
||||
};
|
||||
UCHAR padding_128b[128];
|
||||
};
|
||||
struct {
|
||||
union {
|
||||
BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
|
||||
IDE_AHCI_CMD ahci_cmd; // for AHCI
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UCHAR padding_4kb[PAGE_SIZE];
|
||||
|
||||
} ATA_REQ, *PATA_REQ;
|
||||
|
||||
|
@ -588,6 +638,7 @@ typedef struct _ATA_REQ {
|
|||
#define REQ_STATE_QUEUED 0x10
|
||||
|
||||
#define REQ_STATE_PREPARE_TO_TRANSFER 0x20
|
||||
#define REQ_STATE_PREPARE_TO_NEXT 0x21
|
||||
#define REQ_STATE_READY_TO_TRANSFER 0x30
|
||||
|
||||
#define REQ_STATE_EXPECTING_INTR 0x40
|
||||
|
@ -724,7 +775,14 @@ typedef struct _HW_CHANNEL {
|
|||
PVOID DB_IO;
|
||||
ULONG DB_IO_PhAddr;
|
||||
|
||||
PUCHAR DmaBuffer;
|
||||
PUCHAR DmaBuffer;
|
||||
|
||||
//
|
||||
PIDE_AHCI_CMD_LIST AHCI_CL;
|
||||
ULONGLONG AHCI_CL_PhAddr;
|
||||
PVOID AHCI_FIS; // is not actually used by UniATA now, but is required by AHCI controller
|
||||
ULONGLONG AHCI_FIS_PhAddr;
|
||||
// Note: in contrast to FBSD, we keep PRD and CMD item in AtaReq structure
|
||||
|
||||
#ifdef QUEUE_STATISTICS
|
||||
LONGLONG QueueStat[MAX_QUEUE_STAT];
|
||||
|
@ -732,7 +790,7 @@ typedef struct _HW_CHANNEL {
|
|||
LONGLONG IntersectCount;
|
||||
LONGLONG TryReorderCount;
|
||||
LONGLONG TryReorderHeadCount;
|
||||
LONGLONG TryReorderTailCount; // in-order requests
|
||||
LONGLONG TryReorderTailCount; /* in-order requests */
|
||||
#endif //QUEUE_STATISTICS
|
||||
|
||||
//ULONG BaseMemAddress;
|
||||
|
@ -800,13 +858,16 @@ typedef struct _HW_LU_EXTENSION {
|
|||
ULONG opt_PreferedTransferMode;
|
||||
BOOLEAN opt_ReadCacheEnable;
|
||||
BOOLEAN opt_WriteCacheEnable;
|
||||
UCHAR opt_ReadOnly;
|
||||
// padding
|
||||
BOOLEAN opt_reserved[2];
|
||||
BOOLEAN opt_reserved[1];
|
||||
|
||||
struct _SBadBlockListItem* bbListDescr;
|
||||
struct _SBadBlockRange* arrBadBlocks;
|
||||
ULONG nBadBlocks;
|
||||
|
||||
struct _HW_DEVICE_EXTENSION* DeviceExtension;
|
||||
|
||||
#ifdef IO_STATISTICS
|
||||
|
||||
LONGLONG ModeErrorCount[MAX_RETRIES];
|
||||
|
@ -833,7 +894,7 @@ typedef struct _HW_DEVICE_EXTENSION {
|
|||
ULONG FirstChannelToCheck;
|
||||
#if 1
|
||||
HW_LU_EXTENSION lun[IDE_MAX_LUN];
|
||||
HW_CHANNEL chan[AHCI_MAX_PORT]; // IDE_MAX_CHAN
|
||||
HW_CHANNEL chan[AHCI_MAX_PORT/*IDE_MAX_CHAN*/];
|
||||
#else
|
||||
PHW_LU_EXTENSION lun;
|
||||
PHW_CHANNEL chan;
|
||||
|
@ -851,12 +912,12 @@ typedef struct _HW_DEVICE_EXTENSION {
|
|||
|
||||
ULONG ActiveDpcChan;
|
||||
ULONG FirstDpcChan;
|
||||
|
||||
// PHW_TIMER HwScsiTimer1;
|
||||
// PHW_TIMER HwScsiTimer2;
|
||||
// LONGLONG DpcTime1;
|
||||
// LONGLONG DpcTime2;
|
||||
|
||||
/*
|
||||
PHW_TIMER HwScsiTimer1;
|
||||
PHW_TIMER HwScsiTimer2;
|
||||
LONGLONG DpcTime1;
|
||||
LONGLONG DpcTime2;
|
||||
*/
|
||||
ULONG queue_depth;
|
||||
|
||||
PDEVICE_OBJECT Isr2DevObj;
|
||||
|
@ -891,6 +952,7 @@ typedef struct _HW_DEVICE_EXTENSION {
|
|||
ULONG MaxTransferMode; // max transfer mode supported by controller
|
||||
ULONG HwFlags;
|
||||
INTERFACE_TYPE OrigAdapterInterfaceType;
|
||||
INTERFACE_TYPE AdapterInterfaceType;
|
||||
ULONG MaximumDmaTransferLength;
|
||||
ULONG AlignmentMask;
|
||||
|
||||
|
@ -908,6 +970,8 @@ typedef struct _HW_DEVICE_EXTENSION {
|
|||
BOOLEAN opt_AtapiDmaRawRead; // default TRUE
|
||||
BOOLEAN opt_AtapiDmaReadWrite; // default TRUE
|
||||
|
||||
PCHAR FullDevName;
|
||||
|
||||
} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
|
||||
|
||||
typedef struct _ISR2_DEVICE_EXTENSION {
|
||||
|
@ -921,6 +985,8 @@ typedef struct _ISR2_DEVICE_EXTENSION {
|
|||
extern UCHAR pciBuffer[256];
|
||||
extern PBUSMASTER_CONTROLLER_INFORMATION BMList;
|
||||
extern ULONG BMListLen;
|
||||
extern ULONG IsaCount;
|
||||
extern ULONG MCACount;
|
||||
|
||||
//extern const CHAR retry_Wdma[MAX_RETRIES+1];
|
||||
//extern const CHAR retry_Udma[MAX_RETRIES+1];
|
||||
|
@ -931,6 +997,26 @@ UniataEnumBusMasterController(
|
|||
PVOID Argument2
|
||||
);
|
||||
|
||||
extern ULONG DDKAPI
|
||||
UniataFindCompatBusMasterController1(
|
||||
IN PVOID HwDeviceExtension,
|
||||
IN PVOID Context,
|
||||
IN PVOID BusInformation,
|
||||
IN PCHAR ArgumentString,
|
||||
IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
|
||||
OUT PBOOLEAN Again
|
||||
);
|
||||
|
||||
extern ULONG DDKAPI
|
||||
UniataFindCompatBusMasterController2(
|
||||
IN PVOID HwDeviceExtension,
|
||||
IN PVOID Context,
|
||||
IN PVOID BusInformation,
|
||||
IN PCHAR ArgumentString,
|
||||
IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
|
||||
OUT PBOOLEAN Again
|
||||
);
|
||||
|
||||
extern ULONG DDKAPI
|
||||
UniataFindBusMasterController(
|
||||
IN PVOID HwDeviceExtension,
|
||||
|
@ -941,6 +1027,16 @@ UniataFindBusMasterController(
|
|||
OUT PBOOLEAN Again
|
||||
);
|
||||
|
||||
extern ULONG DDKAPI
|
||||
UniataFindFakeBusMasterController(
|
||||
IN PVOID HwDeviceExtension,
|
||||
IN PVOID Context,
|
||||
IN PVOID BusInformation,
|
||||
IN PCHAR ArgumentString,
|
||||
IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
|
||||
OUT PBOOLEAN Again
|
||||
);
|
||||
|
||||
extern NTSTATUS
|
||||
UniataConnectIntr2(
|
||||
IN PVOID HwDeviceExtension
|
||||
|
@ -962,6 +1058,9 @@ ScsiPortGetBusDataByOffset(
|
|||
IN ULONG Length
|
||||
);
|
||||
|
||||
#define PCIBUSNUM_NOT_SPECIFIED (0xffffffffL)
|
||||
#define PCISLOTNUM_NOT_SPECIFIED (0xffffffffL)
|
||||
|
||||
extern ULONG
|
||||
AtapiFindListedDev(
|
||||
PBUSMASTER_CONTROLLER_INFORMATION BusMasterAdapters,
|
||||
|
@ -1021,8 +1120,6 @@ AtapiDmaStart(
|
|||
IN PSCSI_REQUEST_BLOCK Srb
|
||||
);
|
||||
|
||||
//#define DEVNUM_NOT_SPECIFIED (0xffffffffL)
|
||||
|
||||
extern UCHAR
|
||||
AtapiDmaDone(
|
||||
IN PVOID HwDeviceExtension,
|
||||
|
@ -1327,6 +1424,8 @@ AtapiReadBuffer2(
|
|||
chan->lun[1] = &(deviceExtension->lun[c*2+1]); \
|
||||
chan->AltRegMap = deviceExtension->AltRegMap; \
|
||||
chan->NextDpcChan = -1; \
|
||||
chan->lun[0]->DeviceExtension = deviceExtension; \
|
||||
chan->lun[1]->DeviceExtension = deviceExtension; \
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
|
@ -1336,6 +1435,11 @@ AtapiReadChipConfig(
|
|||
IN ULONG channel // physical channel
|
||||
);
|
||||
|
||||
VOID
|
||||
UniataForgetDevice(
|
||||
PHW_LU_EXTENSION LunExt
|
||||
);
|
||||
|
||||
extern ULONG SkipRaids;
|
||||
extern ULONG ForceSimplex;
|
||||
|
||||
|
@ -1343,4 +1447,6 @@ extern BOOLEAN InDriverEntry;
|
|||
|
||||
extern BOOLEAN g_opt_Verbose;
|
||||
|
||||
extern BOOLEAN WinVer_WDM_Model;
|
||||
|
||||
#endif //__IDE_BUSMASTER_H__
|
||||
|
|
|
@ -58,6 +58,12 @@
|
|||
|
||||
#define IO_STATISTICS
|
||||
|
||||
/***************************************/
|
||||
// Misc
|
||||
/***************************************/
|
||||
|
||||
//#define NAVO_TEST
|
||||
|
||||
/***************************************************/
|
||||
/* Validate Options */
|
||||
/***************************************************/
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -176,7 +176,24 @@ err_1:
|
|||
}
|
||||
}
|
||||
#endif //USE_OWN_DMA
|
||||
|
||||
/*
|
||||
if(deviceExtension->HwFlags & UNIATA_AHCI) {
|
||||
chan->AHCI_CLP = MmAllocateContiguousMemory(sizeof(((PATA_REQ)NULL)->dma_tab), ph4gb);
|
||||
if(chan->AHCI_CLP) {
|
||||
chan->DB_PRD_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->DB_PRD), &i, &ph_addru);
|
||||
if(!chan->DB_PRD_PhAddr || !i || ((LONG)(chan->DB_PRD_PhAddr) == -1)) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD BASE\n" ));
|
||||
chan->DB_PRD = NULL;
|
||||
chan->DB_PRD_PhAddr = 0;
|
||||
return;
|
||||
}
|
||||
if(ph_addru) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD below 4Gb\n" ));
|
||||
goto err_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
return;
|
||||
} // end AtapiDmaAlloc()
|
||||
|
||||
|
@ -196,36 +213,45 @@ AtapiDmaSetup(
|
|||
PHW_CHANNEL chan = &(deviceExtension->chan[lChannel]);
|
||||
PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension);
|
||||
BOOLEAN use_DB_IO = FALSE;
|
||||
BOOLEAN use_AHCI = FALSE;
|
||||
ULONG orig_count = count;
|
||||
ULONG max_entries = (deviceExtension->HwFlags & UNIATA_AHCI) ? ATA_AHCI_DMA_ENTRIES : ATA_DMA_ENTRIES;
|
||||
|
||||
AtaReq->Flags &= ~REQ_FLAG_DMA_OPERATION;
|
||||
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: mode %#x\n", deviceExtension->lun[lChannel*2+DeviceNumber].TransferMode ));
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: mode %#x, data %x, count %x, lCh %x, dev %x\n",
|
||||
deviceExtension->lun[lChannel*2+DeviceNumber].TransferMode,
|
||||
data, count, lChannel, DeviceNumber ));
|
||||
if(deviceExtension->lun[lChannel*2+DeviceNumber].TransferMode < ATA_DMA) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: Not DMA mode, assume this is just preparation\n" ));
|
||||
//return FALSE;
|
||||
}
|
||||
//KdPrint2((PRINT_PREFIX " checkpoint 1\n" ));
|
||||
if(!count) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: count=0\n" ));
|
||||
return FALSE;
|
||||
}
|
||||
//KdPrint2((PRINT_PREFIX " checkpoint 2\n" ));
|
||||
if(count > deviceExtension->MaximumDmaTransferLength) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: deviceExtension->MaximumDmaTransferLength > count\n" ));
|
||||
return FALSE;
|
||||
}
|
||||
//KdPrint2((PRINT_PREFIX " checkpoint 3\n" ));
|
||||
if((ULONG)data & deviceExtension->AlignmentMask) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: unaligned data: %#x (%#x)\n", data, deviceExtension->AlignmentMask));
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
// NOTE: This code is intended for 32-bit capable controllers only.
|
||||
// 64-bit capable controllers shall be handled separately.
|
||||
//KdPrint2((PRINT_PREFIX " checkpoint 4\n" ));
|
||||
KdPrint2((PRINT_PREFIX " get Phys(PRD=%x)\n", &(AtaReq->dma_tab) ));
|
||||
dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)&(AtaReq->dma_tab) /*chan->dma_tab*/, &i, &dma_baseu);
|
||||
if(dma_baseu) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: SRB built-in PRD above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
|
||||
dma_base = chan->DB_PRD_PhAddr;
|
||||
AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
|
||||
i = 1;
|
||||
if(!deviceExtension->Host64) {
|
||||
dma_base = chan->DB_PRD_PhAddr;
|
||||
AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
|
||||
i = 1;
|
||||
}
|
||||
} else
|
||||
if(!dma_base || !i || ((LONG)(dma_base) == -1)) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No BASE\n" ));
|
||||
|
@ -233,17 +259,23 @@ AtapiDmaSetup(
|
|||
}
|
||||
AtaReq->dma_base = dma_base;
|
||||
|
||||
KdPrint2((PRINT_PREFIX " get Phys(data=%x)\n", data ));
|
||||
dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu);
|
||||
if(dma_baseu) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
|
||||
if(!deviceExtension->Host64) {
|
||||
retry_DB_IO:
|
||||
use_DB_IO = TRUE;
|
||||
dma_base = chan->DB_IO_PhAddr;
|
||||
data = (PUCHAR)(chan->DB_IO);
|
||||
use_DB_IO = TRUE;
|
||||
dma_base = chan->DB_IO_PhAddr;
|
||||
data = (PUCHAR)(chan->DB_IO);
|
||||
} else {
|
||||
AtaReq->ahci_base64 = (ULONGLONG)dma_base | ((ULONGLONG)dma_baseu << 32);
|
||||
}
|
||||
} else
|
||||
if(!dma_count || ((LONG)(dma_base) == -1)) {
|
||||
AtaReq->dma_base = 0;
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No 1st block\n" ));
|
||||
//AtaReq->dma_base = NULL;
|
||||
AtaReq->ahci_base64 = NULL;
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
@ -253,26 +285,37 @@ retry_DB_IO:
|
|||
i = 0;
|
||||
|
||||
while (count) {
|
||||
AtaReq->dma_tab[i].base = dma_base;
|
||||
AtaReq->dma_tab[i].count = (dma_count & 0xffff);
|
||||
if(deviceExtension->HwFlags & UNIATA_AHCI) {
|
||||
AtaReq->ahci_cmd.prd_tab[i].base = dma_base;
|
||||
AtaReq->ahci_cmd.prd_tab[i].baseu = dma_baseu;
|
||||
AtaReq->ahci_cmd.prd_tab[i].DBC = ((dma_count-1) & 0x3fffff);
|
||||
} else {
|
||||
AtaReq->dma_tab[i].base = dma_base;
|
||||
AtaReq->dma_tab[i].count = (dma_count & 0xffff);
|
||||
}
|
||||
i++;
|
||||
if (i >= ATA_DMA_ENTRIES) {
|
||||
AtaReq->dma_base = 0;
|
||||
if (i >= max_entries) {
|
||||
KdPrint2((PRINT_PREFIX "too many segments in DMA table\n" ));
|
||||
//AtaReq->dma_base = NULL;
|
||||
AtaReq->ahci_base64 = NULL;
|
||||
return FALSE;
|
||||
}
|
||||
KdPrint2((PRINT_PREFIX " get Phys(data[n]=%x)\n", data ));
|
||||
dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu);
|
||||
if(dma_baseu) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
|
||||
if(use_DB_IO) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
|
||||
return FALSE;
|
||||
if(!deviceExtension->Host64) {
|
||||
if(use_DB_IO) {
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
|
||||
return FALSE;
|
||||
}
|
||||
count = orig_count;
|
||||
goto retry_DB_IO;
|
||||
}
|
||||
count = orig_count;
|
||||
goto retry_DB_IO;
|
||||
} else
|
||||
if(!dma_count || !dma_base || ((LONG)(dma_base) == -1)) {
|
||||
AtaReq->dma_base = 0;
|
||||
//AtaReq->dma_base = NULL;
|
||||
AtaReq->ahci_base64 = NULL;
|
||||
KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No NEXT block\n" ));
|
||||
return FALSE;
|
||||
}
|
||||
|
@ -281,8 +324,16 @@ retry_DB_IO:
|
|||
data += min(count, PAGE_SIZE);
|
||||
count -= min(count, PAGE_SIZE);
|
||||
}
|
||||
AtaReq->dma_tab[i].base = dma_base;
|
||||
AtaReq->dma_tab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
|
||||
KdPrint2((PRINT_PREFIX " set TERM\n" ));
|
||||
if(deviceExtension->HwFlags & UNIATA_AHCI) {
|
||||
AtaReq->ahci_cmd.prd_tab[i].base = dma_base;
|
||||
AtaReq->ahci_cmd.prd_tab[i].baseu = dma_baseu;
|
||||
AtaReq->ahci_cmd.prd_tab[i].DBC = ((dma_count-1) & 0x3fffff);
|
||||
} else {
|
||||
AtaReq->dma_tab[i].base = dma_base;
|
||||
AtaReq->dma_tab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
|
||||
}
|
||||
AtaReq->dma_entries = i;
|
||||
|
||||
if(use_DB_IO) {
|
||||
AtaReq->Flags |= REQ_FLAG_DMA_DBUF;
|
||||
|
@ -405,7 +456,11 @@ AtapiDmaStart(
|
|||
if(AtaReq->Flags & REQ_FLAG_DMA_DBUF_PRD) {
|
||||
KdPrint2((PRINT_PREFIX " DBUF_PRD\n"));
|
||||
ASSERT(FALSE);
|
||||
RtlCopyMemory(chan->DB_PRD, &(AtaReq->dma_tab), sizeof(AtaReq->dma_tab));
|
||||
if(deviceExtension->HwFlags & UNIATA_AHCI) {
|
||||
RtlCopyMemory(chan->DB_PRD, &(AtaReq->ahci_cmd), sizeof(AtaReq->ahci_cmd));
|
||||
} else {
|
||||
RtlCopyMemory(chan->DB_PRD, &(AtaReq->dma_tab), sizeof(AtaReq->dma_tab));
|
||||
}
|
||||
}
|
||||
if(!(Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
|
||||
(AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
|
||||
|
@ -567,16 +622,25 @@ limit_lba48:
|
|||
LunExt->DeviceFlags |= REQ_FLAG_FORCE_DOWNRATE_LBA48;
|
||||
limit_pio:
|
||||
// do not make extra work if we already use PIO
|
||||
KdPrint2((PRINT_PREFIX
|
||||
"AtapiDmaReinit: set PIO mode on Device %d (%x -> %x)\n", ldev & 1, LunExt->TransferMode, ATA_PIO0+apiomode));
|
||||
if(/*LunExt->TransferMode >= ATA_DMA*/
|
||||
LunExt->TransferMode != ATA_PIO0+apiomode
|
||||
(LunExt->TransferMode > ATA_PIO5) && (LunExt->TransferMode != ATA_PIO0+apiomode)
|
||||
) {
|
||||
KdPrint2((PRINT_PREFIX
|
||||
"AtapiDmaReinit: set PIO mode on Device %d (%x -> %x)\n", ldev & 1, LunExt->TransferMode, ATA_PIO0+apiomode));
|
||||
AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
|
||||
apiomode,
|
||||
-1,
|
||||
-1 );
|
||||
} else
|
||||
if(LunExt->LimitedTransferMode < LunExt->TransferMode) {
|
||||
KdPrint2((PRINT_PREFIX
|
||||
"AtapiDmaReinit: set PIO mode on Device %d (%x -> %x) (2)\n", ldev & 1, LunExt->TransferMode, LunExt->LimitedTransferMode));
|
||||
AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
|
||||
LunExt->LimitedTransferMode-ATA_PIO0,
|
||||
-1,
|
||||
-1 );
|
||||
}
|
||||
|
||||
} else {
|
||||
KdPrint2((PRINT_PREFIX
|
||||
"AtapiDmaReinit: set MAX mode on Device %d\n", ldev & 1));
|
||||
|
@ -653,23 +717,23 @@ AtaSetTransferMode(
|
|||
IDE_COMMAND_SET_FEATURES, 0, 0, 0,
|
||||
(UCHAR)((mode > ATA_UDMA6) ? ATA_UDMA6 : mode), ATA_C_F_SETXFER, ATA_WAIT_BASE_READY);
|
||||
if(statusByte & IDE_STATUS_ERROR) {
|
||||
KdPrint2((PRINT_PREFIX " wait ready after error\n"));
|
||||
KdPrint3((PRINT_PREFIX " wait ready after error\n"));
|
||||
if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
|
||||
AtapiStallExecution(10);
|
||||
} else {
|
||||
AtapiStallExecution(100);
|
||||
}
|
||||
apiomode = (CHAR)AtaPioMode(&(LunExt->IdentifyData));
|
||||
if( apiomode > 0 &&
|
||||
(CHAR)AtaWmode(&(LunExt->IdentifyData)) > 0 &&
|
||||
(CHAR)AtaUmode(&(LunExt->IdentifyData)) > 0
|
||||
if( (apiomode > 0) &&
|
||||
((CHAR)AtaWmode(&(LunExt->IdentifyData)) > 0) &&
|
||||
((CHAR)AtaUmode(&(LunExt->IdentifyData)) > 0)
|
||||
) {
|
||||
return FALSE;
|
||||
}
|
||||
if(mode > ATA_PIO2) {
|
||||
return FALSE;
|
||||
}
|
||||
KdPrint2((PRINT_PREFIX " assume that drive doesn't support mode swithingm using PIO%d\n", apiomode));
|
||||
KdPrint3((PRINT_PREFIX " assume that drive doesn't support mode swithing using PIO%d\n", apiomode));
|
||||
mode = ATA_PIO0 + apiomode;
|
||||
}
|
||||
//if(mode <= ATA_UDMA6) {
|
||||
|
@ -780,7 +844,7 @@ AtapiDmaInit(
|
|||
goto try_generic_dma;
|
||||
}
|
||||
|
||||
if(deviceExtension->BaseIoAddressSATA_0.Addr) {
|
||||
if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
|
||||
//if(ChipFlags & UNIATA_SATA) {
|
||||
/****************/
|
||||
/* SATA Generic */
|
||||
|
@ -1060,6 +1124,17 @@ set_new_acard:
|
|||
}
|
||||
/* Use GENERIC PIO */
|
||||
break;
|
||||
case ATA_NETCELL_ID:
|
||||
/***********/
|
||||
/* NetCell */
|
||||
/***********/
|
||||
if (wdmamode >= 2 && apiomode >= 4) {
|
||||
if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
/* Use GENERIC PIO */
|
||||
break;
|
||||
case ATA_HIGHPOINT_ID: {
|
||||
/********************/
|
||||
/* High Point (HPT) */
|
||||
|
@ -1184,6 +1259,7 @@ set_new_acard:
|
|||
if(ChipFlags & ICH4_FIX) {
|
||||
return;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -1978,3 +2054,4 @@ via82c_timing(
|
|||
SetPciConfig1(0x4b-dev, (FIT(active - 1, 0, 0xf) << 4) | FIT(recover - 1, 0, 0xf) );
|
||||
} // end via82c_timing()
|
||||
|
||||
|
||||
|
|
|
@ -244,7 +244,7 @@ UniataChipDetect(
|
|||
i = Ata_is_dev_listed(DevTypeInfo, VendorID, DeviceID, RevID, -1);
|
||||
for_ugly_chips:
|
||||
KdPrint2((PRINT_PREFIX "i: %#x\n", i));
|
||||
if(i == 0xFFFFFFFF) {
|
||||
if(i == BMLIST_TERMINATOR) {
|
||||
return FALSE;
|
||||
}
|
||||
deviceExtension->MaxTransferMode = DevTypeInfo[i].MaxTransferMode;
|
||||
|
@ -556,7 +556,7 @@ for_ugly_chips:
|
|||
tmp32 == ATA_SIS5517) {
|
||||
i = AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION*)&SiSSouthAdapters[0],
|
||||
-1, HwDeviceExtension, SystemIoBusNumber, -1, NULL);
|
||||
if(i != 0xFFFFFFFF) {
|
||||
if(i != BMLIST_TERMINATOR) {
|
||||
deviceExtension->HwFlags = (deviceExtension->HwFlags & ~CHIPTYPE_MASK) | SIS133OLD;
|
||||
//deviceExtension->MaxTransferMode = ATA_UDMA6;
|
||||
deviceExtension->MaxTransferMode = SiSSouthAdapters[i].MaxTransferMode;
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -350,7 +350,7 @@ UniataGetNextChannel(
|
|||
cost_c = chan->queue_depth * (chan->ChannelSelectWaitCount+1);
|
||||
}
|
||||
}
|
||||
if(best_c == 0xFFFFFFFF) {
|
||||
if(best_c == CHAN_NOT_SPECIFIED) {
|
||||
KdPrint2((PRINT_PREFIX " empty queues\n"));
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -19,7 +19,7 @@ UniataSataConnect(
|
|||
|
||||
KdPrint2((PRINT_PREFIX "UniataSataConnect:\n"));
|
||||
|
||||
if(!deviceExtension->BaseIoAddressSATA_0.Addr) {
|
||||
if(!UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
|
||||
KdPrint2((PRINT_PREFIX " no I/O range\n"));
|
||||
return IDE_STATUS_IDLE;
|
||||
}
|
||||
|
@ -73,7 +73,7 @@ UniataSataPhyEnable(
|
|||
|
||||
KdPrint2((PRINT_PREFIX "UniataSataPhyEnable:\n"));
|
||||
|
||||
if(!deviceExtension->BaseIoAddressSATA_0.Addr) {
|
||||
if(!UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
|
||||
KdPrint2((PRINT_PREFIX " no I/O range\n"));
|
||||
return IDE_STATUS_IDLE;
|
||||
}
|
||||
|
@ -130,7 +130,7 @@ UniataSataClearErr(
|
|||
SATA_SSTATUS_REG SStatus;
|
||||
SATA_SERROR_REG SError;
|
||||
|
||||
if(deviceExtension->BaseIoAddressSATA_0.Addr) {
|
||||
if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
|
||||
//if(ChipFlags & UNIATA_SATA) {
|
||||
|
||||
SStatus.Reg = AtapiReadPort4(chan, IDX_SATA_SStatus);
|
||||
|
@ -172,7 +172,7 @@ UniataSataEvent(
|
|||
UCHAR Status;
|
||||
ULONG ldev = lChannel*2;
|
||||
|
||||
if(!deviceExtension->BaseIoAddressSATA_0.Addr) {
|
||||
if(!UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
@ -189,7 +189,7 @@ UniataSataEvent(
|
|||
break;
|
||||
case UNIATA_SATA_EVENT_DETACH:
|
||||
KdPrint2((PRINT_PREFIX " DISCONNECTED\n"));
|
||||
deviceExtension->lun[ldev].DeviceFlags = 0;
|
||||
UniataForgetDevice(&(deviceExtension->lun[ldev]));
|
||||
return TRUE;
|
||||
break;
|
||||
}
|
||||
|
@ -287,3 +287,127 @@ UniataAhciInit(
|
|||
return TRUE;
|
||||
} // end UniataAhciInit()
|
||||
|
||||
UCHAR
|
||||
UniataAhciStatus(
|
||||
IN PVOID HwDeviceExtension,
|
||||
IN ULONG lChannel
|
||||
)
|
||||
{
|
||||
PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
|
||||
PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
|
||||
ULONG Channel = deviceExtension->Channel + lChannel;
|
||||
ULONG hIS;
|
||||
ULONG CI;
|
||||
AHCI_IS_REG IS;
|
||||
SATA_SSTATUS_REG SStatus;
|
||||
SATA_SERROR_REG SError;
|
||||
ULONG offs = sizeof(IDE_AHCI_REGISTERS) + Channel*sizeof(IDE_AHCI_PORT_REGISTERS);
|
||||
ULONG base;
|
||||
ULONG tag=0;
|
||||
|
||||
KdPrint(("UniataAhciStatus:\n"));
|
||||
|
||||
hIS = AtapiReadPortEx4(NULL, (ULONG)&deviceExtension->BaseIoAHCI_0, IDX_AHCI_IS);
|
||||
KdPrint((" hIS %x\n", hIS));
|
||||
hIS &= (1 << Channel);
|
||||
if(!hIS) {
|
||||
return 0;
|
||||
}
|
||||
base = (ULONG)&deviceExtension->BaseIoAHCI_0 + offs;
|
||||
IS.Reg = AtapiReadPort4(chan, base + IDX_AHCI_P_IS);
|
||||
CI = AtapiReadPort4(chan, base + IDX_AHCI_P_CI);
|
||||
SStatus.Reg = AtapiReadPort4(chan, IDX_SATA_SStatus);
|
||||
SError.Reg = AtapiReadPort4(chan, IDX_SATA_SError);
|
||||
|
||||
/* clear interrupt(s) */
|
||||
AtapiWritePortEx4(NULL, (ULONG)&deviceExtension->BaseIoAHCI_0, IDX_AHCI_IS, hIS);
|
||||
AtapiWritePort4(chan, base + IDX_AHCI_P_IS, IS.Reg);
|
||||
AtapiWritePort4(chan, IDX_SATA_SError, SError.Reg);
|
||||
|
||||
KdPrint((" AHCI: status=%08x sstatus=%08x error=%08x CI=%08x\n",
|
||||
IS.Reg, SStatus.Reg, SError.Reg, CI));
|
||||
|
||||
/* do we have cold connect surprise */
|
||||
if(IS.CPDS) {
|
||||
}
|
||||
|
||||
/* check for and handle connect events */
|
||||
if(IS.PCS) {
|
||||
UniataSataEvent(HwDeviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH);
|
||||
}
|
||||
if(IS.PRCS) {
|
||||
UniataSataEvent(HwDeviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH);
|
||||
}
|
||||
if(CI & (1 << tag)) {
|
||||
return 1;
|
||||
}
|
||||
KdPrint((" AHCI: unexpected\n"));
|
||||
return 2;
|
||||
|
||||
} // end UniataAhciStatus()
|
||||
|
||||
ULONG
|
||||
UniataAhciSetupFIS(
|
||||
IN PHW_DEVICE_EXTENSION deviceExtension,
|
||||
IN ULONG DeviceNumber,
|
||||
IN ULONG lChannel,
|
||||
OUT PUCHAR fis,
|
||||
IN UCHAR command,
|
||||
IN ULONGLONG lba,
|
||||
IN USHORT count,
|
||||
IN USHORT feature,
|
||||
IN ULONG flags
|
||||
)
|
||||
{
|
||||
ULONG ldev = lChannel*2 + DeviceNumber;
|
||||
ULONG i;
|
||||
PUCHAR plba;
|
||||
|
||||
KdPrint2((PRINT_PREFIX " AHCI setup FIS\n" ));
|
||||
i = 0;
|
||||
plba = (PUCHAR)&lba;
|
||||
|
||||
/* translate command into 48bit version */
|
||||
if ((lba >= ATA_MAX_LBA28 || count > 256) &&
|
||||
deviceExtension->lun[ldev].IdentifyData.FeaturesSupport.Address48) {
|
||||
if(AtaCommandFlags[command] & ATA_CMD_FLAG_48supp) {
|
||||
command = AtaCommands48[command];
|
||||
} else {
|
||||
KdPrint2((PRINT_PREFIX " unhandled LBA48 command\n"));
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
fis[i++] = 0x27; /* host to device */
|
||||
fis[i++] = 0x80; /* command FIS (note PM goes here) */
|
||||
fis[i++] = command;
|
||||
fis[i++] = (UCHAR)feature;
|
||||
|
||||
fis[i++] = plba[0];
|
||||
fis[i++] = plba[1];
|
||||
fis[i++] = plba[2];
|
||||
fis[i] = IDE_USE_LBA | (DeviceNumber ? IDE_DRIVE_2 : IDE_DRIVE_1);
|
||||
if ((lba >= ATA_MAX_LBA28 || count > 256) &&
|
||||
deviceExtension->lun[ldev].IdentifyData.FeaturesSupport.Address48) {
|
||||
i++;
|
||||
} else {
|
||||
fis[i++] |= (plba[3] >> 24) & 0x0f;
|
||||
}
|
||||
|
||||
fis[i++] = plba[3];
|
||||
fis[i++] = plba[4];
|
||||
fis[i++] = plba[5];
|
||||
fis[i++] = (UCHAR)(feature>>8) & 0xff;
|
||||
|
||||
fis[i++] = (UCHAR)count & 0xff;
|
||||
fis[i++] = (UCHAR)(count>>8) & 0xff;
|
||||
fis[i++] = 0x00;
|
||||
fis[i++] = IDE_DC_A_4BIT;
|
||||
|
||||
fis[i++] = 0x00;
|
||||
fis[i++] = 0x00;
|
||||
fis[i++] = 0x00;
|
||||
fis[i++] = 0x00;
|
||||
return i;
|
||||
} // end UniataAhciSetupFIS()
|
||||
|
||||
|
|
|
@ -33,4 +33,33 @@ UniataSataEvent(
|
|||
IN ULONG Action
|
||||
);
|
||||
|
||||
#define UniataIsSATARangeAvailable(deviceExtension, lChannel) \
|
||||
((deviceExtension->BaseIoAddressSATA_0.Addr || \
|
||||
deviceExtension->BaseIoAHCI_0.Addr) && \
|
||||
(deviceExtension->chan[lChannel].RegTranslation[IDX_SATA_SStatus].Addr))
|
||||
|
||||
BOOLEAN
|
||||
UniataAhciInit(
|
||||
IN PVOID HwDeviceExtension
|
||||
);
|
||||
|
||||
UCHAR
|
||||
UniataAhciStatus(
|
||||
IN PVOID HwDeviceExtension,
|
||||
IN ULONG lChannel
|
||||
);
|
||||
|
||||
ULONG
|
||||
UniataAhciSetupFIS(
|
||||
IN PHW_DEVICE_EXTENSION deviceExtension,
|
||||
IN ULONG DeviceNumber,
|
||||
IN ULONG lChannel,
|
||||
OUT PUCHAR fis,
|
||||
IN UCHAR command,
|
||||
IN ULONGLONG lba,
|
||||
IN USHORT count,
|
||||
IN USHORT feature,
|
||||
IN ULONG flags
|
||||
);
|
||||
|
||||
#endif //__UNIATA_SATA__H__
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
#include "uniata_ver.h"
|
||||
|
||||
#define VERSION 0,38,2,0
|
||||
#define VERSION 0,39,6,0
|
||||
#define VERSION_STR "0." UNIATA_VER_STR
|
||||
|
||||
#define REACTOS_FILETYPE VFT_DRV
|
||||
|
|
|
@ -1,16 +1,20 @@
|
|||
#ifndef __NTDDK_EX__H__
|
||||
#define __NTDDK_EX__H__
|
||||
|
||||
#ifndef __REACTOS__
|
||||
#undef ASSERT
|
||||
#define ASSERT
|
||||
#else
|
||||
#undef ASSERT
|
||||
#define ASSERT //(x) if (!(x)) {RtlAssert("#x",__FILE__,__LINE__, ""); }
|
||||
#endif //__REACTOS__
|
||||
|
||||
typedef enum _SYSTEM_INFORMATION_CLASS
|
||||
{
|
||||
typedef enum _SYSTEM_INFORMATION_CLASS {
|
||||
SystemBasicInformation,
|
||||
SystemProcessorInformation,
|
||||
SystemPerformanceInformation,
|
||||
SystemTimeOfDayInformation,
|
||||
SystemPathInformation, /// Obsolete: Use KUSER_SHARED_DATA
|
||||
SystemPathInformation,
|
||||
SystemProcessInformation,
|
||||
SystemCallCountInformation,
|
||||
SystemDeviceInformation,
|
||||
|
@ -36,9 +40,15 @@ typedef enum _SYSTEM_INFORMATION_CLASS
|
|||
SystemUnloadGdiDriverInformation,
|
||||
SystemTimeAdjustmentInformation,
|
||||
SystemSummaryMemoryInformation,
|
||||
#ifndef __REACTOS__
|
||||
SystemNextEventIdInformation,
|
||||
SystemEventIdsInformation,
|
||||
SystemCrashDumpInformation,
|
||||
#else
|
||||
SystemMirrorMemoryInformation,
|
||||
SystemPerformanceTraceInformation,
|
||||
SystemObsolete0,
|
||||
#endif
|
||||
SystemExceptionInformation,
|
||||
SystemCrashDumpStateInformation,
|
||||
SystemKernelDebuggerInformation,
|
||||
|
@ -48,10 +58,17 @@ typedef enum _SYSTEM_INFORMATION_CLASS
|
|||
SystemPrioritySeperation,
|
||||
SystemPlugPlayBusInformation,
|
||||
SystemDockInformation,
|
||||
#ifdef __REACTOS__
|
||||
SystemPowerInformationNative,
|
||||
#elif defined IRP_MN_START_DEVICE
|
||||
SystemPowerInformationInfo,
|
||||
#else
|
||||
SystemPowerInformation,
|
||||
#endif
|
||||
SystemProcessorSpeedInformation,
|
||||
SystemCurrentTimeZoneInformation,
|
||||
SystemLookasideInformation,
|
||||
#ifdef __REACTOS__
|
||||
SystemTimeSlipNotification,
|
||||
SystemSessionCreate,
|
||||
SystemSessionDetach,
|
||||
|
@ -105,8 +122,10 @@ typedef enum _SYSTEM_INFORMATION_CLASS
|
|||
SystemPrefetchPathInformation,
|
||||
SystemVerifierFaultsInformation,
|
||||
MaxSystemInfoClass,
|
||||
#endif //__REACTOS__
|
||||
} SYSTEM_INFORMATION_CLASS;
|
||||
|
||||
|
||||
NTSYSAPI
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
|
@ -161,7 +180,9 @@ typedef struct _SYSTEM_MODULE_INFORMATION
|
|||
} SYSTEM_MODULE_INFORMATION, *PSYSTEM_MODULE_INFORMATION;
|
||||
|
||||
typedef unsigned short WORD;
|
||||
//typedef unsigned int BOOL;
|
||||
#ifndef __REACTOS__
|
||||
typedef unsigned int BOOL;
|
||||
#endif //__REACTOS__
|
||||
typedef unsigned long DWORD;
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
|
|
|
@ -423,39 +423,39 @@ typedef struct _SCSI_WMI_REQUEST_BLOCK {
|
|||
//
|
||||
|
||||
typedef
|
||||
BOOLEAN DDKAPI
|
||||
(*PHW_INITIALIZE) (
|
||||
BOOLEAN
|
||||
(DDKAPI *PHW_INITIALIZE) (
|
||||
IN PVOID DeviceExtension
|
||||
);
|
||||
|
||||
typedef
|
||||
BOOLEAN DDKAPI
|
||||
(*PHW_STARTIO) (
|
||||
BOOLEAN
|
||||
(DDKAPI *PHW_STARTIO) (
|
||||
IN PVOID DeviceExtension,
|
||||
IN PSCSI_REQUEST_BLOCK Srb
|
||||
);
|
||||
|
||||
typedef
|
||||
BOOLEAN DDKAPI
|
||||
(*PHW_INTERRUPT) (
|
||||
BOOLEAN
|
||||
(DDKAPI *PHW_INTERRUPT) (
|
||||
IN PVOID DeviceExtension
|
||||
);
|
||||
|
||||
typedef
|
||||
VOID DDKAPI
|
||||
(*PHW_TIMER) (
|
||||
VOID
|
||||
(DDKAPI *PHW_TIMER) (
|
||||
IN PVOID DeviceExtension
|
||||
);
|
||||
|
||||
typedef
|
||||
VOID DDKAPI
|
||||
(*PHW_DMA_STARTED) (
|
||||
VOID
|
||||
(DDKAPI *PHW_DMA_STARTED) (
|
||||
IN PVOID DeviceExtension
|
||||
);
|
||||
|
||||
typedef
|
||||
ULONG DDKAPI
|
||||
(*PHW_FIND_ADAPTER) (
|
||||
ULONG
|
||||
(DDKAPI *PHW_FIND_ADAPTER) (
|
||||
IN PVOID DeviceExtension,
|
||||
IN PVOID HwContext,
|
||||
IN PVOID BusInformation,
|
||||
|
@ -465,23 +465,23 @@ ULONG DDKAPI
|
|||
);
|
||||
|
||||
typedef
|
||||
BOOLEAN DDKAPI
|
||||
(*PHW_RESET_BUS) (
|
||||
BOOLEAN
|
||||
(DDKAPI *PHW_RESET_BUS) (
|
||||
IN PVOID DeviceExtension,
|
||||
IN ULONG PathId
|
||||
);
|
||||
|
||||
typedef
|
||||
BOOLEAN DDKAPI
|
||||
(*PHW_ADAPTER_STATE) (
|
||||
BOOLEAN
|
||||
(DDKAPI *PHW_ADAPTER_STATE) (
|
||||
IN PVOID DeviceExtension,
|
||||
IN PVOID Context,
|
||||
IN BOOLEAN SaveState
|
||||
);
|
||||
|
||||
typedef
|
||||
SCSI_ADAPTER_CONTROL_STATUS DDKAPI
|
||||
(*PHW_ADAPTER_CONTROL) (
|
||||
SCSI_ADAPTER_CONTROL_STATUS
|
||||
(DDKAPI *PHW_ADAPTER_CONTROL) (
|
||||
IN PVOID DeviceExtension,
|
||||
IN SCSI_ADAPTER_CONTROL_TYPE ControlType,
|
||||
IN PVOID Parameters
|
||||
|
|
|
@ -19,7 +19,17 @@ extern "C" {
|
|||
|
||||
#include "id_queue.h"
|
||||
|
||||
#ifdef ExAllocatePool
|
||||
#undef ExAllocatePool
|
||||
#endif
|
||||
|
||||
#define TAG(A, B, C, D) (ULONG)(((A)<<0) + ((B)<<8) + ((C)<<16) + ((D)<<24))
|
||||
#define TAG_UNIATA TAG('a', 't', 'a', 'U')
|
||||
|
||||
#define ExAllocatePool(a,b) ExAllocatePoolWithTag(a,b,TAG_UNIATA)
|
||||
|
||||
#endif //UNIATA_CORE
|
||||
|
||||
#include "badblock.h"
|
||||
|
||||
|
||||
|
|
|
@ -50,6 +50,7 @@ extern "C" {
|
|||
|
||||
#define MAX_QUEUE_STAT 8
|
||||
|
||||
#define UNIATA_COMM_PORT_VENDOR_STR "UNIATA " "Management Port " UNIATA_VER_STR
|
||||
|
||||
#ifndef UNIATA_CORE
|
||||
|
||||
|
@ -65,6 +66,11 @@ extern "C" {
|
|||
|
||||
typedef struct _ADDREMOVEDEV {
|
||||
ULONG WaitForPhysicalLink; // us
|
||||
ULONG Flags;
|
||||
|
||||
#define UNIATA_REMOVE_FLAGS_HIDE 0x01
|
||||
#define UNIATA_ADD_FLAGS_UNHIDE 0x01
|
||||
|
||||
} ADDREMOVEDEV, *PADDREMOVEDEV;
|
||||
|
||||
typedef struct _SETTRANSFERMODE {
|
||||
|
@ -127,11 +133,49 @@ typedef struct _ADAPTERINFO {
|
|||
ULONG NumberChannels;
|
||||
|
||||
BOOLEAN ChanInfoValid;
|
||||
CHAR Reserved[3];
|
||||
|
||||
ULONG AdapterInterfaceType;
|
||||
|
||||
CHANINFO Chan[AHCI_MAX_PORT];
|
||||
|
||||
} ADAPTERINFO, *PADAPTERINFO;
|
||||
|
||||
#ifdef USER_MODE
|
||||
|
||||
typedef enum _INTERFACE_TYPE {
|
||||
InterfaceTypeUndefined = -1,
|
||||
Internal,
|
||||
Isa,
|
||||
Eisa,
|
||||
MicroChannel,
|
||||
TurboChannel,
|
||||
PCIBus,
|
||||
VMEBus,
|
||||
NuBus,
|
||||
PCMCIABus,
|
||||
CBus,
|
||||
MPIBus,
|
||||
MPSABus,
|
||||
ProcessorInternal,
|
||||
InternalPowerBus,
|
||||
PNPISABus,
|
||||
MaximumInterfaceType
|
||||
} INTERFACE_TYPE, *PINTERFACE_TYPE;
|
||||
|
||||
typedef struct _PCI_SLOT_NUMBER {
|
||||
union {
|
||||
struct {
|
||||
ULONG DeviceNumber:5;
|
||||
ULONG FunctionNumber:3;
|
||||
ULONG Reserved:24;
|
||||
} bits;
|
||||
ULONG AsULONG;
|
||||
} u;
|
||||
} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef ATA_FLAGS_DRDY_REQUIRED
|
||||
|
||||
//The ATA_PASS_THROUGH_DIRECT structure is used in conjunction with an IOCTL_ATA_PASS_THROUGH_DIRECT request to instruct the port driver to send an embedded ATA command to the target device.
|
||||
|
@ -179,22 +223,28 @@ typedef struct _IDEREGS_EX {
|
|||
#define UNIATA_SPTI_EX_LBA48 0x08
|
||||
#define UNIATA_SPTI_EX_SPEC_TO 0x10
|
||||
//#define UNIATA_SPTI_EX_FREEZE_TO 0x20 // do not reset device on timeout and keep interrupts disabled
|
||||
#define UNIATA_SPTI_EX_USE_DMA 0x20 // Force DMA transfer mode
|
||||
|
||||
UCHAR bFeaturesRegH; // feature (high part for LBA48 mode)
|
||||
UCHAR bSectorCountRegH; // IDE sector count register (high part for LBA48 mode)
|
||||
UCHAR bSectorNumberRegH; // IDE sector number register (high part for LBA48 mode)
|
||||
UCHAR bCylLowRegH; // IDE low order cylinder value (high part for LBA48 mode)
|
||||
UCHAR bCylHighRegH; // IDE high order cylinder value (high part for LBA48 mode)
|
||||
UCHAR bReserved; // 0
|
||||
UCHAR bReserved2; // 0
|
||||
} IDEREGS_EX, *PIDEREGS_EX, *LPIDEREGS_EX;
|
||||
|
||||
typedef struct _UNIATA_REG_IO {
|
||||
USHORT RegIDX;
|
||||
UCHAR RegSz:2; // 0=1, 1=2, 2=4, 3=2+2 (for lba48)
|
||||
UCHAR RegSz:3; // 0=1, 1=2, 2=4, 3=1+1 (for lba48) 4=2+2 (for lba48)
|
||||
UCHAR InOut:1; // 0=in, 1=out
|
||||
UCHAR Reserved:5;
|
||||
UCHAR Reserved:4;
|
||||
UCHAR Reserved1;
|
||||
ULONG Data;
|
||||
union {
|
||||
ULONG Data;
|
||||
ULONG d32;
|
||||
USHORT d16[2];
|
||||
USHORT d8[2];
|
||||
};
|
||||
} UNIATA_REG_IO, *PUNIATA_REG_IO;
|
||||
|
||||
typedef struct _UNIATA_REG_IO_HDR {
|
||||
|
|
|
@ -2,7 +2,6 @@
|
|||
<!DOCTYPE module SYSTEM "../../../../tools/rbuild/project.dtd">
|
||||
<module name="uniata" type="kernelmodedriver" installbase="system32/drivers" allowwarnings="true" installname="uniata.sys">
|
||||
<bootstrap installbase="$(CDOUTPUT)" />
|
||||
<define name="_DEBUG" />
|
||||
<include base="uniata">.</include>
|
||||
<include base="uniata">inc</include>
|
||||
<library>ntoskrnl</library>
|
||||
|
|
|
@ -1,2 +1,6 @@
|
|||
|
||||
#define UNIATA_VER_STR "38c2"
|
||||
#define UNIATA_VER_STR "39f"
|
||||
#define UNIATA_VER_DOT 0.39.6.0
|
||||
#define UNIATA_VER_DOT_COMMA 0,39,6,0
|
||||
#define UNIATA_VER_DOT_STR "0.39.6.0"
|
||||
#define UNIATA_VER_YEAR 2007
|
||||
#define UNIATA_VER_YEAR_STR "2007"
|
||||
|
|
Loading…
Reference in a new issue