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[SERIAL]
Comment the different defines. svn path=/trunk/; revision=57775
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Hermès Bélusca-Maïto
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dfa74be23e
commit
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@ -10,60 +10,93 @@
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#pragma once
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/* Note: These definitions are the internal definitions used by Microsoft serial
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driver (see src/kernel/serial/serial.h in WDK source code). Linux uses its own,
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as do most other OS.
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/* Note: These definitions are the internal definitions used by Microsoft
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Serial Driver (see src/serial/serial/serial.h in WDK source code).
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Linux uses its own, as do most other OS.
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*/
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/* Baud master clock */
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// #define BAUD_CLOCK 1843200
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// #define CLOCKS_PER_BIT 16
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#define CLOCK_RATE 115200 // UART clock rate == BAUD_CLOCK / CLOCKS_PER_BIT
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// Define the spacing between registers.
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#if !defined(SERIAL_REGISTER_STRIDE)
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#define SERIAL_REGISTER_STRIDE 1
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#endif
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#define RECEIVE_BUFFER_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define TRANSMIT_HOLDING_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define INTERRUPT_ENABLE_REGISTER ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
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#define INTERRUPT_IDENT_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
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#define FIFO_CONTROL_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
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#define LINE_CONTROL_REGISTER ((ULONG)((0x03)*SERIAL_REGISTER_STRIDE))
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#define MODEM_CONTROL_REGISTER ((ULONG)((0x04)*SERIAL_REGISTER_STRIDE))
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#define LINE_STATUS_REGISTER ((ULONG)((0x05)*SERIAL_REGISTER_STRIDE))
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#define MODEM_STATUS_REGISTER ((ULONG)((0x06)*SERIAL_REGISTER_STRIDE))
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#define DIVISOR_LATCH_LSB ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define DIVISOR_LATCH_MSB ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
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#define SERIAL_REGISTER_SPAN ((ULONG)(7*SERIAL_REGISTER_STRIDE))
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#define SERIAL_STATUS_LENGTH ((ULONG)(1*SERIAL_REGISTER_STRIDE))
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/*
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* Offsets of the various registers, from the base register address.
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*/
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#define RECEIVE_BUFFER_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define TRANSMIT_HOLDING_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define INTERRUPT_ENABLE_REGISTER ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
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#define INTERRUPT_IDENT_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
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#define FIFO_CONTROL_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
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#define LINE_CONTROL_REGISTER ((ULONG)((0x03)*SERIAL_REGISTER_STRIDE))
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#define MODEM_CONTROL_REGISTER ((ULONG)((0x04)*SERIAL_REGISTER_STRIDE))
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#define LINE_STATUS_REGISTER ((ULONG)((0x05)*SERIAL_REGISTER_STRIDE))
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#define MODEM_STATUS_REGISTER ((ULONG)((0x06)*SERIAL_REGISTER_STRIDE))
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#define SCRATCH_REGISTER ((ULONG)((0x07)*SERIAL_REGISTER_STRIDE))
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#define SERIAL_DATA_LENGTH_5 0x00
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#define SERIAL_DATA_LENGTH_6 0x01
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#define SERIAL_DATA_LENGTH_7 0x02
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#define SERIAL_DATA_LENGTH_8 0x03
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#define DIVISOR_LATCH_LSB ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define DIVISOR_LATCH_MSB ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
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#define SERIAL_REGISTER_LENGTH ((ULONG)(7*SERIAL_REGISTER_STRIDE))
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#define SERIAL_IER_RDA 0x01
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#define SERIAL_IER_THR 0x02
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#define SERIAL_IER_RLS 0x04
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#define SERIAL_IER_MS 0x08
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// Length of the interrupt status register.
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#define SERIAL_STATUS_LENGTH ((ULONG)(1*SERIAL_REGISTER_STRIDE))
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/*
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* Start, Data, Parity, Stop number of data bits
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* transmitted in the Serial Data Unit.
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*/
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#define SERIAL_DATA_LENGTH_5 0x00
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#define SERIAL_DATA_LENGTH_6 0x01
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#define SERIAL_DATA_LENGTH_7 0x02
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#define SERIAL_DATA_LENGTH_8 0x03
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/*
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* Masks defining the interrupts that can be enabled or disabled.
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*/
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#define SERIAL_IER_RDA 0x01 // New incoming data available.
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#define SERIAL_IER_THR 0x02 // Space available for another octet in the transmitter.
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#define SERIAL_IER_RLS 0x04 // Error occurred with incoming data.
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#define SERIAL_IER_MS 0x08 // Change occurred in the modem control line.
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/*
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* Interrupt Identification Register masks.
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*/
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#define SERIAL_IIR_RLS 0x06
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#define SERIAL_IIR_RDA 0x04
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#define SERIAL_IIR_CTI 0x0c
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#define SERIAL_IIR_THR 0x02
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#define SERIAL_IIR_MS 0x00
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#define SERIAL_IIR_FIFOS_ENABLED 0xc0
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#define SERIAL_IIR_FIFOS_ENABLED 0xc0
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#define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01
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#define SERIAL_IIR_MUST_BE_ZERO 0x30
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#define SERIAL_IIR_MUST_BE_ZERO 0x30
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#define SERIAL_FCR_ENABLE ((UCHAR)0x01)
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#define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02)
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#define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04)
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/*
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* Fifo Control Register accessing masks.
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*/
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#define SERIAL_FCR_DISABLE ((UCHAR)0x00)
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#define SERIAL_FCR_ENABLE ((UCHAR)0x01)
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#define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02)
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#define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04)
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#define SERIAL_1_BYTE_HIGH_WATER ((UCHAR)0x00)
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#define SERIAL_4_BYTE_HIGH_WATER ((UCHAR)0x40)
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#define SERIAL_8_BYTE_HIGH_WATER ((UCHAR)0x80)
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#define SERIAL_14_BYTE_HIGH_WATER ((UCHAR)0xc0)
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#define SERIAL_1_BYTE_HIGH_WATER ((UCHAR)0x00)
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#define SERIAL_4_BYTE_HIGH_WATER ((UCHAR)0x40)
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#define SERIAL_8_BYTE_HIGH_WATER ((UCHAR)0x80)
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#define SERIAL_14_BYTE_HIGH_WATER ((UCHAR)0xc0)
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#define SERIAL_LCR_DLAB 0x80
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#define SERIAL_LCR_BREAK 0x40
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/*
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* Line Control Register accessing masks.
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*/
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#define SERIAL_LCR_DLAB 0x80 // Divisor Latch Access Bit
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#define SERIAL_LCR_BREAK 0x40 // Send a break
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/*
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* Line Control Register setting bits.
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*/
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#define SERIAL_5_DATA ((UCHAR)0x00)
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#define SERIAL_6_DATA ((UCHAR)0x01)
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#define SERIAL_7_DATA ((UCHAR)0x02)
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@ -82,27 +115,38 @@
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#define SERIAL_SPACE_PARITY ((UCHAR)0x38)
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#define SERIAL_PARITY_MASK ((UCHAR)0x38)
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#define SERIAL_MCR_DTR 0x01
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#define SERIAL_MCR_RTS 0x02
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#define SERIAL_MCR_OUT1 0x04
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#define SERIAL_MCR_OUT2 0x08
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#define SERIAL_MCR_LOOP 0x10
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#define SERIAL_MCR_TL16C550CAFE 0x20
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/*
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* Modem Control Register accessing masks.
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*/
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#define SERIAL_MCR_DTR 0x01 // Controls the Data Terminal Ready line
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#define SERIAL_MCR_RTS 0x02 // Controls the Ready To Send line
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#define SERIAL_MCR_OUT1 0x04 // General purpose output
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#define SERIAL_MCR_OUT2 0x08 // General purpose output
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#define SERIAL_MCR_LOOP 0x10 // Controls the loopback testing mode
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#define SERIAL_MCR_TL16C550CAFE 0x20 // Enables Auto Flow Control on a TI TL16C550C
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#define SERIAL_LSR_DR 0x01
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#define SERIAL_LSR_OE 0x02
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#define SERIAL_LSR_PE 0x04
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#define SERIAL_LSR_FE 0x08
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#define SERIAL_LSR_BI 0x10
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#define SERIAL_LSR_THRE 0x20
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#define SERIAL_LSR_TEMT 0x40
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#define SERIAL_LSR_FIFOERR 0x80
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/*
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* Line Status Register accessing masks.
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*/
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#define SERIAL_LSR_DR 0x01 // Data Ready indicator
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#define SERIAL_LSR_OE 0x02 // Overrun indicator
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#define SERIAL_LSR_PE 0x04 // Parity Error indicator
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#define SERIAL_LSR_FE 0x08 // Framing Error indicator
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#define SERIAL_LSR_BI 0x10 // Break Interrupt indicator
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#define SERIAL_LSR_THRE 0x20 // Transmit Holding Register Empty indicator
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#define SERIAL_LSR_TEMT 0x40 // Transmitter Empty indicator
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#define SERIAL_LSR_FIFOERR 0x80 // Fifo Error indicator
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#define SERIAL_MSR_DCTS 0x01
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#define SERIAL_MSR_DDSR 0x02
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#define SERIAL_MSR_TERI 0x04
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#define SERIAL_MSR_DDCD 0x08
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#define SERIAL_MSR_CTS 0x10
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#define SERIAL_MSR_DSR 0x20
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#define SERIAL_MSR_RI 0x40
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#define SERIAL_MSR_DCD 0x80
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/*
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* Modem Status Register accessing masks.
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*/
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#define SERIAL_MSR_DCTS 0x01 // Delta Clear To Send
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#define SERIAL_MSR_DDSR 0x02 // Delta Data Set Ready
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#define SERIAL_MSR_TERI 0x04 // Trailing Edge Ring Indicator
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#define SERIAL_MSR_DDCD 0x08 // Delta Data Carrier Detect
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#define SERIAL_MSR_CTS 0x10 // Clear To Send
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#define SERIAL_MSR_DSR 0x20 // Data Set Ready
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#define SERIAL_MSR_RI 0x40 // Ring Indicator
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#define SERIAL_MSR_DCD 0x80 // Data Carrier Detect
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/* EOF */
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