mirror of
https://github.com/reactos/reactos.git
synced 2025-07-31 10:11:48 +00:00
[HALX86] Deduplicate initialization of legacy PICs and remove EOI in I/O APIC initialization, which causes an unexpected interrupt
This commit is contained in:
parent
0fdb5d9b63
commit
361b6e39e3
5 changed files with 96 additions and 136 deletions
|
@ -254,74 +254,6 @@ HalpSendEOI(VOID)
|
|||
ApicSendEOI();
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
HalpInitializeLegacyPIC(VOID)
|
||||
{
|
||||
I8259_ICW1 Icw1;
|
||||
I8259_ICW2 Icw2;
|
||||
I8259_ICW3 Icw3;
|
||||
I8259_ICW4 Icw4;
|
||||
|
||||
/* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */
|
||||
Icw1.NeedIcw4 = TRUE;
|
||||
Icw1.OperatingMode = Cascade;
|
||||
Icw1.Interval = Interval8;
|
||||
Icw1.InterruptMode = EdgeTriggered;
|
||||
Icw1.Init = TRUE;
|
||||
Icw1.InterruptVectorAddress = 0;
|
||||
__outbyte(PIC1_CONTROL_PORT, Icw1.Bits);
|
||||
|
||||
/* ICW2 - interrupt vector offset */
|
||||
Icw2.Bits = PRIMARY_VECTOR_BASE;
|
||||
__outbyte(PIC1_DATA_PORT, Icw2.Bits);
|
||||
|
||||
/* Connect slave to IRQ 2 */
|
||||
Icw3.Bits = 0;
|
||||
Icw3.SlaveIrq2 = TRUE;
|
||||
__outbyte(PIC1_DATA_PORT, Icw3.Bits);
|
||||
|
||||
/* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
|
||||
Icw4.SystemMode = New8086Mode;
|
||||
Icw4.EoiMode = NormalEoi;
|
||||
Icw4.BufferedMode = NonBuffered;
|
||||
Icw4.SpecialFullyNestedMode = FALSE;
|
||||
Icw4.Reserved = 0;
|
||||
__outbyte(PIC1_DATA_PORT, Icw4.Bits);
|
||||
|
||||
/* Mask all interrupts */
|
||||
__outbyte(PIC1_DATA_PORT, 0xFF);
|
||||
|
||||
/* Initialize ICW1 for slave, interval 8, edge-triggered mode with ICW4 */
|
||||
Icw1.NeedIcw4 = TRUE;
|
||||
Icw1.InterruptMode = EdgeTriggered;
|
||||
Icw1.OperatingMode = Cascade;
|
||||
Icw1.Interval = Interval8;
|
||||
Icw1.Init = TRUE;
|
||||
Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */
|
||||
__outbyte(PIC2_CONTROL_PORT, Icw1.Bits);
|
||||
|
||||
/* Set interrupt vector base */
|
||||
Icw2.Bits = PRIMARY_VECTOR_BASE + 8;
|
||||
__outbyte(PIC2_DATA_PORT, Icw2.Bits);
|
||||
|
||||
/* Slave ID */
|
||||
Icw3.Bits = 0;
|
||||
Icw3.SlaveId = 2;
|
||||
__outbyte(PIC2_DATA_PORT, Icw3.Bits);
|
||||
|
||||
/* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
|
||||
Icw4.SystemMode = New8086Mode;
|
||||
Icw4.EoiMode = NormalEoi;
|
||||
Icw4.BufferedMode = NonBuffered;
|
||||
Icw4.SpecialFullyNestedMode = FALSE;
|
||||
Icw4.Reserved = 0;
|
||||
__outbyte(PIC2_DATA_PORT, Icw4.Bits);
|
||||
|
||||
/* Mask all interrupts */
|
||||
__outbyte(PIC2_DATA_PORT, 0xFF);
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
ApicInitializeLocalApic(ULONG Cpu)
|
||||
|
@ -506,8 +438,6 @@ ApicInitializeIOApic(VOID)
|
|||
ReDirReg.Mask = 0;
|
||||
ReDirReg.Destination = ApicRead(APIC_ID);
|
||||
IOApicWrite(IOAPIC_REDTBL + 2 * APIC_CLOCK_INDEX, ReDirReg.Long0);
|
||||
|
||||
ApicSendEOI();
|
||||
}
|
||||
|
||||
VOID
|
||||
|
@ -521,7 +451,7 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
|
|||
_disable();
|
||||
|
||||
/* Initialize and mask the PIC */
|
||||
HalpInitializeLegacyPIC();
|
||||
HalpInitializeLegacyPICs();
|
||||
|
||||
/* Initialize the I/O APIC */
|
||||
ApicInitializeIOApic();
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue