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[HALX86] Add missing \n to DPRINT() calls (#5993)

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And promote some DPRINT() to DPRINT1().
This commit is contained in:
Serge Gautherie 2023-11-19 19:44:46 +01:00 committed by GitHub
parent d27ec14822
commit 2cc7eeb939
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GPG key ID: 4AEE18F83AFDEB23
3 changed files with 38 additions and 39 deletions
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21
hal/halx86/acpi/halacpi.c
View file

@ -779,7 +779,7 @@ HaliAcpiTimerInit(IN ULONG TimerPort,
/* Get the data from the FADT */ /* Get the data from the FADT */
TimerPort = HalpFixedAcpiDescTable.pm_tmr_blk_io_port; TimerPort = HalpFixedAcpiDescTable.pm_tmr_blk_io_port;
TimerValExt = HalpFixedAcpiDescTable.flags & ACPI_TMR_VAL_EXT; TimerValExt = HalpFixedAcpiDescTable.flags & ACPI_TMR_VAL_EXT;
DPRINT1("ACPI Timer at: %Xh (EXT: %d)\n", TimerPort, TimerValExt); DPRINT1("ACPI Timer at: %lXh (EXT: %lu)\n", TimerPort, TimerValExt);
} }
/* FIXME: Now proceed to the timer initialization */ /* FIXME: Now proceed to the timer initialization */
@ -888,14 +888,14 @@ HalpSetupAcpiPhase0(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
if ((CachedTable->Header.Signature == RSDT_SIGNATURE) || if ((CachedTable->Header.Signature == RSDT_SIGNATURE) ||
(CachedTable->Header.Signature == XSDT_SIGNATURE)) (CachedTable->Header.Signature == XSDT_SIGNATURE))
{ {
DPRINT1("ACPI %d.0 Detected. Tables: ", (CachedTable->Header.Revision + 1)); DPRINT1("ACPI %u.0 Detected. Tables:", CachedTable->Header.Revision + 1);
} }
DbgPrint("[%c%c%c%c] ", DbgPrint(" [%c%c%c%c]",
(CachedTable->Header.Signature & 0xFF), CachedTable->Header.Signature & 0x000000FF,
(CachedTable->Header.Signature & 0xFF00) >> 8, (CachedTable->Header.Signature & 0x0000FF00) >> 8,
(CachedTable->Header.Signature & 0xFF0000) >> 16, (CachedTable->Header.Signature & 0x00FF0000) >> 16,
(CachedTable->Header.Signature & 0xFF000000) >> 24); (CachedTable->Header.Signature & 0xFF000000) >> 24);
/* Keep going */ /* Keep going */
NextEntry = NextEntry->Flink; NextEntry = NextEntry->Flink;
@ -1016,18 +1016,19 @@ NTAPI
HalpQueryAcpiResourceRequirements(OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements) HalpQueryAcpiResourceRequirements(OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements)
{ {
PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList; PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList;
ULONG Count = 0, ListSize; ULONG Count, ListSize;
NTSTATUS Status; NTSTATUS Status;
PAGED_CODE(); PAGED_CODE();
/* Get ACPI resources */ /* Get ACPI resources */
HalpAcpiDetectResourceListSize(&Count); HalpAcpiDetectResourceListSize(&Count);
DPRINT("Resource count: %d\n", Count); DPRINT("Resource count: %lu\n", Count);
/* Compute size of the list and allocate it */ /* Compute size of the list and allocate it */
ListSize = FIELD_OFFSET(IO_RESOURCE_REQUIREMENTS_LIST, List[0].Descriptors) + ListSize = FIELD_OFFSET(IO_RESOURCE_REQUIREMENTS_LIST, List[0].Descriptors) +
(Count * sizeof(IO_RESOURCE_DESCRIPTOR)); (Count * sizeof(IO_RESOURCE_DESCRIPTOR));
DPRINT("Resource list size: %d\n", ListSize); DPRINT("Resource list size: %lu\n", ListSize);
RequirementsList = ExAllocatePoolWithTag(PagedPool, ListSize, TAG_HAL); RequirementsList = ExAllocatePoolWithTag(PagedPool, ListSize, TAG_HAL);
if (RequirementsList) if (RequirementsList)
{ {

9
hal/halx86/generic/x86bios.c
View file

@ -138,7 +138,8 @@ HalInitializeBios(
x86BiosMemoryMapping = MmGetSystemAddressForMdlSafe(Mdl, HighPagePriority); x86BiosMemoryMapping = MmGetSystemAddressForMdlSafe(Mdl, HighPagePriority);
ASSERT(x86BiosMemoryMapping); ASSERT(x86BiosMemoryMapping);
DPRINT1("memory: %p, %p\n", *(PVOID*)x86BiosMemoryMapping, *(PVOID*)(x86BiosMemoryMapping + 8)); DPRINT1("*x86BiosMemoryMapping: %p, %p\n",
*(PVOID*)x86BiosMemoryMapping, *(PVOID*)(x86BiosMemoryMapping + 8));
//DbgDumpPage(x86BiosMemoryMapping, 0xc351); //DbgDumpPage(x86BiosMemoryMapping, 0xc351);
x86BiosIsInitialized = TRUE; x86BiosIsInitialized = TRUE;
@ -271,7 +272,7 @@ x86MemRead(
else else
{ {
RtlFillMemory(Buffer, Size, 0xCC); RtlFillMemory(Buffer, Size, 0xCC);
DPRINT1("x86MemRead: invalid read at 0x%lx (size 0x%lx)", Address, Size); DPRINT1("x86MemRead: invalid read at 0x%lx (size 0x%lx)\n", Address, Size);
} }
} }
@ -291,7 +292,7 @@ x86MemWrite(
} }
else else
{ {
DPRINT1("x86MemWrite: invalid write at 0x%lx (size 0x%lx)", Address, Size); DPRINT1("x86MemWrite: invalid write at 0x%lx (size 0x%lx)\n", Address, Size);
} }
} }
@ -465,7 +466,7 @@ x86BiosCall(
/* Make sure we haven't left the allowed memory range */ /* Make sure we haven't left the allowed memory range */
if (FlatIp >= 0x100000) if (FlatIp >= 0x100000)
{ {
DPRINT1("x86BiosCall: invalid IP (0x%lx) during BIOS execution", FlatIp); DPRINT1("x86BiosCall: invalid IP (0x%lx) during BIOS execution\n", FlatIp);
return FALSE; return FALSE;
} }

47
hal/halx86/mp/ioapic.c
View file

@ -70,7 +70,7 @@ static ULONG EISA_ELCR_Read(ULONG irq)
PUCHAR port = (PUCHAR)(0x4d0 + (irq >> 3)); PUCHAR port = (PUCHAR)(0x4d0 + (irq >> 3));
return (READ_PORT_UCHAR(port) >> (irq & 7)) & 1; return (READ_PORT_UCHAR(port) >> (irq & 7)) & 1;
} }
DPRINT("Broken MPtable reports ISA irq %d\n", irq); DPRINT1("Broken MPtable reports ISA irq %lu\n", irq);
return 0; return 0;
} }
@ -106,7 +106,7 @@ IRQPolarity(ULONG idx)
break; break;
default: default:
DPRINT("Broken BIOS!!\n"); DPRINT1("Broken BIOS\n");
polarity = 1; polarity = 1;
} }
} }
@ -117,7 +117,7 @@ IRQPolarity(ULONG idx)
break; break;
case 2: /* reserved */ case 2: /* reserved */
DPRINT("Broken BIOS!!\n"); DPRINT1("Broken BIOS\n");
polarity = 1; polarity = 1;
break; break;
@ -126,7 +126,7 @@ IRQPolarity(ULONG idx)
break; break;
default: /* invalid */ default: /* invalid */
DPRINT("Broken BIOS!!\n"); DPRINT1("Broken BIOS\n");
polarity = 1; polarity = 1;
} }
return polarity; return polarity;
@ -164,7 +164,7 @@ IRQTrigger(ULONG idx)
break; break;
default: default:
DPRINT("Broken BIOS!!\n"); DPRINT1("Broken BIOS\n");
trigger = 1; trigger = 1;
} }
} }
@ -175,7 +175,7 @@ IRQTrigger(ULONG idx)
break; break;
case 2: /* reserved */ case 2: /* reserved */
DPRINT("Broken BIOS!!\n"); DPRINT1("Broken BIOS\n");
trigger = 1; trigger = 1;
break; break;
@ -184,7 +184,7 @@ IRQTrigger(ULONG idx)
break; break;
default: /* invalid */ default: /* invalid */
DPRINT("Broken BIOS!!\n"); DPRINT1("Broken BIOS\n");
trigger = 0; trigger = 0;
} }
return trigger; return trigger;
@ -203,7 +203,7 @@ Pin2Irq(ULONG idx,
*/ */
if (IRQMap[idx].DstApicInt != pin) if (IRQMap[idx].DstApicInt != pin)
{ {
DPRINT("broken BIOS or MPTABLE parser, ayiee!!\n"); DPRINT1("Broken BIOS or MPTABLE parser\n");
} }
switch (BUSMap[bus]) switch (BUSMap[bus])
@ -227,7 +227,7 @@ Pin2Irq(ULONG idx,
break; break;
default: default:
DPRINT("Unknown bus type %d.\n",bus); DPRINT1("Unknown bus type %lu\n", bus);
irq = 0; irq = 0;
} }
return irq; return irq;
@ -254,7 +254,7 @@ AssignIrqVector(ULONG irq)
} }
else if (current_vector == FIRST_SYSTEM_VECTOR) else if (current_vector == FIRST_SYSTEM_VECTOR)
{ {
DPRINT1("Ran out of interrupt sources!"); DPRINT1("Ran out of interrupt sources\n");
ASSERT(FALSE); ASSERT(FALSE);
} }
@ -322,12 +322,12 @@ IOAPICSetupIrqs(VOID)
{ {
if (first_notcon) if (first_notcon)
{ {
DPRINT(" IO-APIC (apicid-pin) %d-%d\n", IOAPICMap[apic].ApicId, pin); DPRINT(" IO-APIC (apicid-pin) %u-%lu\n", IOAPICMap[apic].ApicId, pin);
first_notcon = 0; first_notcon = 0;
} }
else else
{ {
DPRINT(", %d-%d\n", IOAPICMap[apic].ApicId, pin); DPRINT(", %u-%lu\n", IOAPICMap[apic].ApicId, pin);
} }
continue; continue;
} }
@ -345,7 +345,7 @@ IOAPICSetupIrqs(VOID)
vector = AssignIrqVector(irq); vector = AssignIrqVector(irq);
entry.vector = vector; entry.vector = vector;
DPRINT("vector 0x%.08x assigned to irq 0x%.02x\n", vector, irq); DPRINT("Vector 0x%.08lx assigned to irq 0x%.02lx\n", vector, irq);
if (irq == 0) if (irq == 0)
{ {
@ -362,7 +362,7 @@ IOAPICSetupIrqs(VOID)
IrqApicMap[irq] = apic; IrqApicMap[irq] = apic;
DPRINT("Vector %x, Pin %x, Irq %x\n", vector, pin, irq); DPRINT("Vector %lx, Pin %lx, Irq %lx\n", vector, pin, irq);
} }
} }
} }
@ -372,7 +372,7 @@ IOAPICClearPin(ULONG Apic, ULONG Pin)
{ {
IOAPIC_ROUTE_ENTRY Entry; IOAPIC_ROUTE_ENTRY Entry;
DPRINT("IOAPICClearPin(Apic %d, Pin %d\n", Apic, Pin); DPRINT("IOAPICClearPin(Apic %lu, Pin %lu\n", Apic, Pin);
/* /*
* Disable it in the IO-APIC irq-routing table * Disable it in the IO-APIC irq-routing table
*/ */
@ -447,11 +447,9 @@ IOAPICSetupIds(VOID)
if (IOAPICMap[apic].ApicId >= 0xf) if (IOAPICMap[apic].ApicId >= 0xf)
{ {
DPRINT1("BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", DPRINT1("BIOS bug, IO-APIC#%lu ID is %u in the MPC table\n", apic, IOAPICMap[apic].ApicId);
apic, IOAPICMap[apic].ApicId);
DPRINT1("... fixing up to %d. (tell your hw vendor)\n",
GET_IOAPIC_ID(tmp));
IOAPICMap[apic].ApicId = GET_IOAPIC_ID(tmp); IOAPICMap[apic].ApicId = GET_IOAPIC_ID(tmp);
DPRINT1(" Fixed up to %u. (Tell your hardware vendor)\n", IOAPICMap[apic].ApicId);
} }
/* /*
@ -473,8 +471,7 @@ IOAPICSetupIds(VOID)
* Read the right value from the MPC table and * Read the right value from the MPC table and
* write it into the ID register. * write it into the ID register.
*/ */
DPRINT("Changing IO-APIC physical APIC ID to %d\n", DPRINT("Changing IO-APIC physical APIC ID to %u\n", IOAPICMap[apic].ApicId);
IOAPICMap[apic].ApicId);
tmp &= ~IOAPIC_ID_MASK; tmp &= ~IOAPIC_ID_MASK;
tmp |= SET_IOAPIC_ID(IOAPICMap[apic].ApicId); tmp |= SET_IOAPIC_ID(IOAPICMap[apic].ApicId);
@ -642,10 +639,10 @@ HaliReconfigurePciInterrupts(VOID)
{ {
if (BUSMap[IRQMap[i].SrcBusId] == MP_BUS_PCI) if (BUSMap[IRQMap[i].SrcBusId] == MP_BUS_PCI)
{ {
DPRINT("%02x: IrqType %02x, IrqFlag %02x, SrcBusId %02x, SrcBusIrq %02x" DPRINT("%02lx: IrqType %02x, IrqFlag %04x, SrcBusId %02x"
", DstApicId %02x, DstApicInt %02x\n", ", SrcBusIrq %02x, DstApicId %02x, DstApicInt %02x\n",
i, IRQMap[i].IrqType, IRQMap[i].IrqFlag, IRQMap[i].SrcBusId, i, IRQMap[i].IrqType, IRQMap[i].IrqFlag, IRQMap[i].SrcBusId,
IRQMap[i].SrcBusIrq, IRQMap[i].DstApicId, IRQMap[i].DstApicInt); IRQMap[i].SrcBusIrq, IRQMap[i].DstApicId, IRQMap[i].DstApicInt);
HalSetBusDataByOffset(PCIConfiguration, HalSetBusDataByOffset(PCIConfiguration,
IRQMap[i].SrcBusId, IRQMap[i].SrcBusId,