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- Provide better PCI device descriptions.
- Use public macros to analyze the PCI configuration space. svn path=/trunk/; revision=10617
This commit is contained in:
Eric Kohl
parent
a5e0bea967
commit
26981b72cf
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@ -1,4 +1,4 @@
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/* $Id: pci.c,v 1.8 2004/08/16 09:13:00 ekohl Exp $
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/* $Id: pci.c,v 1.9 2004/08/20 13:33:51 ekohl Exp $
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*
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* PROJECT: ReactOS PCI Bus driver
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* FILE: pci.c
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@ -436,8 +436,22 @@ PciCreateDeviceDescriptionString(PUNICODE_STRING DeviceDescription,
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switch (Device->PciConfig.BaseClass)
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{
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case PCI_CLASS_PRE_20:
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_PRE_20_VGA:
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Description = L"VGA device";
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break;
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default:
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case PCI_SUBCLASS_PRE_20_NON_VGA:
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Description = L"PCI device";
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break;
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}
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break;
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case PCI_CLASS_MASS_STORAGE_CTLR:
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switch (Device->PciConfig.BaseClass)
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_MSC_SCSI_BUS_CTLR:
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Description = L"SCSI controller";
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@ -461,20 +475,217 @@ PciCreateDeviceDescriptionString(PUNICODE_STRING DeviceDescription,
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default:
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Description = L"Mass storage controller";
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break;
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}
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break;
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case PCI_CLASS_NETWORK_CTLR:
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switch (Device->PciConfig.BaseClass)
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_NET_ETHERNET_CTLR:
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Description = L"Ethernet controller";
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break;
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case PCI_SUBCLASS_NET_TOKEN_RING_CTLR:
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Description = L"Token-Ring controller";
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break;
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case PCI_SUBCLASS_NET_FDDI_CTLR:
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Description = L"FDDI controller";
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break;
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case PCI_SUBCLASS_NET_ATM_CTLR:
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Description = L"ATM controller";
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break;
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default:
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Description = L"Network controller";
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break;
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}
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break;
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case PCI_CLASS_DISPLAY_CTLR:
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_VID_VGA_CTLR:
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Description = L"VGA display controller";
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break;
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case PCI_SUBCLASS_VID_XGA_CTLR:
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Description = L"XGA display controller";
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break;
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case PCI_SUBLCASS_VID_3D_CTLR:
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Description = L"Multimedia display controller";
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break;
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default:
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Description = L"Other display controller";
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break;
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}
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break;
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case PCI_CLASS_MULTIMEDIA_DEV:
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_MM_VIDEO_DEV:
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Description = L"Multimedia video device";
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break;
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case PCI_SUBCLASS_MM_AUDIO_DEV:
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Description = L"Multimedia audio device";
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break;
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case PCI_SUBCLASS_MM_TELEPHONY_DEV:
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Description = L"Multimedia telephony device";
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break;
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default:
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Description = L"Other multimedia device";
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break;
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}
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break;
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case PCI_CLASS_MEMORY_CTLR:
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_MEM_RAM:
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Description = L"PCI Memory";
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break;
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case PCI_SUBCLASS_MEM_FLASH:
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Description = L"PCI Flash Memory";
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break;
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default:
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Description = L"Other memory controller";
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break;
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}
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break;
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case PCI_CLASS_BRIDGE_DEV:
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_BR_HOST:
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Description = L"PCI-Host bridge";
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break;
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case PCI_SUBCLASS_BR_ISA:
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Description = L"PCI-ISA bridge";
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break;
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case PCI_SUBCLASS_BR_EISA:
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Description = L"PCI-EISA bridge";
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break;
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case PCI_SUBCLASS_BR_MCA:
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Description = L"PCI-Micro Channel bridge";
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break;
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case PCI_SUBCLASS_BR_PCI_TO_PCI:
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Description = L"PCI-PCI bridge";
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break;
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case PCI_SUBCLASS_BR_PCMCIA:
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Description = L"PCI-PCMCIA bridge";
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break;
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case PCI_SUBCLASS_BR_NUBUS:
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Description = L"PCI-NUBUS bridge";
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break;
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case PCI_SUBCLASS_BR_CARDBUS:
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Description = L"PCI-CARDBUS bridge";
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break;
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default:
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Description = L"Other bridge device";
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break;
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}
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break;
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case PCI_CLASS_SIMPLE_COMMS_CTLR:
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switch (Device->PciConfig.SubClass)
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{
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default:
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Description = L"Communication device";
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break;
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}
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break;
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case PCI_CLASS_BASE_SYSTEM_DEV:
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switch (Device->PciConfig.SubClass)
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{
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default:
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Description = L"System device";
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break;
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}
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break;
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case PCI_CLASS_INPUT_DEV:
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switch (Device->PciConfig.SubClass)
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{
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default:
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Description = L"Input device";
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break;
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}
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break;
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case PCI_CLASS_DOCKING_STATION:
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switch (Device->PciConfig.SubClass)
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{
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default:
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Description = L"Docking station";
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break;
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}
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break;
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case PCI_CLASS_PROCESSOR:
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switch (Device->PciConfig.SubClass)
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{
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default:
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Description = L"Processor";
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break;
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}
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break;
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case PCI_CLASS_SERIAL_BUS_CTLR:
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switch (Device->PciConfig.SubClass)
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{
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case PCI_SUBCLASS_SB_IEEE1394:
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Description = L"FireWire controller";
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break;
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case PCI_SUBCLASS_SB_ACCESS:
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Description = L"ACCESS bus controller";
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break;
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case PCI_SUBCLASS_SB_SSA:
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Description = L"SSA controller";
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break;
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case PCI_SUBCLASS_SB_USB:
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Description = L"USB controller";
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break;
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case PCI_SUBCLASS_SB_FIBRE_CHANNEL:
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Description = L"Fibre Channel controller";
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break;
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default:
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Description = L"Other serial bus controller";
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break;
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}
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break;
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default:
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Description = L"PCI-Device";
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Description = L"Other PCI Device";
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break;
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}
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Length = (wcslen(Description) + 1) * sizeof(WCHAR);
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@ -1,4 +1,4 @@
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/* $Id: pdo.c,v 1.8 2004/08/18 22:11:15 ekohl Exp $
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/* $Id: pdo.c,v 1.9 2004/08/20 13:33:51 ekohl Exp $
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*
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* PROJECT: ReactOS PCI bus driver
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* FILE: pdo.c
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@ -39,7 +39,7 @@ PdoQueryDeviceText(
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{
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case DeviceTextDescription:
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DPRINT("DeviceTextDescription\n");
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Irp->IoStatus.Information = (ULONG_PTR)DeviceExtension->DeviceLocation.Buffer;
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Irp->IoStatus.Information = (ULONG_PTR)DeviceExtension->DeviceDescription.Buffer;
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break;
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case DeviceTextLocationInformation:
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@ -169,10 +169,10 @@ PdoQueryCapabilities(
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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DeviceCapabilities = IrpSp->Parameters.DeviceCapabilities.Capabilities;
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DeviceCapabilities->UniqueID = TRUE;
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DeviceCapabilities->UniqueID = FALSE;
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DeviceCapabilities->Address =
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DeviceCapabilities->UINumber = DeviceExtension->SlotNumber.u.AsULONG;
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DeviceCapabilities->Address = DeviceExtension->SlotNumber.u.AsULONG;
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DeviceCapabilities->UINumber = (ULONG)-1; /* FIXME */
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return STATUS_SUCCESS;
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}
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@ -338,7 +338,7 @@ PdoQueryResourceRequirements(
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/* Count required resource descriptors */
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ResCount = 0;
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if ((PciConfig.HeaderType & 0x7F) == 0)
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if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
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{
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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@ -347,7 +347,7 @@ PdoQueryResourceRequirements(
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&Base,
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&Length,
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&Flags))
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break;
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break;
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ResCount += 2;
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}
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@ -357,7 +357,7 @@ PdoQueryResourceRequirements(
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if (PciConfig.u.type0.InterruptPin != 0)
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ResCount++;
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}
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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@ -366,14 +366,17 @@ PdoQueryResourceRequirements(
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&Base,
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&Length,
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&Flags))
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break;
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break;
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ResCount += 2;
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}
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}
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
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{
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}
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else
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{
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DPRINT1("Unsupported header type %u\n", PciConfig.HeaderType);
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DPRINT1("Unsupported header type %u\n", PCI_CONFIGURATION_TYPE(&PciConfig));
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}
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if (ResCount == 0)
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@ -389,7 +392,7 @@ PdoQueryResourceRequirements(
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ListSize += ((ResCount - 1) * sizeof(IO_RESOURCE_DESCRIPTOR));
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}
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DPRINT1("ListSize %lu (0x%lx)\n", ListSize, ListSize);
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DPRINT("ListSize %lu (0x%lx)\n", ListSize, ListSize);
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/* Allocate the resource requirements list */
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ResourceList = ExAllocatePool(PagedPool,
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@ -409,7 +412,7 @@ PdoQueryResourceRequirements(
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ResourceList->List[0].Count = ResCount;
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Descriptor = &ResourceList->List[0].Descriptors[0];
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if ((PciConfig.HeaderType & 0x7F) == 0)
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if (PCI_CONFIGURATION_TYPE(&PciConfig) == 0)
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{
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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@ -498,7 +501,7 @@ PdoQueryResourceRequirements(
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Descriptor->u.Interrupt.MaximumVector = 0xFF;
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}
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}
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == 1)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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@ -575,6 +578,10 @@ PdoQueryResourceRequirements(
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Descriptor++;
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}
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}
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == 2)
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{
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/* FIXME: Add Cardbus bridge resources */
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}
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Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
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@ -622,7 +629,7 @@ PdoQueryResources(
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/* Count required resource descriptors */
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ResCount = 0;
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if ((PciConfig.HeaderType & 0x7F) == 0)
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if (PCI_CONFIGURATION_TYPE(&PciConfig) == 0)
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{
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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@ -640,7 +647,7 @@ PdoQueryResources(
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(PciConfig.u.type0.InterruptLine != 0xFF))
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ResCount++;
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}
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == 1)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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@ -653,10 +660,14 @@ PdoQueryResources(
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ResCount++;
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}
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}
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == 2)
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{
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}
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else
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{
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DPRINT1("Unsupported header type %u\n", PciConfig.HeaderType);
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DPRINT1("Unsupported header type %u\n", PCI_CONFIGURATION_TYPE(&PciConfig));
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}
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if (ResCount == 0)
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@ -688,7 +699,7 @@ PdoQueryResources(
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PartialList->Count = ResCount;
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Descriptor = &PartialList->PartialDescriptors[0];
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if ((PciConfig.HeaderType & 0x7F) == 0)
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if (PCI_CONFIGURATION_TYPE(&PciConfig) == 0)
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{
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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@ -742,7 +753,7 @@ PdoQueryResources(
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Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
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}
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}
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == 1)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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@ -784,6 +795,10 @@ PdoQueryResources(
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Descriptor++;
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}
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}
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else if (PCI_CONFIGURATION_TYPE(&PciConfig) == 2)
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{
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/* FIXME: Cardbus */
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}
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Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
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