Intravision/reactos
1
0
Fork 0
mirror of https://github.com/reactos/reactos.git synced 2024-12-28 10:04:49 +00:00
Code Issues Projects Releases Packages Wiki Activity

- Fix some more MSVC problems.

Browse source 
- Get rid of HAL's own intrisics and use intrin_i.h and/or MSVC intrinsics from intrin.h
- If anyone knows how to make a .DEF file that is not only understood by both compilers, but also creates a proper import library, please let me know.

svn path=/trunk/; revision=24774
This commit is contained in:
Alex Ionescu 2006-11-17 04:18:41 +00:00
parent 5ec8f2dc40
commit 1a3b63b4c4
12 changed files with 68 additions and 99 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
reactos/hal/hal/hal.c
View file

@ -27,7 +27,7 @@
/* DATA **********************************************************************/
ULONG KdComPortInUse = 0;
ULONG _KdComPortInUse = 0;
/* FUNCTIONS *****************************************************************/

2
reactos/hal/hal/hal.def
View file

@ -72,7 +72,7 @@ IoMapTransfer@24
IoReadPartitionTable@16=HalpReadPartitionTable@16
IoSetPartitionInformation@16=HalpSetPartitionInformation@16
IoWritePartitionTable@20=HalpWritePartitionTable@20
KdComPortInUse DATA
KdComPortInUse=_KdComPortInUse
; FIXME: DEPRECATED
KdPortGetByte@4
KdPortGetByteEx@8

1
reactos/hal/hal/hal.rbuild
View file

@ -4,6 +4,7 @@
<library>ntoskrnl</library>
<define name="_NTHAL_" />
<define name="__USE_W32API" />
<linkerflag>-enable-stdcall-fixup</linkerflag>
<file>hal.c</file>
<file>hal.rc</file>
</module>

10
reactos/hal/halx86/generic/irql.c
View file

@ -92,7 +92,7 @@ VOID NTAPI HalpInitPICs(VOID)
WRITE_PORT_UCHAR((PUCHAR)0xa1, pic_mask.slave);
/* We can now enable interrupts */
Ki386EnableInterrupts();
_enable();
}
VOID HalpEndSystemInterrupt(KIRQL Irql)
@ -100,7 +100,6 @@ VOID HalpEndSystemInterrupt(KIRQL Irql)
* FUNCTION: Enable all irqs with higher priority.
*/
{
ULONG flags;
const USHORT mask[] =
{
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
@ -110,15 +109,14 @@ VOID HalpEndSystemInterrupt(KIRQL Irql)
};
/* Interrupts should be disable while enabling irqs of both pics */
Ki386SaveFlags(flags);
Ki386DisableInterrupts();
_disable();
pic_mask_intr.both &= mask[Irql];
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
/* restore flags */
Ki386RestoreFlags(flags);
/* restore ints */
_enable();
}
VOID

2
reactos/hal/halx86/generic/processor.c
View file

@ -68,7 +68,7 @@ HalProcessorIdle(VOID)
{
/* Enable interrupts and halt the processor */
_enable();
Ki386HaltProcessor();
Ke386HaltProcessor();
}
/*

2
reactos/hal/halx86/generic/reboot.c
View file

@ -65,7 +65,7 @@ HalpReboot(VOID)
HalpWriteResetCommand();
/* Halt the CPU */
Ki386HaltProcessor();
Ke386HaltProcessor();
}
/* PUBLIC FUNCTIONS **********************************************************/

38
reactos/hal/halx86/generic/timer.c
View file

@ -130,11 +130,11 @@ KeStallExecutionProcessor(ULONG Microseconds)
if (Pcr->PrcbData.FeatureBits & KF_RDTSC)
{
LARGE_INTEGER EndCount, CurrentCount;
EndCount.QuadPart = (LONGLONG)__rdtsc;
EndCount.QuadPart = (LONGLONG)__rdtsc();
EndCount.QuadPart += Microseconds * (ULONGLONG)Pcr->PrcbData.MHz;
do
{
CurrentCount.QuadPart = (LONGLONG)__rdtsc;
CurrentCount.QuadPart = (LONGLONG)__rdtsc();
}
while (CurrentCount.QuadPart < EndCount.QuadPart);
}
@ -147,19 +147,15 @@ KeStallExecutionProcessor(ULONG Microseconds)
static ULONG Read8254Timer(VOID)
{
ULONG Count;
ULONG flags;
/* save flags and disable interrupts */
Ki386SaveFlags(flags);
Ki386DisableInterrupts();
/* Disable interrupts */
_disable();
WRITE_PORT_UCHAR((PUCHAR) TMR_CTRL, TMR_SC0 | TMR_LATCH);
Count = READ_PORT_UCHAR((PUCHAR) TMR_CNT0);
Count |= READ_PORT_UCHAR((PUCHAR) TMR_CNT0) << 8;
/* restore flags */
Ki386RestoreFlags(flags);
_enable();
return Count;
}
@ -212,10 +208,10 @@ VOID HalpCalibrateStallExecution(VOID)
{
WaitFor8254Wraparound();
StartCount.QuadPart = (LONGLONG)__rdtsc;
StartCount.QuadPart = (LONGLONG)__rdtsc();
WaitFor8254Wraparound();
EndCount.QuadPart = (LONGLONG)__rdtsc;
EndCount.QuadPart = (LONGLONG)__rdtsc();
Pcr->PrcbData.MHz = (ULONG)(EndCount.QuadPart - StartCount.QuadPart) / 10000;
DPRINT("%luMHz\n", Pcr->PrcbData.MHz);
@ -294,16 +290,12 @@ VOID HalpCalibrateStallExecution(VOID)
VOID STDCALL
HalCalibratePerformanceCounter(ULONG Count)
{
ULONG flags;
/* save flags and disable interrupts */
Ki386SaveFlags(flags);
Ki386DisableInterrupts();
/* Disable interrupts */
_disable();
__KeStallExecutionProcessor(Count);
/* restore flags */
Ki386RestoreFlags(flags);
_enable();
}
@ -320,21 +312,19 @@ KeQueryPerformanceCounter(PLARGE_INTEGER PerformanceFreq)
{
PKIPCR Pcr;
LARGE_INTEGER Value;
ULONG Flags;
Ki386SaveFlags(Flags);
Ki386DisableInterrupts();
_disable();
Pcr = (PKIPCR)KeGetPcr();
if (Pcr->PrcbData.FeatureBits & KF_RDTSC)
{
Ki386RestoreFlags(Flags);
_enable();
if (NULL != PerformanceFreq)
{
PerformanceFreq->QuadPart = Pcr->PrcbData.MHz * (ULONGLONG)1000000;
}
Value.QuadPart = (LONGLONG)__rdtsc;
Value.QuadPart = (LONGLONG)__rdtsc();
}
else
{
@ -342,7 +332,7 @@ KeQueryPerformanceCounter(PLARGE_INTEGER PerformanceFreq)
LARGE_INTEGER TicksNew;
ULONG CountsLeft;
Ki386RestoreFlags(Flags);
_enable();
if (NULL != PerformanceFreq)
{

8
reactos/hal/halx86/include/hal.h
View file

@ -11,13 +11,14 @@
/* C Headers */
#include <stdio.h>
/* WDK HAL Complation hack */
/* WDK HAL Compilation hack */
#ifdef _MSC_VER
#include <excpt.h>
#include <ntdef.h>
#undef _NTHAL_
#undef DECLSPEC_IMPORT
#define DECLSPEC_IMPORT
#define __declspec(dllimport)
#endif
/* IFS/DDK/NDK Headers */
@ -31,10 +32,11 @@
#include <ldrtypes.h>
#include <obfuncs.h>
#define KPCR_BASE 0xFF000000 // HACK!
/* Internal kernel headers */
#include "internal/pci.h"
#include "internal/i386/intrin_i.h"
/* Internal HAL Headers */
#include "internal/pci.h"
#include "apic.h"
#include "bus.h"
#include "halirq.h"

35
reactos/hal/halx86/include/halp.h
View file

@ -5,6 +5,12 @@
#ifndef __INTERNAL_HAL_HAL_H
#define __INTERNAL_HAL_HAL_H
/* Temporary hack */
#define KPCR_BASE 0xFF000000
/* WDK Hack */
#define KdComPortInUse _KdComPortInUse
#define HAL_APC_REQUEST 0
#define HAL_DPC_REQUEST 1
@ -53,35 +59,6 @@ HalpQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
IN OUT PVOID Buffer,
OUT PULONG ReturnedLength);
/* Non-standard functions */
VOID STDCALL
HalReleaseDisplayOwnership();
BOOLEAN STDCALL
HalQueryDisplayOwnership();
#if defined(__GNUC__)
#define Ki386SaveFlags(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
#define Ki386RestoreFlags(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
#define Ki386DisableInterrupts() __asm__ __volatile__("cli\n\t")
#define Ki386EnableInterrupts() __asm__ __volatile__("sti\n\t")
#define Ki386HaltProcessor() __asm__ __volatile__("hlt\n\t")
#define Ki386RdTSC(x) __asm__ __volatile__("rdtsc\n\t" : "=A" (x.u.LowPart), "=d" (x.u.HighPart))
#define Ki386Rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
#define Ki386Wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : /* no outputs */ : "c" (msr), "a" (val1), "d" (val2))
#define Ki386ReadFsByte(offset,x) __asm__ __volatile__("movb %%fs:%c1,%0" : "=q" (x) : "i" (offset))
#define Ki386WriteFsByte(offset,x) __asm__ __volatile__("movb %0,%%fs:%c1" : : "q" ((UCHAR)x), "i" (offset))
#elif defined(_MSC_VER)
#define Ki386SaveFlags(x) __asm pushfd __asm pop x;
#define Ki386RestoreFlags(x) __asm push x __asm popfd;
#define Ki386DisableInterrupts() __asm cli
#define Ki386EnableInterrupts() __asm sti
#define Ki386HaltProcessor() __asm hlt
#else
#error Unknown compiler for inline assembler
#endif
typedef struct tagHALP_HOOKS
{
void (*InitPciBus)(ULONG BusNumber, PBUS_HANDLER BusHandler);

22
reactos/hal/halx86/mp/apic.c
View file

@ -465,14 +465,14 @@ BOOLEAN VerifyLocalAPIC(VOID)
return FALSE;
}
Ki386Rdmsr(0x1b /*MSR_IA32_APICBASE*/, l, h);
Ke386Rdmsr(0x1b /*MSR_IA32_APICBASE*/, l, h);
if (!(l & /*MSR_IA32_APICBASE_ENABLE*/(1<<11)))
{
DPRINT1("Local APIC disabled by BIOS -- reenabling.\n");
l &= ~/*MSR_IA32_APICBASE_BASE*/(1<<11);
l |= /*MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE*/(1<<11)|0xfee00000;
Ki386Wrmsr(0x1b/*MSR_IA32_APICBASE*/, l, h);
Ke386Wrmsr(0x1b/*MSR_IA32_APICBASE*/, l, h);
}
@ -486,8 +486,8 @@ VOID APICSendIPI(ULONG Target, ULONG Mode)
ULONG tmp, i, flags;
/* save flags and disable interrupts */
Ki386SaveFlags(flags);
Ki386DisableInterrupts();
Ke386SaveFlags(flags);
_disable();
/* Wait up to 100ms for the APIC to become ready */
for (i = 0; i < 10000; i++)
@ -542,7 +542,7 @@ VOID APICSendIPI(ULONG Target, ULONG Mode)
{
DPRINT1("CPU(%d) Current IPI was not delivered after 100ms.\n", ThisCPU());
}
Ki386RestoreFlags(flags);
Ke386RestoreFlags(flags);
}
#endif
@ -754,7 +754,7 @@ VOID MpsIpiHandler(VOID)
HalBeginSystemInterrupt(IPI_LEVEL,
IPI_VECTOR,
&oldIrql);
Ki386EnableInterrupts();
_enable();
#if 0
DbgPrint("(%s:%d) MpsIpiHandler on CPU%d, current irql is %d\n",
__FILE__,__LINE__, KeGetCurrentProcessorNumber(), KeGetCurrentIrql());
@ -766,7 +766,7 @@ VOID MpsIpiHandler(VOID)
DbgPrint("(%s:%d) MpsIpiHandler on CPU%d done\n", __FILE__,__LINE__, KeGetCurrentProcessorNumber());
#endif
Ki386DisableInterrupts();
_disable();
HalEndSystemInterrupt(oldIrql, 0);
}
#endif
@ -804,7 +804,7 @@ MpsTimerHandler(ULONG Vector, PKIRQ_TRAPFRAME Trapframe)
HalBeginSystemInterrupt(LOCAL_TIMER_VECTOR,
PROFILE_LEVEL,
&oldIrql);
Ki386EnableInterrupts();
_enable();
#if 0
CPU = ThisCPU();
@ -826,7 +826,7 @@ MpsTimerHandler(ULONG Vector, PKIRQ_TRAPFRAME Trapframe)
//KeUpdateRunTime(&KernelTrapFrame, oldIrql);
}
Ki386DisableInterrupts();
_disable();
HalEndSystemInterrupt (oldIrql, 0);
}
@ -878,7 +878,7 @@ APICCalibrateTimer(ULONG CPU)
*/
if (TSCPresent)
{
Ki386RdTSC(t1);
t1.QuadPart = (LONGLONG)__rdtsc();
}
tt1 = APICRead(APIC_CCRT);
@ -888,7 +888,7 @@ APICCalibrateTimer(ULONG CPU)
tt2 = APICRead(APIC_CCRT);
if (TSCPresent)
{
Ki386RdTSC(t2);
t2.QuadPart = (LONGLONG)__rdtsc();
CPUMap[CPU].CoreSpeed = (HZ * (t2.QuadPart - t1.QuadPart));
DPRINT("CPU clock speed is %ld.%04ld MHz.\n",
CPUMap[CPU].CoreSpeed/1000000,

44
reactos/hal/halx86/mp/mpsirql.c
View file

@ -30,10 +30,10 @@ KIRQL STDCALL KeGetCurrentIrql (VOID)
KIRQL irql;
ULONG Flags;
Ki386SaveFlags(Flags);
Ki386DisableInterrupts();
Ke386SaveFlags(Flags);
_disable();
Ki386ReadFsByte(FIELD_OFFSET(KPCR, Irql), irql);
irql = __readfsbyte(FIELD_OFFSET(KPCR, Irql));
if (irql > HIGH_LEVEL)
{
DPRINT1 ("CurrentIrql %x\n", irql);
@ -41,7 +41,7 @@ KIRQL STDCALL KeGetCurrentIrql (VOID)
}
if (Flags & EFLAGS_INTERRUPT_MASK)
{
Ki386EnableInterrupts();
_enable();
}
return irql;
}
@ -59,12 +59,12 @@ VOID KeSetCurrentIrql (KIRQL NewIrql)
DPRINT1 ("NewIrql %x\n", NewIrql);
KEBUGCHECK (0);
}
Ki386SaveFlags(Flags);
Ki386DisableInterrupts();
Ki386WriteFsByte(FIELD_OFFSET(KPCR, Irql), NewIrql);
Ke386SaveFlags(Flags);
_disable();
__writefsbyte(FIELD_OFFSET(KPCR, Irql), NewIrql);
if (Flags & EFLAGS_INTERRUPT_MASK)
{
Ki386EnableInterrupts();
_enable();
}
}
@ -79,20 +79,20 @@ HalpLowerIrql(KIRQL NewIrql, BOOLEAN FromHalEndSystemInterrupt)
APICWrite(APIC_TPR, IRQL2TPR (NewIrql) & APIC_TPR_PRI);
return;
}
Ki386SaveFlags(Flags);
Ke386SaveFlags(Flags);
if (KeGetCurrentIrql() > APC_LEVEL)
{
KeSetCurrentIrql (DISPATCH_LEVEL);
APICWrite(APIC_TPR, IRQL2TPR (DISPATCH_LEVEL) & APIC_TPR_PRI);
Ki386ReadFsByte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]), DpcRequested);
DpcRequested = __readfsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]));
if (FromHalEndSystemInterrupt || DpcRequested)
{
Ki386WriteFsByte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]), 0);
Ki386EnableInterrupts();
__writefsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]), 0);
_enable();
KiDispatchInterrupt();
if (!(Flags & EFLAGS_INTERRUPT_MASK))
{
Ki386DisableInterrupts();
_disable();
}
}
KeSetCurrentIrql (APC_LEVEL);
@ -104,11 +104,11 @@ HalpLowerIrql(KIRQL NewIrql, BOOLEAN FromHalEndSystemInterrupt)
if (KeGetCurrentThread () != NULL &&
KeGetCurrentThread ()->ApcState.KernelApcPending)
{
Ki386EnableInterrupts();
_enable();
KiDeliverApc(KernelMode, NULL, NULL);
if (!(Flags & EFLAGS_INTERRUPT_MASK))
{
Ki386DisableInterrupts();
_disable();
}
}
KeSetCurrentIrql (PASSIVE_LEVEL);
@ -190,8 +190,8 @@ KfRaiseIrql (KIRQL NewIrql)
KIRQL OldIrql;
ULONG Flags;
Ki386SaveFlags(Flags);
Ki386DisableInterrupts();
Ke386SaveFlags(Flags);
_disable();
OldIrql = KeGetCurrentIrql ();
@ -209,7 +209,7 @@ KfRaiseIrql (KIRQL NewIrql)
KeSetCurrentIrql (NewIrql);
if (Flags & EFLAGS_INTERRUPT_MASK)
{
Ki386EnableInterrupts();
_enable();
}
return OldIrql;
@ -304,7 +304,7 @@ HalBeginSystemInterrupt (KIRQL Irql,
KEBUGCHECK(0);
}
Ki386SaveFlags(Flags);
Ke386SaveFlags(Flags);
if (Flags & EFLAGS_INTERRUPT_MASK)
{
DPRINT1("HalBeginSystemInterrupt was called with interrupt's enabled\n");
@ -325,7 +325,7 @@ HalEndSystemInterrupt (KIRQL Irql,
*/
{
ULONG Flags;
Ki386SaveFlags(Flags);
Ke386SaveFlags(Flags);
if (Flags & EFLAGS_INTERRUPT_MASK)
{
@ -386,11 +386,11 @@ HalRequestSoftwareInterrupt(IN KIRQL Request)
switch (Request)
{
case APC_LEVEL:
Ki386WriteFsByte(FIELD_OFFSET(KIPCR, HalReserved[HAL_APC_REQUEST]), 1);
__writefsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_APC_REQUEST]), 1);
break;
case DISPATCH_LEVEL:
Ki386WriteFsByte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]), 1);
__writefsbyte(FIELD_OFFSET(KIPCR, HalReserved[HAL_DPC_REQUEST]), 1);
break;
default:

1
reactos/hal/halx86/up/halup.rbuild
View file

@ -6,6 +6,7 @@
<define name="_DISABLE_TIDENTS" />
<define name="__USE_W32API" />
<define name="_NTHAL_" />
<linkerflag>-enable-stdcall-fixup</linkerflag>
<library>hal_generic</library>
<library>hal_generic_up</library>
<library>hal_generic_pc</library>