mirror of
https://github.com/reactos/reactos.git
synced 2024-07-10 14:45:06 +00:00
[NTOS]: Make system startup match x86 code as closely as possible, instead of mixing MIPS/PPC code. Only rip out parts that are obviously x86-specific. Also fix code to use new KPCR definitions.
[NTOS]: Implement a DbgPrintEarly function that directly uses KDCOM to print to the serial console, instead of going through the Debug Service Interrupt. svn path=/trunk/; revision=45513
This commit is contained in:
Sir Richard
parent
6995f3fca6
commit
16ab546411
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@ -28,9 +28,7 @@ VOID
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NTAPI
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NTAPI
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KiInitMachineDependent(VOID)
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KiInitMachineDependent(VOID)
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{
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{
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//
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/* There is nothing to do on ARM */
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// There is nothing to do on ARM
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//
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return;
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return;
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}
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}
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@ -43,169 +41,55 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
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IN CCHAR Number,
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IN CCHAR Number,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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{
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PKIPCR Pcr = (PKIPCR)KeGetPcr();
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ULONG PageDirectory[2];
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ULONG PageDirectory[2];
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PKPCR Pcr;
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ULONG i;
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ULONG i;
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//
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// Initialize the platform
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//
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HalInitializeProcessor(Number, LoaderBlock);
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//
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/* Set the default NX policy (opt-in) */
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// Save loader block
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN;
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//
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KeLoaderBlock = LoaderBlock;
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//
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/* Initialize spinlocks and DPC data */
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// Setup KPRCB
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//
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Prcb->MajorVersion = 1;
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Prcb->MinorVersion = 1;
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Prcb->BuildType = 0;
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#ifndef CONFIG_SMP
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Prcb->BuildType |= PRCB_BUILD_UNIPROCESSOR;
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#endif
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#if DBG
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Prcb->BuildType |= PRCB_BUILD_DEBUG;
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#endif
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Prcb->CurrentThread = InitThread;
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Prcb->NextThread = NULL;
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Prcb->IdleThread = InitThread;
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Prcb->Number = Number;
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Prcb->SetMember = 1 << Number;
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Prcb->PcrPage = LoaderBlock->u.Arm.PcrPage;
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//
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// Initialize spinlocks and DPC data
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//
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KiInitSpinLocks(Prcb, Number);
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KiInitSpinLocks(Prcb, Number);
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//
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/* Set stack pointers */
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// Set the PRCB in the processor block
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//
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KiProcessorBlock[(ULONG)Number] = Prcb;
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Pcr = (PKPCR)KeGetPcr();
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//
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// Set processor information
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//
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KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM;
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KeFeatureBits = 0;
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KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8);
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KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF);
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//
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// Set stack pointers
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//
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Pcr->InitialStack = IdleStack;
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Pcr->InitialStack = IdleStack;
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Pcr->StackLimit = (PVOID)((ULONG_PTR)IdleStack - KERNEL_STACK_SIZE);
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//
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/* Check if this is the Boot CPU */
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// Check if this is the Boot CPU
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//
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if (!Number)
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if (!Number)
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{
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{
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//
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/* Setup the unexpected interrupt */
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// Setup the unexpected interrupt
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//
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KxUnexpectedInterrupt.DispatchAddress = KiUnexpectedInterrupt;
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KxUnexpectedInterrupt.DispatchAddress = KiUnexpectedInterrupt;
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for (i = 0; i < 4; i++)
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for (i = 0; i < 4; i++)
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{
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{
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//
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/* Copy the template code */
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// Copy the template code
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//
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KxUnexpectedInterrupt.DispatchCode[i] = ((PULONG)KiInterruptTemplate)[i];
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KxUnexpectedInterrupt.DispatchCode[i] = ((PULONG)KiInterruptTemplate)[i];
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}
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}
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//
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/* Set DMA coherency */
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// Set DMA coherency
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//
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KiDmaIoCoherency = 0;
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KiDmaIoCoherency = 0;
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//
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/* Sweep D-Cache */
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// Sweep D-Cache
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//
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HalSweepDcache();
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HalSweepDcache();
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}
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/* Set boot-level flags */
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//
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KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM;
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// Set all interrupt routines to unexpected interrupts as well
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KeFeatureBits = 0;
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//
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KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8);
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for (i = 0; i < MAXIMUM_VECTOR; i++)
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KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF);
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{
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//
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// Point to the same template
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//
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Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode;
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}
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//
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// Setup profiling
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//
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Pcr->ProfileCount = 0;
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Pcr->ProfileInterval = 0x200000;
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Pcr->StallScaleFactor = 50;
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//
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// Setup software interrupts
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//
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Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease;
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Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt;
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Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt;
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Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) |
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(1 << APC_LEVEL) |
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(1 << DISPATCH_LEVEL) |
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(1 << IPI_LEVEL);
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//
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/* Set the current MP Master KPRCB to the Boot PRCB */
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// Set IRQL and prcessor member/number
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Prcb->MultiThreadSetMaster = Prcb;
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//
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Pcr->CurrentIrql = APC_LEVEL;
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Pcr->SetMember = 1 << Number;
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Pcr->NotMember = -Pcr->SetMember;
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Pcr->Number = Number;
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//
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/* Lower to APC_LEVEL */
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// Remember our parent
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KeLowerIrql(APC_LEVEL);
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//
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InitThread->ApcState.Process = InitProcess;
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//
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/* Initialize portable parts of the OS */
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// Setup the active processor numbers
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//
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KeActiveProcessors |= 1 << Number;
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KeNumberProcessors = Number + 1;
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//
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// Check if this is the boot CPU
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//
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if (!Number)
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{
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//
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// Setup KD
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//
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KdInitSystem(0, LoaderBlock);
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//
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// Check for break-in
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//
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if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
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//
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// Cleanup the rest of the processor block array
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//
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for (i = 1; i < MAXIMUM_PROCESSORS; i++) KiProcessorBlock[i] = NULL;
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//
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// Initialize portable parts of the OS
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//
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KiInitSystem();
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KiInitSystem();
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//
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/* Initialize the Idle Process and the Process Listhead */
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// Initialize the Idle Process and the Process Listhead
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//
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InitializeListHead(&KiProcessListHead);
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InitializeListHead(&KiProcessListHead);
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PageDirectory[0] = 0;
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PageDirectory[1] = 0;
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KeInitializeProcess(InitProcess,
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KeInitializeProcess(InitProcess,
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0,
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0,
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0xFFFFFFFF,
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0xFFFFFFFF,
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@ -215,15 +99,11 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
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}
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}
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else
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else
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{
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{
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//
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/* FIXME-V6: See if we want to support MP */
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// FIXME-V6: See if we want to support MP
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//
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DPRINT1("ARM MPCore not supported\n");
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DPRINT1("ARM MPCore not supported\n");
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}
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}
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//
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/* Setup the Idle Thread */
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// Setup the Idle Thread
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//
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KeInitializeThread(InitProcess,
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KeInitializeThread(InitProcess,
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InitThread,
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InitThread,
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NULL,
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NULL,
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@ -239,253 +119,310 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
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InitThread->WaitIrql = DISPATCH_LEVEL;
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InitThread->WaitIrql = DISPATCH_LEVEL;
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InitProcess->ActiveProcessors = 1 << Number;
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InitProcess->ActiveProcessors = 1 << Number;
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//
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/* HACK for MmUpdatePageDir */
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// HACK for MmUpdatePageDir
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//
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((PETHREAD)InitThread)->ThreadsProcess = (PEPROCESS)InitProcess;
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((PETHREAD)InitThread)->ThreadsProcess = (PEPROCESS)InitProcess;
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//
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/* Set up the thread-related fields in the PRCB */
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// Initialize the Kernel Executive
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Prcb->CurrentThread = InitThread;
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//
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Prcb->NextThread = NULL;
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Prcb->IdleThread = InitThread;
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/* Initialize the Kernel Executive */
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ExpInitializeExecutive(Number, LoaderBlock);
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ExpInitializeExecutive(Number, LoaderBlock);
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//
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/* Only do this on the boot CPU */
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// Only do this on the boot CPU
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//
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if (!Number)
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if (!Number)
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{
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{
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//
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/* Calculate the time reciprocal */
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// Calculate the time reciprocal
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//
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KiTimeIncrementReciprocal =
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KiTimeIncrementReciprocal =
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KiComputeReciprocal(KeMaximumIncrement,
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KiComputeReciprocal(KeMaximumIncrement,
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&KiTimeIncrementShiftCount);
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&KiTimeIncrementShiftCount);
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//
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/* Update DPC Values in case they got updated by the executive */
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// Update DPC Values in case they got updated by the executive
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//
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Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth;
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Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth;
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Prcb->MinimumDpcRate = KiMinimumDpcRate;
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Prcb->MinimumDpcRate = KiMinimumDpcRate;
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Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold;
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Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold;
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}
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}
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//
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/* Raise to Dispatch */
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// Raise to Dispatch
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//
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KfRaiseIrql(DISPATCH_LEVEL);
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KfRaiseIrql(DISPATCH_LEVEL);
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//
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/* Set the Idle Priority to 0. This will jump into Phase 1 */
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// Set the Idle Priority to 0. This will jump into Phase 1
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//
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KeSetPriorityThread(InitThread, 0);
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KeSetPriorityThread(InitThread, 0);
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//
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/* If there's no thread scheduled, put this CPU in the Idle summary */
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// If there's no thread scheduled, put this CPU in the Idle summary
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//
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KiAcquirePrcbLock(Prcb);
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KiAcquirePrcbLock(Prcb);
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if (!Prcb->NextThread) KiIdleSummary |= 1 << Number;
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if (!Prcb->NextThread) KiIdleSummary |= 1 << Number;
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KiReleasePrcbLock(Prcb);
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KiReleasePrcbLock(Prcb);
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//
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/* Raise back to HIGH_LEVEL and clear the PRCB for the loader block */
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// Raise back to HIGH_LEVEL
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//
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KfRaiseIrql(HIGH_LEVEL);
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KfRaiseIrql(HIGH_LEVEL);
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LoaderBlock->Prcb = 0;
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}
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}
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C_ASSERT((PKIPCR)KeGetPcr() == (PKIPCR)0xFFDFF000);
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C_ASSERT((FIELD_OFFSET(KIPCR, FirstLevelDcacheSize) & 4) == 0);
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C_ASSERT(sizeof(KIPCR) <= PAGE_SIZE);
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VOID
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VOID
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KiInitializeSystem(IN ULONG Magic,
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NTAPI
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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KiInitializePcr(IN ULONG ProcessorNumber,
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IN PKIPCR Pcr,
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IN PKTHREAD IdleThread,
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IN PVOID PanicStack,
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IN PVOID InterruptStack)
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{
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{
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ARM_PTE Pte;
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ULONG i;
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PKPCR Pcr;
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ARM_CONTROL_REGISTER ControlRegister;
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/* Set the Current Thread */
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Pcr->PrcbData.CurrentThread = IdleThread;
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//
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/* Set pointers to ourselves */
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// Detect ARM version (Architecture 6 is the ARMv5TE-J, go figure!)
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Pcr->Self = (PKPCR)Pcr;
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//
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Pcr->Prcb = &Pcr->PrcbData;
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KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture == 7;
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//
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// Set the number of TLB entries and ASIDs
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//
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KeNumberTbEntries = 64;
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if (__ARMV6__)
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{
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//
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// 256 ASIDs on v6/v7
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//
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KeNumberProcessIds = 256;
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}
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else
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{
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//
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// The TLB is VIVT on v4/v5
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//
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KeNumberProcessIds = 0;
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}
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//
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// Flush the TLB
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//
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KeFlushTb();
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//
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// Build the KIPCR pte
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//
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Pte.L1.Section.Type = SectionPte;
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Pte.L1.Section.Buffered = FALSE;
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Pte.L1.Section.Cached = FALSE;
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Pte.L1.Section.Reserved = 1; // ARM926EJ-S manual recommends setting to 1
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Pte.L1.Section.Domain = Domain0;
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Pte.L1.Section.Access = SupervisorAccess;
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Pte.L1.Section.BaseAddress = LoaderBlock->u.Arm.PcrPage;
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Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0;
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//
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// Map it into kernel address space by locking it into the TLB
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//
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KeFillFixedEntryTb(Pte, (PVOID)KIPCR, PCR_ENTRY);
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//
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/* Set the PCR Version */
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// Now map the PCR into user address space as well (read-only)
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Pcr->MajorVersion = PCR_MAJOR_VERSION;
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//
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Pcr->MinorVersion = PCR_MINOR_VERSION;
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Pte.L1.Section.Access = SharedAccess;
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KeFillFixedEntryTb(Pte, (PVOID)USPCR, PCR_ENTRY + 1);
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//
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// Now we should be able to use the PCR...
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//
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Pcr = (PKPCR)KeGetPcr();
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//
|
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// Set the cache policy (HACK)
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//
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Pcr->CachePolicy = 0;
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Pcr->AlignedCachePolicy = 0;
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//
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// Copy cache information from the loader block
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//
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Pcr->FirstLevelDcacheSize = LoaderBlock->u.Arm.FirstLevelDcacheSize;
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Pcr->SecondLevelDcacheSize = LoaderBlock->u.Arm.SecondLevelDcacheSize;
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Pcr->FirstLevelIcacheSize = LoaderBlock->u.Arm.FirstLevelIcacheSize;
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Pcr->SecondLevelIcacheSize = LoaderBlock->u.Arm.SecondLevelIcacheSize;
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Pcr->FirstLevelDcacheFillSize = LoaderBlock->u.Arm.FirstLevelDcacheFillSize;
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Pcr->SecondLevelDcacheFillSize = LoaderBlock->u.Arm.SecondLevelDcacheFillSize;
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Pcr->FirstLevelIcacheFillSize = LoaderBlock->u.Arm.FirstLevelIcacheFillSize;
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Pcr->SecondLevelIcacheFillSize = LoaderBlock->u.Arm.SecondLevelIcacheFillSize;
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//
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/* Set the PCRB Version */
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||||||
// Set global d-cache fill and alignment values
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Pcr->PrcbData.MajorVersion = 1;
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||||||
//
|
Pcr->PrcbData.MinorVersion = 1;
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/* Set the Build Type */
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Pcr->PrcbData.BuildType = 0;
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#ifndef CONFIG_SMP
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||||||
|
Pcr->PrcbData.BuildType |= PRCB_BUILD_UNIPROCESSOR;
|
||||||
|
#endif
|
||||||
|
#if DBG
|
||||||
|
Pcr->PrcbData.BuildType |= PRCB_BUILD_DEBUG;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set the Processor Number and current Processor Mask */
|
||||||
|
Pcr->PrcbData.Number = (UCHAR)ProcessorNumber;
|
||||||
|
Pcr->PrcbData.SetMember = 1 << ProcessorNumber;
|
||||||
|
|
||||||
|
/* Set the PRCB for this Processor */
|
||||||
|
KiProcessorBlock[ProcessorNumber] = Pcr->Prcb;
|
||||||
|
|
||||||
|
/* Start us out at PASSIVE_LEVEL */
|
||||||
|
Pcr->Irql = PASSIVE_LEVEL;
|
||||||
|
|
||||||
|
/* Set the stacks */
|
||||||
|
Pcr->PanicStack = PanicStack;
|
||||||
|
Pcr->InterruptStack = InterruptStack;
|
||||||
|
|
||||||
|
/* Setup the processor set */
|
||||||
|
Pcr->PrcbData.MultiThreadProcessorSet = Pcr->PrcbData.SetMember;
|
||||||
|
|
||||||
|
/* Copy cache information from the loader block */
|
||||||
|
Pcr->FirstLevelDcacheSize = KeLoaderBlock->u.Arm.FirstLevelDcacheSize;
|
||||||
|
Pcr->SecondLevelDcacheSize = KeLoaderBlock->u.Arm.SecondLevelDcacheSize;
|
||||||
|
Pcr->FirstLevelIcacheSize = KeLoaderBlock->u.Arm.FirstLevelIcacheSize;
|
||||||
|
Pcr->SecondLevelIcacheSize = KeLoaderBlock->u.Arm.SecondLevelIcacheSize;
|
||||||
|
Pcr->FirstLevelDcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelDcacheFillSize;
|
||||||
|
Pcr->SecondLevelDcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelDcacheFillSize;
|
||||||
|
Pcr->FirstLevelIcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelIcacheFillSize;
|
||||||
|
Pcr->SecondLevelIcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelIcacheFillSize;
|
||||||
|
|
||||||
|
/* Set global d-cache fill and alignment values */
|
||||||
if (!Pcr->SecondLevelDcacheSize)
|
if (!Pcr->SecondLevelDcacheSize)
|
||||||
{
|
{
|
||||||
//
|
/* Use the first level */
|
||||||
// Use the first level
|
|
||||||
//
|
|
||||||
Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize;
|
Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
//
|
/* Use the second level */
|
||||||
// Use the second level
|
|
||||||
//
|
|
||||||
Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize;
|
Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize;
|
||||||
}
|
}
|
||||||
|
|
||||||
//
|
/* Set the alignment */
|
||||||
// Set the alignment
|
|
||||||
//
|
|
||||||
Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1;
|
Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1;
|
||||||
|
|
||||||
//
|
/* Set global i-cache fill and alignment values */
|
||||||
// Set global i-cache fill and alignment values
|
|
||||||
//
|
|
||||||
if (!Pcr->SecondLevelIcacheSize)
|
if (!Pcr->SecondLevelIcacheSize)
|
||||||
{
|
{
|
||||||
//
|
/* Use the first level */
|
||||||
// Use the first level
|
|
||||||
//
|
|
||||||
Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize;
|
Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
//
|
/* Use the second level */
|
||||||
// Use the second level
|
|
||||||
//
|
|
||||||
Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize;
|
Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize;
|
||||||
}
|
}
|
||||||
|
|
||||||
//
|
/* Set the alignment */
|
||||||
// Set the alignment
|
|
||||||
//
|
|
||||||
Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1;
|
Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1;
|
||||||
|
|
||||||
//
|
/* Set processor information */
|
||||||
// Now sweep caches
|
Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong;
|
||||||
//
|
|
||||||
|
/* Set all interrupt routines to unexpected interrupts as well */
|
||||||
|
for (i = 0; i < MAXIMUM_VECTOR; i++)
|
||||||
|
{
|
||||||
|
/* Point to the same template */
|
||||||
|
Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set default stall factor */
|
||||||
|
Pcr->StallScaleFactor = 50;
|
||||||
|
|
||||||
|
/* Setup software interrupts */
|
||||||
|
Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease;
|
||||||
|
Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt;
|
||||||
|
Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt;
|
||||||
|
Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) |
|
||||||
|
(1 << APC_LEVEL) |
|
||||||
|
(1 << DISPATCH_LEVEL) |
|
||||||
|
(1 << IPI_LEVEL);
|
||||||
|
}
|
||||||
|
|
||||||
|
VOID
|
||||||
|
KiInitializeMachineType(VOID)
|
||||||
|
{
|
||||||
|
/* Detect ARM version */
|
||||||
|
KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture >= 7;
|
||||||
|
|
||||||
|
/* Set the number of TLB entries and ASIDs */
|
||||||
|
KeNumberTbEntries = 64;
|
||||||
|
if (__ARMV6__)
|
||||||
|
{
|
||||||
|
/* 256 ASIDs on v6/v7 */
|
||||||
|
KeNumberProcessIds = 256;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* The TLB is VIVT on v4/v5 */
|
||||||
|
KeNumberProcessIds = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
VOID
|
||||||
|
KiInitializeSystem(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||||
|
{
|
||||||
|
ULONG Cpu;
|
||||||
|
PKTHREAD InitialThread;
|
||||||
|
PKPROCESS InitialProcess;
|
||||||
|
ARM_CONTROL_REGISTER ControlRegister;
|
||||||
|
PKIPCR Pcr = (PKIPCR)KeGetPcr();
|
||||||
|
PKTHREAD Thread;
|
||||||
|
|
||||||
|
/* Flush the TLB */
|
||||||
|
KeFlushTb();
|
||||||
|
|
||||||
|
/* Save the loader block and get the current CPU */
|
||||||
|
KeLoaderBlock = LoaderBlock;
|
||||||
|
Cpu = KeNumberProcessors;
|
||||||
|
|
||||||
|
/* Save the initial thread and process */
|
||||||
|
InitialThread = (PKTHREAD)LoaderBlock->Thread;
|
||||||
|
InitialProcess = (PKPROCESS)LoaderBlock->Process;
|
||||||
|
|
||||||
|
/* Clean the APC List Head */
|
||||||
|
InitializeListHead(&InitialThread->ApcState.ApcListHead[KernelMode]);
|
||||||
|
|
||||||
|
/* Initialize the machine type */
|
||||||
|
KiInitializeMachineType();
|
||||||
|
|
||||||
|
/* Skip initial setup if this isn't the Boot CPU */
|
||||||
|
if (Cpu) goto AppCpuInit;
|
||||||
|
|
||||||
|
/* Initialize the PCR */
|
||||||
|
RtlZeroMemory(Pcr, PAGE_SIZE);
|
||||||
|
KiInitializePcr(Cpu,
|
||||||
|
Pcr,
|
||||||
|
InitialThread,
|
||||||
|
(PVOID)LoaderBlock->u.Arm.PanicStack,
|
||||||
|
(PVOID)LoaderBlock->u.Arm.InterruptStack);
|
||||||
|
|
||||||
|
/* Now sweep caches */
|
||||||
HalSweepIcache();
|
HalSweepIcache();
|
||||||
HalSweepDcache();
|
HalSweepDcache();
|
||||||
|
|
||||||
//
|
/* Set us as the current process */
|
||||||
// Set PCR version
|
InitialThread->ApcState.Process = InitialProcess;
|
||||||
//
|
|
||||||
Pcr->MinorVersion = PCR_MINOR_VERSION;
|
|
||||||
Pcr->MajorVersion = PCR_MAJOR_VERSION;
|
|
||||||
|
|
||||||
//
|
AppCpuInit:
|
||||||
// Set boot PRCB
|
/* Setup CPU-related fields */
|
||||||
//
|
Pcr->Number = Cpu;
|
||||||
Pcr->Prcb = (PKPRCB)LoaderBlock->Prcb;
|
Pcr->SetMember = 1 << Cpu;
|
||||||
|
Pcr->SetMemberCopy = 1 << Cpu;
|
||||||
|
Pcr->PrcbData.SetMember = 1 << Cpu;
|
||||||
|
|
||||||
//
|
/* Initialize the Processor with HAL */
|
||||||
// Set the different stacks
|
HalInitializeProcessor(Cpu, KeLoaderBlock);
|
||||||
//
|
|
||||||
Pcr->InitialStack = (PVOID)LoaderBlock->KernelStack;
|
/* Set active processors */
|
||||||
Pcr->PanicStack = (PVOID)LoaderBlock->u.Arm.PanicStack;
|
KeActiveProcessors |= Pcr->SetMember;
|
||||||
Pcr->InterruptStack = (PVOID)LoaderBlock->u.Arm.InterruptStack;
|
KeNumberProcessors++;
|
||||||
|
|
||||||
|
/* Check if this is the boot CPU */
|
||||||
|
if (!Cpu)
|
||||||
|
{
|
||||||
|
/* Initialize debugging system */
|
||||||
|
KdInitSystem(0, KeLoaderBlock);
|
||||||
|
|
||||||
|
/* Check for break-in */
|
||||||
|
if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Raise to HIGH_LEVEL */
|
||||||
|
KfRaiseIrql(HIGH_LEVEL);
|
||||||
|
|
||||||
//
|
/* Set the exception address to high */
|
||||||
// Set the current thread
|
|
||||||
//
|
|
||||||
Pcr->CurrentThread = (PKTHREAD)LoaderBlock->Thread;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Set the current IRQL to high
|
|
||||||
//
|
|
||||||
Pcr->CurrentIrql = HIGH_LEVEL;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Set processor information
|
|
||||||
//
|
|
||||||
Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong;
|
|
||||||
Pcr->SystemReserved[0] = KeArmControlRegisterGet().AsUlong;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Set the exception address to high
|
|
||||||
//
|
|
||||||
ControlRegister = KeArmControlRegisterGet();
|
ControlRegister = KeArmControlRegisterGet();
|
||||||
ControlRegister.HighVectors = TRUE;
|
ControlRegister.HighVectors = TRUE;
|
||||||
KeArmControlRegisterSet(ControlRegister);
|
KeArmControlRegisterSet(ControlRegister);
|
||||||
|
|
||||||
//
|
/* Setup the exception vector table */
|
||||||
// Setup the exception vector table
|
|
||||||
//
|
|
||||||
RtlCopyMemory((PVOID)0xFFFF0000, &KiArmVectorTable, 14 * sizeof(PVOID));
|
RtlCopyMemory((PVOID)0xFFFF0000, &KiArmVectorTable, 14 * sizeof(PVOID));
|
||||||
|
|
||||||
//
|
/* Initialize the rest of the kernel now */
|
||||||
// Initialize the rest of the kernel now
|
|
||||||
//
|
|
||||||
KiInitializeKernel((PKPROCESS)LoaderBlock->Process,
|
KiInitializeKernel((PKPROCESS)LoaderBlock->Process,
|
||||||
(PKTHREAD)LoaderBlock->Thread,
|
(PKTHREAD)LoaderBlock->Thread,
|
||||||
(PVOID)LoaderBlock->KernelStack,
|
(PVOID)LoaderBlock->KernelStack,
|
||||||
(PKPRCB)LoaderBlock->Prcb,
|
Pcr->Prcb,
|
||||||
Pcr->Prcb->Number,
|
Pcr->Prcb->Number,
|
||||||
LoaderBlock);
|
KeLoaderBlock);
|
||||||
|
|
||||||
|
/* Set the priority of this thread to 0 */
|
||||||
//
|
Thread = KeGetCurrentThread();
|
||||||
// Jump to idle loop
|
Thread->Priority = 0;
|
||||||
//
|
|
||||||
|
/* Force interrupts enabled and lower IRQL back to DISPATCH_LEVEL */
|
||||||
|
_enable();
|
||||||
|
KfLowerIrql(DISPATCH_LEVEL);
|
||||||
|
|
||||||
|
/* Set the right wait IRQL */
|
||||||
|
Thread->WaitIrql = DISPATCH_LEVEL;
|
||||||
|
|
||||||
|
/* Jump into the idle loop */
|
||||||
KiIdleLoop();
|
KiIdleLoop();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ULONG
|
||||||
|
DbgPrintEarly(const char *fmt, ...)
|
||||||
|
{
|
||||||
|
va_list args;
|
||||||
|
unsigned int i;
|
||||||
|
char Buffer[1024];
|
||||||
|
PCHAR String = Buffer;
|
||||||
|
|
||||||
|
va_start(args, fmt);
|
||||||
|
i = vsprintf(Buffer, fmt, args);
|
||||||
|
va_end(args);
|
||||||
|
|
||||||
|
/* Output the message */
|
||||||
|
while (*String != 0)
|
||||||
|
{
|
||||||
|
if (*String == '\n')
|
||||||
|
{
|
||||||
|
KdPortPutByteEx(NULL, '\r');
|
||||||
|
}
|
||||||
|
KdPortPutByteEx(NULL, *String);
|
||||||
|
String++;
|
||||||
|
}
|
||||||
|
|
||||||
|
return STATUS_SUCCESS;
|
||||||
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue