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- Cleanup some debug-only debug prints.

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- Make the VA-range-printing debug prints match the same format as those in ReactOS Mm (MiDbgKernelLayout).
  - Add the appropriate number of spaces so that the layout appears continuous, even though it's coming from two source files.
  - This makes it easy to see the VA mappings at boot (but not all of them).


svn path=/trunk/; revision=41709
This commit is contained in:
ReactOS Portable Systems Group 2009-06-30 10:38:51 +00:00
parent f91f8ec7cf
commit 15eecb0b40
2 changed files with 25 additions and 21 deletions
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32
reactos/ntoskrnl/mm/ARM3/init.c
View file

@ -338,7 +338,7 @@ MmArmInitSystem(IN ULONG Phase,
} }
} }
DPRINT1("System PTE count has been tuned to %d (%d bytes)\n", DPRINT("System PTE count has been tuned to %d (%d bytes)\n",
MmNumberOfSystemPtes, MmNumberOfSystemPtes * PAGE_SIZE); MmNumberOfSystemPtes, MmNumberOfSystemPtes * PAGE_SIZE);
// //
@ -443,7 +443,7 @@ MmArmInitSystem(IN ULONG Phase,
MmSizeOfNonPagedPoolInBytes); MmSizeOfNonPagedPoolInBytes);
MmNonPagedPoolStart = (PVOID)PAGE_ALIGN(MmNonPagedPoolStart); MmNonPagedPoolStart = (PVOID)PAGE_ALIGN(MmNonPagedPoolStart);
NonPagedPoolExpansionVa = MmNonPagedPoolStart; NonPagedPoolExpansionVa = MmNonPagedPoolStart;
DPRINT1("NP Pool has been tuned to: %d bytes and %d bytes\n", DPRINT("NP Pool has been tuned to: %d bytes and %d bytes\n",
MmSizeOfNonPagedPoolInBytes, MmMaximumNonPagedPoolInBytes); MmSizeOfNonPagedPoolInBytes, MmMaximumNonPagedPoolInBytes);
// //
@ -488,9 +488,6 @@ MmArmInitSystem(IN ULONG Phase,
// //
// Non paged pool comes after the PFN database // Non paged pool comes after the PFN database
// //
DPRINT1("System PTE VA starts at: %p\n", MmNonPagedSystemStart);
DPRINT1("NP Expansion VA begins at: %p and ends at: %p\n",
MmNonPagedPoolStart, MmNonPagedPoolEnd);
MmNonPagedPoolStart = (PVOID)((ULONG_PTR)MmArmPfnDatabase + MmNonPagedPoolStart = (PVOID)((ULONG_PTR)MmArmPfnDatabase +
(MxPfnAllocation << PAGE_SHIFT)); (MxPfnAllocation << PAGE_SHIFT));
@ -505,14 +502,16 @@ MmArmInitSystem(IN ULONG Phase,
BoundaryAddressMultiple, BoundaryAddressMultiple,
FALSE); FALSE);
ASSERT(PageFrameIndex != 0); ASSERT(PageFrameIndex != 0);
DPRINT1("PFN DB VA begins at: %p and ends at: %p\n", DPRINT1(" 0x%p - 0x%p\t%s\n",
MmArmPfnDatabase, MmArmPfnDatabase,
(ULONG_PTR)MmArmPfnDatabase + (MxPfnAllocation << PAGE_SHIFT)); (ULONG_PTR)MmArmPfnDatabase + (MxPfnAllocation << PAGE_SHIFT),
DPRINT1("PFN DB PA PFN begins at: %lx\n", PageFrameIndex); "Shadow PFN Database");
DPRINT1("NP VA begins at: %p and ends at: %p\n", DPRINT("PFN DB PA PFN begins at: %lx\n", PageFrameIndex);
DPRINT1(" 0x%p - 0x%p\t%s\n",
MmNonPagedPoolStart, MmNonPagedPoolStart,
(ULONG_PTR)MmNonPagedPoolStart + MmSizeOfNonPagedPoolInBytes); (ULONG_PTR)MmNonPagedPoolStart + MmSizeOfNonPagedPoolInBytes,
DPRINT1("NP PA PFN begins at: %lx\n", PageFrameIndex + MxPfnAllocation); "ARM Non Paged Pool");
DPRINT("NP PA PFN begins at: %lx\n", PageFrameIndex + MxPfnAllocation);
// //
// Now we need some pages to create the page tables for the NP system VA // Now we need some pages to create the page tables for the NP system VA
@ -582,6 +581,12 @@ MmArmInitSystem(IN ULONG Phase,
// Now remember where the expansion starts // Now remember where the expansion starts
// //
MmNonPagedPoolExpansionStart = NonPagedPoolExpansionVa; MmNonPagedPoolExpansionStart = NonPagedPoolExpansionVa;
DPRINT1(" 0x%p - 0x%p\t%s\n",
MmNonPagedSystemStart, MmNonPagedPoolExpansionStart,
"System PTE Space");
DPRINT1(" 0x%p - 0x%p\t%s\n",
MmNonPagedPoolExpansionStart, MmNonPagedPoolEnd,
"Non Paged Pool Expansion PTE Space");
// //
// Last step is to actually map the nonpaged pool // Last step is to actually map the nonpaged pool
@ -650,7 +655,7 @@ MmArmInitSystem(IN ULONG Phase,
MmNumberOfSystemPtes = MiAddressToPte(MmNonPagedPoolExpansionStart) - MmNumberOfSystemPtes = MiAddressToPte(MmNonPagedPoolExpansionStart) -
PointerPte; PointerPte;
MmNumberOfSystemPtes--; MmNumberOfSystemPtes--;
DPRINT1("Final System PTE count: %d (%d bytes)\n", DPRINT("Final System PTE count: %d (%d bytes)\n",
MmNumberOfSystemPtes, MmNumberOfSystemPtes * PAGE_SIZE); MmNumberOfSystemPtes, MmNumberOfSystemPtes * PAGE_SIZE);
// //
@ -691,7 +696,6 @@ MmArmInitSystem(IN ULONG Phase,
// //
MiFirstReservedZeroingPte = MiReserveSystemPtes(MI_ZERO_PTES, MiFirstReservedZeroingPte = MiReserveSystemPtes(MI_ZERO_PTES,
SystemPteSpace); SystemPteSpace);
DPRINT1("ZERO PTEs are at: %p\n", MiFirstReservedZeroingPte);
RtlZeroMemory(MiFirstReservedZeroingPte, MI_ZERO_PTES * sizeof(MMPTE)); RtlZeroMemory(MiFirstReservedZeroingPte, MI_ZERO_PTES * sizeof(MMPTE));
// //
@ -731,7 +735,7 @@ MmArmInitSystem(IN ULONG Phase,
// //
PPHYSICAL_MEMORY_RUN Run; PPHYSICAL_MEMORY_RUN Run;
Run = &MmPhysicalMemoryBlock->Run[i]; Run = &MmPhysicalMemoryBlock->Run[i];
DPRINT1("PHYSICAL RAM [0x%08p to 0x%08p]\n", DPRINT("PHYSICAL RAM [0x%08p to 0x%08p]\n",
Run->BasePage << PAGE_SHIFT, Run->BasePage << PAGE_SHIFT,
(Run->BasePage + Run->PageCount) << PAGE_SHIFT); (Run->BasePage + Run->PageCount) << PAGE_SHIFT);
} }

2
reactos/ntoskrnl/mm/ARM3/syspte.c
View file

@ -339,7 +339,7 @@ MiInitializeSystemPtes(IN PMMPTE StartingPte,
MmSystemPteBase = (PVOID)PAGETABLE_MAP; MmSystemPteBase = (PVOID)PAGETABLE_MAP;
MmSystemPtesStart[PoolType] = StartingPte; MmSystemPtesStart[PoolType] = StartingPte;
MmSystemPtesEnd[PoolType] = StartingPte + NumberOfPtes - 1; MmSystemPtesEnd[PoolType] = StartingPte + NumberOfPtes - 1;
DPRINT1("System PTE space for %d starting at: %p and ending at: %p\n", DPRINT("System PTE space for %d starting at: %p and ending at: %p\n",
PoolType, MmSystemPtesStart[PoolType], MmSystemPtesEnd[PoolType]); PoolType, MmSystemPtesStart[PoolType], MmSystemPtesEnd[PoolType]);
// //