mirror of
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- Move more stuff to wdm.h
- Add PCI_DISABLE_LEVEL_INTERRUPT, PCI_STATUS_DETECTED_PARITY_ERROR, PCI_SUBCLASS_NET_ISDN_CTLR, PCI_SUBCLASS_BR_RACEWAY and several missing PCI_CLASS_* definitions svn path=/branches/header-work/; revision=45744
This commit is contained in:
Amine Khaldi
parent
44e57fdff5
commit
15be67bafc
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@ -1586,6 +1586,23 @@ typedef struct _ACCESS_STATE {
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* Configuration Manager Types *
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******************************************************************************/
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/* KEY_VALUE_Xxx.Type */
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#define REG_NONE 0
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#define REG_SZ 1
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#define REG_EXPAND_SZ 2
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#define REG_BINARY 3
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#define REG_DWORD 4
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#define REG_DWORD_LITTLE_ENDIAN 4
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#define REG_DWORD_BIG_ENDIAN 5
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#define REG_LINK 6
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#define REG_MULTI_SZ 7
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#define REG_RESOURCE_LIST 8
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#define REG_FULL_RESOURCE_DESCRIPTOR 9
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#define REG_RESOURCE_REQUIREMENTS_LIST 10
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#define REG_QWORD 11
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#define REG_QWORD_LITTLE_ENDIAN 11
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//
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// Registry Access Rights
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//
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@ -2158,6 +2175,159 @@ IoMapTransfer(
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}
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#endif
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/* PCI_COMMON_CONFIG.Command */
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#define PCI_ENABLE_IO_SPACE 0x0001
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#define PCI_ENABLE_MEMORY_SPACE 0x0002
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#define PCI_ENABLE_BUS_MASTER 0x0004
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#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
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#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
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#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
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#define PCI_ENABLE_PARITY 0x0040
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#define PCI_ENABLE_WAIT_CYCLE 0x0080
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#define PCI_ENABLE_SERR 0x0100
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#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
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#define PCI_DISABLE_LEVEL_INTERRUPT 0x0400
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/* PCI_COMMON_CONFIG.Status */
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#define PCI_STATUS_INTERRUPT_PENDING 0x0008
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#define PCI_STATUS_CAPABILITIES_LIST 0x0010
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#define PCI_STATUS_66MHZ_CAPABLE 0x0020
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#define PCI_STATUS_UDF_SUPPORTED 0x0040
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#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
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#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
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#define PCI_STATUS_DEVSEL 0x0600
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#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
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#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
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#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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/* PCI_COMMON_CONFIG.HeaderType */
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#define PCI_MULTIFUNCTION 0x80
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#define PCI_DEVICE_TYPE 0x00
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#define PCI_BRIDGE_TYPE 0x01
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#define PCI_CARDBUS_BRIDGE_TYPE 0x02
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#define PCI_CONFIGURATION_TYPE(PciData) \
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(((PPCI_COMMON_CONFIG) (PciData))->HeaderType & ~PCI_MULTIFUNCTION)
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#define PCI_MULTIFUNCTION_DEVICE(PciData) \
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((((PPCI_COMMON_CONFIG) (PciData))->HeaderType & PCI_MULTIFUNCTION) != 0)
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/* PCI device classes */
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#define PCI_CLASS_PRE_20 0x00
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#define PCI_CLASS_MASS_STORAGE_CTLR 0x01
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#define PCI_CLASS_NETWORK_CTLR 0x02
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#define PCI_CLASS_DISPLAY_CTLR 0x03
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#define PCI_CLASS_MULTIMEDIA_DEV 0x04
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#define PCI_CLASS_MEMORY_CTLR 0x05
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#define PCI_CLASS_BRIDGE_DEV 0x06
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#define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07
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#define PCI_CLASS_BASE_SYSTEM_DEV 0x08
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#define PCI_CLASS_INPUT_DEV 0x09
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#define PCI_CLASS_DOCKING_STATION 0x0a
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#define PCI_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_SERIAL_BUS_CTLR 0x0c
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#define PCI_CLASS_WIRELESS_CTLR 0x0d
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#define PCI_CLASS_INTELLIGENT_IO_CTLR 0x0e
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#define PCI_CLASS_SATELLITE_COMMS_CTLR 0x0f
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#define PCI_CLASS_ENCRYPTION_DECRYPTION 0x10
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#define PCI_CLASS_DATA_ACQ_SIGNAL_PROC 0x11
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/* PCI device subclasses for class 0 */
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#define PCI_SUBCLASS_PRE_20_NON_VGA 0x00
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#define PCI_SUBCLASS_PRE_20_VGA 0x01
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/* PCI device subclasses for class 1 (mass storage controllers)*/
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#define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00
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#define PCI_SUBCLASS_MSC_IDE_CTLR 0x01
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#define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02
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#define PCI_SUBCLASS_MSC_IPI_CTLR 0x03
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#define PCI_SUBCLASS_MSC_RAID_CTLR 0x04
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#define PCI_SUBCLASS_MSC_OTHER 0x80
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/* PCI device subclasses for class 2 (network controllers)*/
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#define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00
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#define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01
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#define PCI_SUBCLASS_NET_FDDI_CTLR 0x02
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#define PCI_SUBCLASS_NET_ATM_CTLR 0x03
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#define PCI_SUBCLASS_NET_ISDN_CTLR 0x04
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#define PCI_SUBCLASS_NET_OTHER 0x80
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/* PCI device subclasses for class 3 (display controllers)*/
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#define PCI_SUBCLASS_VID_VGA_CTLR 0x00
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#define PCI_SUBCLASS_VID_XGA_CTLR 0x01
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#define PCI_SUBCLASS_VID_3D_CTLR 0x02
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#define PCI_SUBCLASS_VID_OTHER 0x80
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/* PCI device subclasses for class 4 (multimedia device)*/
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#define PCI_SUBCLASS_MM_VIDEO_DEV 0x00
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#define PCI_SUBCLASS_MM_AUDIO_DEV 0x01
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#define PCI_SUBCLASS_MM_TELEPHONY_DEV 0x02
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#define PCI_SUBCLASS_MM_OTHER 0x80
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/* PCI device subclasses for class 5 (memory controller)*/
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#define PCI_SUBCLASS_MEM_RAM 0x00
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#define PCI_SUBCLASS_MEM_FLASH 0x01
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#define PCI_SUBCLASS_MEM_OTHER 0x80
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/* PCI device subclasses for class 6 (bridge device)*/
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#define PCI_SUBCLASS_BR_HOST 0x00
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#define PCI_SUBCLASS_BR_ISA 0x01
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#define PCI_SUBCLASS_BR_EISA 0x02
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#define PCI_SUBCLASS_BR_MCA 0x03
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#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
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#define PCI_SUBCLASS_BR_PCMCIA 0x05
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#define PCI_SUBCLASS_BR_NUBUS 0x06
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#define PCI_SUBCLASS_BR_CARDBUS 0x07
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#define PCI_SUBCLASS_BR_RACEWAY 0x08
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#define PCI_SUBCLASS_BR_OTHER 0x80
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/* PCI device subclasses for class C (serial bus controller)*/
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#define PCI_SUBCLASS_SB_IEEE1394 0x00
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#define PCI_SUBCLASS_SB_ACCESS 0x01
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#define PCI_SUBCLASS_SB_SSA 0x02
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#define PCI_SUBCLASS_SB_USB 0x03
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#define PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04
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#define PCI_SUBCLASS_SB_SMBUS 0x05
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_MAX_BRIDGE_NUMBER 0xFF
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#define PCI_INVALID_VENDORID 0xFFFF
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#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET(PCI_COMMON_CONFIG, DeviceSpecific))
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#define PCI_ADDRESS_IO_SPACE 0x00000001
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#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006
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#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008
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#define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc
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#define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0
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#define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800
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#define PCI_TYPE_32BIT 0
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#define PCI_TYPE_20BIT 2
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#define PCI_TYPE_64BIT 4
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#define POOL_COLD_ALLOCATION 256
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#define POOL_QUOTA_FAIL_INSTEAD_OF_RAISE 8
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#define POOL_RAISE_IF_ALLOCATION_FAILURE 16
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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#define PCI_TYPE2_ADDRESSES 5
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#define IO_TYPE_ADAPTER 1
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#define IO_TYPE_CONTROLLER 2
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#define IO_TYPE_DEVICE 3
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@ -2295,6 +2465,17 @@ IoMapTransfer(
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#define FILE_DEVICE_BIOMETRIC 0x00000044
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#define FILE_DEVICE_PMI 0x00000045
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typedef struct _PCI_SLOT_NUMBER {
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union {
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struct {
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ULONG DeviceNumber : 5;
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ULONG FunctionNumber : 3;
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ULONG Reserved : 24;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
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typedef struct _IO_STATUS_BLOCK {
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_ANONYMOUS_UNION union {
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NTSTATUS Status;
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@ -1124,27 +1124,6 @@ typedef struct _KEY_USER_FLAGS_INFORMATION {
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ULONG UserFlags;
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} KEY_USER_FLAGS_INFORMATION, *PKEY_USER_FLAGS_INFORMATION;
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/* KEY_VALUE_Xxx.Type */
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#define REG_NONE 0
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#define REG_SZ 1
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#define REG_EXPAND_SZ 2
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#define REG_BINARY 3
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#define REG_DWORD 4
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#define REG_DWORD_LITTLE_ENDIAN 4
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#define REG_DWORD_BIG_ENDIAN 5
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#define REG_LINK 6
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#define REG_MULTI_SZ 7
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#define REG_RESOURCE_LIST 8
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#define REG_FULL_RESOURCE_DESCRIPTOR 9
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#define REG_RESOURCE_REQUIREMENTS_LIST 10
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#define REG_QWORD 11
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#define REG_QWORD_LITTLE_ENDIAN 11
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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#define PCI_TYPE2_ADDRESSES 5
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typedef struct _PCI_COMMON_CONFIG {
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USHORT VendorID;
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USHORT DeviceID;
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@ -1218,157 +1197,8 @@ typedef struct _PCI_COMMON_CONFIG {
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UCHAR DeviceSpecific[192];
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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/* PCI_COMMON_CONFIG.Command */
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#define PCI_ENABLE_IO_SPACE 0x0001
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#define PCI_ENABLE_MEMORY_SPACE 0x0002
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#define PCI_ENABLE_BUS_MASTER 0x0004
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#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
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#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
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#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
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#define PCI_ENABLE_PARITY 0x0040
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#define PCI_ENABLE_WAIT_CYCLE 0x0080
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#define PCI_ENABLE_SERR 0x0100
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#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
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/* PCI_COMMON_CONFIG.Status */
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#define PCI_STATUS_CAPABILITIES_LIST 0x0010
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#define PCI_STATUS_66MHZ_CAPABLE 0x0020
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#define PCI_STATUS_UDF_SUPPORTED 0x0040
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#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
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#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
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#define PCI_STATUS_DEVSEL 0x0600
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#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
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#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
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#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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/* PCI_COMMON_CONFIG.HeaderType */
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#define PCI_MULTIFUNCTION 0x80
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#define PCI_DEVICE_TYPE 0x00
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#define PCI_BRIDGE_TYPE 0x01
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#define PCI_CARDBUS_BRIDGE_TYPE 0x02
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#define PCI_CONFIGURATION_TYPE(PciData) \
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(((PPCI_COMMON_CONFIG) (PciData))->HeaderType & ~PCI_MULTIFUNCTION)
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#define PCI_MULTIFUNCTION_DEVICE(PciData) \
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((((PPCI_COMMON_CONFIG) (PciData))->HeaderType & PCI_MULTIFUNCTION) != 0)
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/* PCI device classes */
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#define PCI_CLASS_PRE_20 0x00
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#define PCI_CLASS_MASS_STORAGE_CTLR 0x01
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#define PCI_CLASS_NETWORK_CTLR 0x02
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#define PCI_CLASS_DISPLAY_CTLR 0x03
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#define PCI_CLASS_MULTIMEDIA_DEV 0x04
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#define PCI_CLASS_MEMORY_CTLR 0x05
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#define PCI_CLASS_BRIDGE_DEV 0x06
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#define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07
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#define PCI_CLASS_BASE_SYSTEM_DEV 0x08
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#define PCI_CLASS_INPUT_DEV 0x09
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#define PCI_CLASS_DOCKING_STATION 0x0a
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#define PCI_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_SERIAL_BUS_CTLR 0x0c
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/* PCI device subclasses for class 0 */
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#define PCI_SUBCLASS_PRE_20_NON_VGA 0x00
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#define PCI_SUBCLASS_PRE_20_VGA 0x01
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/* PCI device subclasses for class 1 (mass storage controllers)*/
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#define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00
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#define PCI_SUBCLASS_MSC_IDE_CTLR 0x01
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#define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02
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#define PCI_SUBCLASS_MSC_IPI_CTLR 0x03
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#define PCI_SUBCLASS_MSC_RAID_CTLR 0x04
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#define PCI_SUBCLASS_MSC_OTHER 0x80
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/* PCI device subclasses for class 2 (network controllers)*/
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#define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00
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#define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01
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#define PCI_SUBCLASS_NET_FDDI_CTLR 0x02
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#define PCI_SUBCLASS_NET_ATM_CTLR 0x03
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#define PCI_SUBCLASS_NET_OTHER 0x80
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/* PCI device subclasses for class 3 (display controllers)*/
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#define PCI_SUBCLASS_VID_VGA_CTLR 0x00
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#define PCI_SUBCLASS_VID_XGA_CTLR 0x01
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#define PCI_SUBCLASS_VID_3D_CTLR 0x02
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#define PCI_SUBCLASS_VID_OTHER 0x80
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/* PCI device subclasses for class 4 (multimedia device)*/
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#define PCI_SUBCLASS_MM_VIDEO_DEV 0x00
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#define PCI_SUBCLASS_MM_AUDIO_DEV 0x01
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#define PCI_SUBCLASS_MM_TELEPHONY_DEV 0x02
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#define PCI_SUBCLASS_MM_OTHER 0x80
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/* PCI device subclasses for class 5 (memory controller)*/
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#define PCI_SUBCLASS_MEM_RAM 0x00
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#define PCI_SUBCLASS_MEM_FLASH 0x01
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#define PCI_SUBCLASS_MEM_OTHER 0x80
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/* PCI device subclasses for class 6 (bridge device)*/
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#define PCI_SUBCLASS_BR_HOST 0x00
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#define PCI_SUBCLASS_BR_ISA 0x01
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#define PCI_SUBCLASS_BR_EISA 0x02
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#define PCI_SUBCLASS_BR_MCA 0x03
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#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
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#define PCI_SUBCLASS_BR_PCMCIA 0x05
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#define PCI_SUBCLASS_BR_NUBUS 0x06
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#define PCI_SUBCLASS_BR_CARDBUS 0x07
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#define PCI_SUBCLASS_BR_OTHER 0x80
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/* PCI device subclasses for class C (serial bus controller)*/
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#define PCI_SUBCLASS_SB_IEEE1394 0x00
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#define PCI_SUBCLASS_SB_ACCESS 0x01
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#define PCI_SUBCLASS_SB_SSA 0x02
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#define PCI_SUBCLASS_SB_USB 0x03
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#define PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04
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#define PCI_SUBCLASS_SB_SMBUS 0x05
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_MAX_BRIDGE_NUMBER 0xFF
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#define PCI_INVALID_VENDORID 0xFFFF
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#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET(PCI_COMMON_CONFIG, DeviceSpecific))
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#define PCI_ADDRESS_MEMORY_SPACE 0x00000000
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#define PCI_ADDRESS_IO_SPACE 0x00000001
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#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006
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#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008
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#define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc
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#define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0
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#define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800
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#define PCI_TYPE_32BIT 0
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#define PCI_TYPE_20BIT 2
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#define PCI_TYPE_64BIT 4
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typedef struct _PCI_SLOT_NUMBER {
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union {
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struct {
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ULONG DeviceNumber : 5;
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ULONG FunctionNumber : 3;
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ULONG Reserved : 24;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
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#define POOL_COLD_ALLOCATION 256
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#define POOL_QUOTA_FAIL_INSTEAD_OF_RAISE 8
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#define POOL_RAISE_IF_ALLOCATION_FAILURE 16
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typedef struct _OSVERSIONINFOA {
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ULONG dwOSVersionInfoSize;
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