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[FREELDR] Fix some more register accesses and magic values

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Addendum to 764e884.
This commit is contained in:
Stanislav Motylkov 2020-05-08 23:02:42 +03:00
parent 49040fa54c
commit 10e52f68b2
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GPG key ID: AFE513258CBA9E92
3 changed files with 11 additions and 8 deletions
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4
boot/freeldr/freeldr/arch/i386/xbox/machxbox.c
View file

@ -261,8 +261,8 @@ MachInit(const char *CmdLine)
/* Check for Xbox by identifying device at PCI 0:0:0, if it's
* 0x10DE/0x02A5 then we're running on an Xbox */
WRITE_PORT_ULONG((ULONG *)0xCF8, CONFIG_CMD(0, 0, 0));
PciId = READ_PORT_ULONG((ULONG *)0xCFC);
WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(0, 0, 0));
PciId = READ_PORT_ULONG((PULONG)0xCFC);
if (PciId != 0x02A510DE)
{
ERR("This is not original Xbox!\n");

13
boot/freeldr/freeldr/arch/i386/xbox/xboxmem.c
View file

@ -60,11 +60,12 @@ XboxMemInit(VOID)
PVOID MembaseTop = (PVOID)(64 * 1024 * 1024);
PVOID MembaseLow = (PVOID)0;
(*(PULONG)(0xfd000000 + 0x100200)) = 0x03070103;
(*(PULONG)(0xfd000000 + 0x100204)) = 0x11448000;
WRITE_REGISTER_ULONG((PULONG)NV2A_FB_CFG0, 0x03070103);
WRITE_REGISTER_ULONG((PULONG)NV2A_FB_CFG0 + 4, 0x11448000);
WRITE_PORT_ULONG((ULONG*) 0xcf8, CONFIG_CMD(0, 0, 0x84));
WRITE_PORT_ULONG((ULONG*) 0xcfc, 0x7ffffff); /* Prep hardware for 128 Mb */
/* Prep hardware for 128 Mb */
WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(0, 0, 0x84));
WRITE_PORT_ULONG((PULONG)0xCFC, 0x7FFFFFF);
InstalledMemoryMb = 64;
memset(ControlRegion, TEST_PATTERN1, TEST_SIZE);
@ -93,8 +94,8 @@ XboxMemInit(VOID)
}
/* Set hardware for amount of memory detected */
WRITE_PORT_ULONG((ULONG*) 0xcf8, CONFIG_CMD(0, 0, 0x84));
WRITE_PORT_ULONG((ULONG*) 0xcfc, InstalledMemoryMb * 1024 * 1024 - 1);
WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(0, 0, 0x84));
WRITE_PORT_ULONG((PULONG)0xCFC, InstalledMemoryMb * 1024 * 1024 - 1);
AvailableMemoryMb = InstalledMemoryMb;
}

2
boot/freeldr/freeldr/include/arch/i386/machxbox.h
View file

@ -38,6 +38,8 @@
#define LPC_CONFIG_DEVICE_INTERRUPT 0x70
#define NV2A_CONTROL_OFFSET 0xFD000000
#define NV2A_FB_OFFSET (0x100000 + NV2A_CONTROL_OFFSET)
#define NV2A_FB_CFG0 (0x200 + NV2A_FB_OFFSET)
#define NV2A_CRTC_OFFSET (0x600000 + NV2A_CONTROL_OFFSET)
#define NV2A_CRTC_FRAMEBUFFER_START (0x800 + NV2A_CRTC_OFFSET)
#define NV2A_CRTC_REGISTER_INDEX (0x13D4 + NV2A_CRTC_OFFSET)