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[NTOSKRNL/MM/AMD64]
- Add MI_REAL_SYSTEM_RANGE_START, which is the canonical system space base address, while MmSystemRangeStart variable contains a broken value, like on Windows. - Define MmSystemRangeStart to MI_REAL_SYSTEM_RANGE_START, since on amd64 there is no dynamic system space start address and we don't want to use the broken address anywhere - Add some more address layout definitions - Add MiIsPteOnP*eBoundary() macro - Add MMPPE, MI_WRITE_VALID_PPE and ValidKernelPpe definitions - Fix initialization of PrototypePte - Add mappings for VAD bitmap and working set list to MiInitializePageTable - Fix calculations in MiBuildNonPagedPool - Improve MiBuildSystemPteSpace - Implement MiBuildPfnDatabase, MiAddDescriptorToDatabase, MiBuildPfnDatabaseFromPageTables, MiSetupPfnForPageTable all of these are written to be portable, yet they are untested on anything else than amd64 builds - Mostly finish MiInitMachineDependent svn path=/trunk/; revision=55403
This commit is contained in:
Timo Kreuzer
parent
adffed162f
commit
0fcb7d138d
2 changed files with 395 additions and 63 deletions
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@ -8,29 +8,39 @@
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#define MI_HIGHEST_USER_ADDRESS (PVOID)0x000007FFFFFEFFFFULL
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#define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL
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#define MI_REAL_SYSTEM_RANGE_START 0xFFFF800000000000ULL
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#define MI_PAGE_TABLE_BASE 0xFFFFF68000000000ULL
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#define HYPER_SPACE 0xFFFFF70000000000ULL
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#define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
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#define MI_SESSION_SPACE_MINIMUM (PVOID)0xFFFFF90000000000ULL
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#define MI_SESSION_VIEW_END (PVOID)0xFFFFF97FFF000000ULL
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#define MI_SESSION_SPACE_END (PVOID)0xFFFFF98000000000ULL
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#define MI_SYSTEM_PTE_START (PVOID)0xFFFFFAA000000000ULL
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#define MI_PAGED_POOL_START (PVOID)0xFFFFFA8000000000ULL
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#define MI_NON_PAGED_SYSTEM_START_MIN 0xFFFFFAA000000000ULL
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#define MI_PFN_DATABASE (PVOID)0xFFFFFAC000000000ULL
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#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
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#define MI_SHARED_SYSTEM_PAGE 0xFFFFF78000000000ULL
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#define MI_SYSTEM_CACHE_WS_START 0xFFFFF78000001000ULL
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#define MI_LOADER_MAPPINGS 0xFFFFF80000000000ULL
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#define MI_PAGED_SYSTEM_START 0xFFFFF88000000000ULL
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#define MI_PAGED_POOL_START (PVOID)0xFFFFF8A000000000ULL
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#define MI_PAGED_POOL_END 0xFFFFF8BFFFFFFFFFULL
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#define MI_SESSION_SPACE_START 0xFFFFF90000000000ULL
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#define MI_SESSION_VIEW_END 0xFFFFF97FFF000000ULL
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#define MI_SESSION_SPACE_END 0xFFFFF97FFFFFFFFFULL
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#define MM_SYSTEM_SPACE_START 0xFFFFF98000000000ULL
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#define MI_PFN_DATABASE 0xFFFFFA8000000000ULL
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#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
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#define MI_SYSTEM_CACHE_WS_START (PVOID)0xFFFFF78000001000ULL // CHECKME
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/* WOW64 address definitions */
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#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
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#define MM_SYSTEM_RANGE_START_WOW64 0x80000000
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#define MI_SYSTEM_PTE_END (PVOID)((ULONG64)MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
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#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME
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#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START
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#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
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#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE)
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#define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define MI_MAPPING_RANGE_START (ULONG64)HYPER_SPACE
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#define MI_MAPPING_RANGE_START HYPER_SPACE
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_DUMMY_PTE (MI_MAPPING_RANGE_END + PAGE_SIZE)
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#define MI_VAD_BITMAP (MI_DUMMY_PTE + PAGE_SIZE)
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#define MI_WORKING_SET_LIST (MI_VAD_BITMAP + PAGE_SIZE)
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#define MI_NONPAGED_POOL_END 0
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/* Memory sizes */
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
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@ -55,6 +65,8 @@
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
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/* Misc constants */
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#define _MI_PAGING_LEVELS 4
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#define MI_NUMBER_SYSTEM_PTES 22000
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@ -63,9 +75,6 @@
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#define NR_SECTION_PAGE_ENTRIES 1024
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + PAGE_SIZE)
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#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + PAGE_SIZE)
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#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + PAGE_SIZE)
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/* FIXME - different architectures have different cache line sizes... */
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#define MM_CACHE_LINE_SIZE 32
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@ -75,6 +84,13 @@
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#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
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#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
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#define MiIsPteOnPdeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPpeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPxeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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/* MMPTE related defines */
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#define MM_EMPTY_PTE_LIST ((ULONG64)0xFFFFFFFF)
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#define MM_EMPTY_LIST ((ULONG_PTR)-1)
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@ -129,6 +145,11 @@
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/* On x86, these two are the same */
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#define MMPDE MMPTE
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#define PMMPDE PMMPTE
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#define MMPPE MMPTE
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#define PMMPPE PMMPTE
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#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
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#define ValidKernelPpe ValidKernelPde
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PULONG64
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FORCEINLINE
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@ -32,13 +32,12 @@ MMPTE DemandZeroPte = {{MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS}};
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/* Template PTE for prototype page */
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MMPTE PrototypePte = {{(MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS) |
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PTE_PROTOTYPE | (MI_PTE_LOOKUP_NEEDED << PAGE_SHIFT)}};
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/* Sizes */
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SIZE_T MiNonPagedSystemSize;
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PTE_PROTOTYPE | (MI_PTE_LOOKUP_NEEDED << 32)}};
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/* Address ranges */
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PVOID MiSessionViewEnd;
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PVOID MiSystemPteSpaceStart;
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PVOID MiSystemPteSpaceEnd;
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ULONG64 MxPfnSizeInBytes;
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BOOLEAN MiIncludeType[LoaderMaximum];
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@ -69,7 +68,7 @@ MiInitializeSessionSpaceLayout()
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/* The view starts right below the session working set (itself below
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* the image area) */
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MiSessionViewEnd = MI_SESSION_VIEW_END;
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MiSessionViewEnd = (PVOID)MI_SESSION_VIEW_END;
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MiSessionViewStart = (PCHAR)MiSessionViewEnd - MmSessionViewSize;
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ASSERT(IS_PAGE_ALIGNED(MiSessionViewStart));
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@ -110,7 +109,7 @@ MiMapPPEs(
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{
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/* No, map it! */
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TmplPde.u.Hard.PageFrameNumber = MxGetNextPage(1);
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*PointerPpe = TmplPde;
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MI_WRITE_VALID_PTE(PointerPpe, TmplPde);
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/* Zero out the page table */
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RtlZeroMemory(MiPteToAddress(PointerPpe), PAGE_SIZE);
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@ -137,7 +136,7 @@ MiMapPDEs(
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{
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/* No, map it! */
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TmplPde.u.Hard.PageFrameNumber = MxGetNextPage(1);
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*PointerPde = TmplPde;
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MI_WRITE_VALID_PTE(PointerPde, TmplPde);
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/* Zero out the page table */
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RtlZeroMemory(MiPteToAddress(PointerPde), PAGE_SIZE);
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@ -164,7 +163,10 @@ MiMapPTEs(
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{
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/* No, map it! */
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TmplPte.u.Hard.PageFrameNumber = MxGetNextPage(1);
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*PointerPte = TmplPte;
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MI_WRITE_VALID_PTE(PointerPte, TmplPte);
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/* Zero out the page (FIXME: not always neccessary) */
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RtlZeroMemory(MiPteToAddress(PointerPte), PAGE_SIZE);
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}
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}
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}
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@ -212,10 +214,10 @@ MiInitializePageTable()
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HyperTemplatePte = TmplPte;
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/* Create PDPTs (72 KB) for shared system address space,
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* skip page tables and hyperspace */
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* skip page tables TODO: use global pages. */
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/* Loop the PXEs */
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for (PointerPxe = MiAddressToPxe((PVOID)(HYPER_SPACE_END + 1));
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for (PointerPxe = MiAddressToPxe((PVOID)HYPER_SPACE);
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PointerPxe <= MiAddressToPxe(MI_HIGHEST_SYSTEM_ADDRESS);
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PointerPxe++)
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{
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@ -231,8 +233,13 @@ MiInitializePageTable()
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}
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}
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/* Setup the mapping PPEs and PDEs */
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MiMapPPEs((PVOID)MI_MAPPING_RANGE_START, (PVOID)MI_MAPPING_RANGE_END);
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/* Map PPEs for paged pool */
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MiMapPPEs(MmPagedPoolStart, MmPagedPoolEnd);
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/* Setup 1 PPE for hyper space */
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MiMapPPEs((PVOID)HYPER_SPACE, (PVOID)HYPER_SPACE_END);
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/* Setup the mapping PDEs */
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MiMapPDEs((PVOID)MI_MAPPING_RANGE_START, (PVOID)MI_MAPPING_RANGE_END);
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/* Setup the mapping PTEs */
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@ -246,6 +253,10 @@ MiInitializePageTable()
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MiMapPDEs((PVOID)MI_DEBUG_MAPPING, (PVOID)MI_DEBUG_MAPPING);
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MmDebugPte = MiAddressToPte((PVOID)MI_DEBUG_MAPPING);
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#endif
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/* Setup PDE and PTEs for VAD bitmap and working set list */
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MiMapPDEs((PVOID)MI_VAD_BITMAP, (PVOID)(MI_WORKING_SET_LIST + PAGE_SIZE - 1));
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MiMapPTEs((PVOID)MI_VAD_BITMAP, (PVOID)(MI_WORKING_SET_LIST + PAGE_SIZE - 1));
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}
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VOID
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@ -311,34 +322,31 @@ MiBuildNonPagedPool(VOID)
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MmMaximumNonPagedPoolInBytes = MI_MAX_NONPAGED_POOL_SIZE;
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}
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/* Put non paged pool to the end of the region */
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MmNonPagedPoolStart = (PCHAR)MmNonPagedPoolEnd - MmMaximumNonPagedPoolInBytes;
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/* Convert nonpaged pool size from bytes to pages */
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MmMaximumNonPagedPoolInPages = MmMaximumNonPagedPoolInBytes >> PAGE_SHIFT;
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/* Make sure it doesn't collide with the PFN database */
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if ((PCHAR)MmNonPagedPoolStart < (PCHAR)MmPfnDatabase + MxPfnSizeInBytes)
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{
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/* Put non paged pool after the PFN database */
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MmNonPagedPoolStart = (PCHAR)MmPfnDatabase + MxPfnSizeInBytes;
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MmMaximumNonPagedPoolInBytes = (ULONG64)MmNonPagedPoolEnd -
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(ULONG64)MmNonPagedPoolStart;
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}
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ASSERT(IS_PAGE_ALIGNED(MmNonPagedPoolStart));
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/* Non paged pool starts after the PFN database */
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MmNonPagedPoolStart = MmPfnDatabase + MxPfnAllocation * PAGE_SIZE;
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/* Calculate the nonpaged pool expansion start region */
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MmNonPagedPoolExpansionStart = (PCHAR)MmNonPagedPoolStart +
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MmSizeOfNonPagedPoolInBytes;
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ASSERT(IS_PAGE_ALIGNED(MmNonPagedPoolExpansionStart));
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/* And this is where the none paged pool ends */
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MmNonPagedPoolEnd = (PCHAR)MmNonPagedPoolStart + MmMaximumNonPagedPoolInBytes;
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ASSERT(MmNonPagedPoolEnd < (PVOID)MM_HAL_VA_START);
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/* Map PPEs and PDEs for non paged pool (including expansion) */
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MiMapPPEs(MmNonPagedPoolStart, MmNonPagedPoolEnd);
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MiMapPDEs(MmNonPagedPoolStart, MmNonPagedPoolEnd);
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/* Map the nonpaged pool PTEs (without expansion) */
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MiMapPTEs(MmNonPagedPoolStart, (PUCHAR)MmNonPagedPoolExpansionStart - 1);
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MiMapPTEs(MmNonPagedPoolStart, (PCHAR)MmNonPagedPoolExpansionStart - 1);
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/* Initialize the ARM3 nonpaged pool */
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MiInitializeNonPagedPool();
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MiInitializeNonPagedPoolThresholds();
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/* Initialize the nonpaged pool */
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InitializePool(NonPagedPool, 0);
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@ -353,32 +361,18 @@ MiBuildSystemPteSpace()
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/* Use the default numer of system PTEs */
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MmNumberOfSystemPtes = MI_NUMBER_SYSTEM_PTES;
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/* System PTE pool is below the PFN database */
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MiNonPagedSystemSize = (MmNumberOfSystemPtes + 1) * PAGE_SIZE;
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MmNonPagedSystemStart = (PCHAR)MmPfnDatabase - MiNonPagedSystemSize;
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MmNonPagedSystemStart = MM_ROUND_DOWN(MmNonPagedSystemStart, 512 * PAGE_SIZE);
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/* Don't let it go below the minimum */
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if (MmNonPagedSystemStart < (PVOID)MI_NON_PAGED_SYSTEM_START_MIN)
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{
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/* This is a hard-coded limit in the Windows NT address space */
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MmNonPagedSystemStart = (PVOID)MI_NON_PAGED_SYSTEM_START_MIN;
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/* Put system PTEs at the start of the system VA space */
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MiSystemPteSpaceStart = MmNonPagedSystemStart;
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MiSystemPteSpaceEnd = (PUCHAR)MiSystemPteSpaceStart + MiNonPagedSystemSize;
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/* Reduce the amount of system PTEs to reach this point */
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MmNumberOfSystemPtes = (ULONG)(((ULONG64)MmPfnDatabase -
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(ULONG64)MmNonPagedSystemStart) >>
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PAGE_SHIFT);
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MmNumberOfSystemPtes--;
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ASSERT(MmNumberOfSystemPtes > 1000);
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}
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/* Map the PPEs and PDEs for the system PTEs */
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MiMapPPEs(MiSystemPteSpaceStart, MiSystemPteSpaceEnd);
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MiMapPDEs(MiSystemPteSpaceStart, MiSystemPteSpaceEnd);
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/* Map the PDEs and PPEs for the system PTEs */
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MiMapPPEs(MI_SYSTEM_PTE_START, MI_SYSTEM_PTE_END);
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MiMapPDEs(MI_SYSTEM_PTE_START, MI_SYSTEM_PTE_END);
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/* Create the system PTE space */
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PointerPte = MiAddressToPte(MI_SYSTEM_PTE_START);
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/* Initialize the system PTE space */
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PointerPte = MiAddressToPte(MiSystemPteSpaceStart);
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MiInitializeSystemPtes(PointerPte, MmNumberOfSystemPtes, SystemPteSpace);
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/* Reserve system PTEs for zeroing PTEs and clear them */
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@ -389,13 +383,302 @@ MiBuildSystemPteSpace()
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MiFirstReservedZeroingPte->u.Hard.PageFrameNumber = MI_ZERO_PTES - 1;
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}
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static
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VOID
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MiSetupPfnForPageTable(
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PFN_NUMBER PageFrameIndex,
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PMMPTE PointerPte)
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{
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PMMPFN Pfn;
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PMMPDE PointerPde;
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/* Get the pfn entry for this page */
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Pfn = MiGetPfnEntry(PageFrameIndex);
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/* Check if it's valid memory */
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if ((PageFrameIndex <= MmHighestPhysicalPage) &&
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(MmIsAddressValid(Pfn)) &&
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(Pfn->u3.e1.PageLocation == ActiveAndValid))
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{
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/* Setup the PFN entry */
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Pfn->u1.WsIndex = 0;
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Pfn->u2.ShareCount++;
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Pfn->PteAddress = PointerPte;
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Pfn->OriginalPte = *PointerPte;
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Pfn->u3.e1.PageLocation = ActiveAndValid;
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Pfn->u3.e1.CacheAttribute = MiNonCached;
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Pfn->u3.e2.ReferenceCount = 1;
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Pfn->u4.PteFrame = PFN_FROM_PTE(MiAddressToPte(PointerPte));
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}
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/* Increase the shared count of the PFN entry for the PDE */
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PointerPde = MiAddressToPde(MiPteToAddress(PointerPte));
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Pfn = MiGetPfnEntry(PFN_FROM_PTE(PointerPde));
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Pfn->u2.ShareCount++;
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}
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VOID
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NTAPI
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MiBuildPfnDatabaseFromPageTables(VOID)
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{
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PVOID Address = NULL;
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PFN_NUMBER PageFrameIndex;
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PMMPDE PointerPde;
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PMMPTE PointerPte;
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ULONG k, l;
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PMMPFN Pfn;
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#if (_MI_PAGING_LEVELS >= 3)
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PMMPDE PointerPpe;
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ULONG j;
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#endif
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#if (_MI_PAGING_LEVELS == 4)
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PMMPDE PointerPxe;
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ULONG i;
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#endif
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/* Manual setup of the top level page directory */
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#if (_MI_PAGING_LEVELS == 4)
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PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PXE_BASE));
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#elif (_MI_PAGING_LEVELS == 3)
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PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PPE_BASE));
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#else
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PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PDE_BASE));
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#endif
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Pfn = MiGetPfnEntry(PageFrameIndex);
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ASSERT(Pfn->u3.e1.PageLocation == ActiveAndValid);
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Pfn->u1.WsIndex = 0;
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Pfn->u2.ShareCount = 1;
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Pfn->PteAddress = NULL;
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Pfn->u3.e1.CacheAttribute = MiNonCached;
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Pfn->u3.e2.ReferenceCount = 1;
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Pfn->u4.PteFrame = 0;
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#if (_MI_PAGING_LEVELS == 4)
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/* Loop all PXEs in the PML4 */
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PointerPxe = MiAddressToPxe(Address);
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for (i = 0; i < PXE_PER_PAGE; i++, PointerPxe++)
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{
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/* Skip invalid PXEs */
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if (!PointerPxe->u.Hard.Valid) continue;
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|
||||
/* Handle the PFN */
|
||||
PageFrameIndex = PFN_FROM_PXE(PointerPxe);
|
||||
MiSetupPfnForPageTable(PageFrameIndex, PointerPxe);
|
||||
|
||||
/* Get starting VA for this PXE */
|
||||
Address = MiPxeToAddress(PointerPxe);
|
||||
#endif
|
||||
#if (_MI_PAGING_LEVELS >= 3)
|
||||
/* Loop all PPEs in this PDP */
|
||||
PointerPpe = MiAddressToPpe(Address);
|
||||
for (j = 0; j < PPE_PER_PAGE; j++, PointerPpe++)
|
||||
{
|
||||
/* Skip invalid PPEs */
|
||||
if (!PointerPpe->u.Hard.Valid) continue;
|
||||
|
||||
/* Handle the PFN */
|
||||
PageFrameIndex = PFN_FROM_PPE(PointerPpe);
|
||||
MiSetupPfnForPageTable(PageFrameIndex, PointerPpe);
|
||||
|
||||
/* Get starting VA for this PPE */
|
||||
Address = MiPpeToAddress(PointerPpe);
|
||||
#endif
|
||||
/* Loop all PDEs in this PD */
|
||||
PointerPde = MiAddressToPde(Address);
|
||||
for (k = 0; k < PDE_PER_PAGE; k++, PointerPde++)
|
||||
{
|
||||
/* Skip invalid PDEs */
|
||||
if (!PointerPde->u.Hard.Valid) continue;
|
||||
|
||||
/* Handle the PFN */
|
||||
PageFrameIndex = PFN_FROM_PDE(PointerPde);
|
||||
MiSetupPfnForPageTable(PageFrameIndex, PointerPde);
|
||||
|
||||
/* Get starting VA for this PDE */
|
||||
Address = MiPdeToAddress(PointerPde);
|
||||
|
||||
/* Loop all PTEs in this PT */
|
||||
PointerPte = MiAddressToPte(Address);
|
||||
for (l = 0; l < PTE_PER_PAGE; l++, PointerPte++)
|
||||
{
|
||||
/* Skip invalid PTEs */
|
||||
if (!PointerPte->u.Hard.Valid) continue;
|
||||
|
||||
/* Handle the PFN */
|
||||
PageFrameIndex = PFN_FROM_PTE(PointerPte);
|
||||
MiSetupPfnForPageTable(PageFrameIndex, PointerPte);
|
||||
}
|
||||
}
|
||||
#if (_MI_PAGING_LEVELS >= 3)
|
||||
}
|
||||
#endif
|
||||
#if (_MI_PAGING_LEVELS == 4)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
INIT_FUNCTION
|
||||
MiAddDescriptorToDatabase(
|
||||
PFN_NUMBER BasePage,
|
||||
PFN_NUMBER PageCount,
|
||||
TYPE_OF_MEMORY MemoryType)
|
||||
{
|
||||
PMMPFN Pfn;
|
||||
|
||||
ASSERT(!MiIsMemoryTypeInvisible(MemoryType));
|
||||
|
||||
/* Check if the memory is free */
|
||||
if (MiIsMemoryTypeFree(MemoryType))
|
||||
{
|
||||
/* Get the last pfn of this descriptor. Note we loop backwards */
|
||||
Pfn = &MmPfnDatabase[BasePage + PageCount - 1];
|
||||
|
||||
/* Loop all pages */
|
||||
while (PageCount--)
|
||||
{
|
||||
/* Add it to the free list */
|
||||
Pfn->u3.e1.CacheAttribute = MiNonCached;
|
||||
MiInsertPageInFreeList(BasePage + PageCount);
|
||||
|
||||
/* Go to the previous page */
|
||||
Pfn--;
|
||||
}
|
||||
}
|
||||
else if (MemoryType == LoaderXIPRom)
|
||||
{
|
||||
Pfn = &MmPfnDatabase[BasePage];
|
||||
while (PageCount--)
|
||||
{
|
||||
/* Make it a pseudo-I/O ROM mapping */
|
||||
Pfn->PteAddress = 0;
|
||||
Pfn->u1.Flink = 0;
|
||||
Pfn->u2.ShareCount = 0;
|
||||
Pfn->u3.e1.PageLocation = 0;
|
||||
Pfn->u3.e1.CacheAttribute = MiNonCached;
|
||||
Pfn->u3.e1.Rom = 1;
|
||||
Pfn->u3.e1.PrototypePte = 1;
|
||||
Pfn->u3.e2.ReferenceCount = 0;
|
||||
Pfn->u4.InPageError = 0;
|
||||
Pfn->u4.PteFrame = 0;
|
||||
|
||||
/* Advance one */
|
||||
Pfn++;
|
||||
}
|
||||
}
|
||||
else if (MemoryType == LoaderBad)
|
||||
{
|
||||
// FIXME: later
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* For now skip it */
|
||||
DbgPrint("Skipping BasePage=0x%lx, PageCount=0x%lx, MemoryType=%lx\n",
|
||||
BasePage, PageCount, MemoryType);
|
||||
Pfn = &MmPfnDatabase[BasePage];
|
||||
while (PageCount--)
|
||||
{
|
||||
/* Make an active PFN */
|
||||
Pfn->u3.e1.PageLocation = ActiveAndValid;
|
||||
|
||||
/* Advance one */
|
||||
Pfn++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
INIT_FUNCTION
|
||||
MiBuildPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
{
|
||||
PLIST_ENTRY ListEntry;
|
||||
PMEMORY_ALLOCATION_DESCRIPTOR Descriptor;
|
||||
PFN_NUMBER BasePage, PageCount;
|
||||
|
||||
/* Map the PDEs and PPEs for the pfn database (ignore holes) */
|
||||
#if (_MI_PAGING_LEVELS >= 3)
|
||||
MiMapPPEs(MmPfnDatabase, (PUCHAR)MmPfnDatabase + MxPfnAllocation - 1);
|
||||
#endif
|
||||
MiMapPDEs(MmPfnDatabase, (PUCHAR)MmPfnDatabase + MxPfnAllocation - 1);
|
||||
|
||||
/* First initialize the color tables */
|
||||
MiInitializeColorTables();
|
||||
|
||||
/* Loop the memory descriptors */
|
||||
for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
|
||||
ListEntry != &LoaderBlock->MemoryDescriptorListHead;
|
||||
ListEntry = ListEntry->Flink)
|
||||
{
|
||||
/* Get the descriptor */
|
||||
Descriptor = CONTAINING_RECORD(ListEntry,
|
||||
MEMORY_ALLOCATION_DESCRIPTOR,
|
||||
ListEntry);
|
||||
|
||||
/* Skip invisible memory */
|
||||
if (MiIsMemoryTypeInvisible(Descriptor->MemoryType)) continue;
|
||||
|
||||
/* If this is the free descriptor, use the copy instead */
|
||||
if (Descriptor == MxFreeDescriptor) Descriptor = &MxOldFreeDescriptor;
|
||||
|
||||
/* Get the range for this descriptor */
|
||||
BasePage = Descriptor->BasePage;
|
||||
PageCount = Descriptor->PageCount;
|
||||
|
||||
/* Map the pages for the database */
|
||||
MiMapPTEs(&MmPfnDatabase[BasePage],
|
||||
(PUCHAR)(&MmPfnDatabase[BasePage + PageCount]) - 1);
|
||||
|
||||
/* If this was the free descriptor, skip the next step */
|
||||
if (Descriptor == &MxOldFreeDescriptor) continue;
|
||||
|
||||
/* Add this descriptor to the database */
|
||||
MiAddDescriptorToDatabase(BasePage, PageCount, Descriptor->MemoryType);
|
||||
}
|
||||
|
||||
/* At this point the whole pfn database is mapped. We are about to add the
|
||||
pages from the free descriptor to the database, so from now on we cannot
|
||||
use it anymore. */
|
||||
|
||||
/* Now add the free descriptor */
|
||||
BasePage = MxFreeDescriptor->BasePage;
|
||||
PageCount = MxFreeDescriptor->PageCount;
|
||||
MiAddDescriptorToDatabase(BasePage, PageCount, LoaderFree);
|
||||
|
||||
/* And finally the memory we used */
|
||||
BasePage = MxOldFreeDescriptor.BasePage;
|
||||
PageCount = MxFreeDescriptor->BasePage - BasePage;
|
||||
MiAddDescriptorToDatabase(BasePage, PageCount, LoaderMemoryData);
|
||||
|
||||
// Reset the descriptor back so we can create the correct memory blocks
|
||||
*MxFreeDescriptor = MxOldFreeDescriptor;
|
||||
}
|
||||
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
INIT_FUNCTION
|
||||
MiInitMachineDependent(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
{
|
||||
KIRQL OldIrql;
|
||||
|
||||
ASSERT(MxPfnAllocation != 0);
|
||||
|
||||
/* Set some hardcoded addresses */
|
||||
MmHyperSpaceEnd = (PVOID)HYPER_SPACE_END;
|
||||
MmNonPagedSystemStart = (PVOID)MM_SYSTEM_SPACE_START;
|
||||
MmPfnDatabase = (PVOID)MI_PFN_DATABASE;
|
||||
MmWorkingSetList = (PVOID)MI_WORKING_SET_LIST;
|
||||
|
||||
|
||||
// PrototypePte.u.Proto.Valid = 1
|
||||
// PrototypePte.u.ReadOnly
|
||||
// PrototypePte.u.Prototype
|
||||
// PrototypePte.u.Protection = MM_READWRITE;
|
||||
// PrototypePte.u.ProtoAddress
|
||||
PrototypePte.u.Soft.PageFileHigh = MI_PTE_LOOKUP_NEEDED;
|
||||
|
||||
|
||||
MiInitializePageTable();
|
||||
|
||||
|
|
@ -403,5 +686,33 @@ MiInitMachineDependent(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
|||
|
||||
MiBuildSystemPteSpace();
|
||||
|
||||
/* Need to be at DISPATCH_LEVEL for MiInsertPageInFreeList */
|
||||
KeRaiseIrql(DISPATCH_LEVEL, &OldIrql);
|
||||
|
||||
/* Map the PFN database pages */
|
||||
MiBuildPfnDatabase(LoaderBlock);
|
||||
|
||||
/* Now process the page tables */
|
||||
MiBuildPfnDatabaseFromPageTables();
|
||||
|
||||
MiPfnsInitialized = TRUE;
|
||||
|
||||
KeLowerIrql(OldIrql);
|
||||
|
||||
/* Initialize the balancer */
|
||||
MmInitializeBalancer((ULONG)MmAvailablePages, 0);
|
||||
|
||||
/* Make sure we have everything we need */
|
||||
ASSERT(MmPfnDatabase);
|
||||
ASSERT(MmNonPagedSystemStart);
|
||||
ASSERT(MmNonPagedPoolStart);
|
||||
ASSERT(MmSizeOfNonPagedPoolInBytes);
|
||||
ASSERT(MmMaximumNonPagedPoolInBytes);
|
||||
ASSERT(MmNonPagedPoolExpansionStart);
|
||||
ASSERT(MmHyperSpaceEnd);
|
||||
ASSERT(MmNumberOfSystemPtes);
|
||||
ASSERT(MiAddressToPde(MmNonPagedPoolStart)->u.Hard.Valid);
|
||||
ASSERT(MiAddressToPte(MmNonPagedPoolStart)->u.Hard.Valid);
|
||||
|
||||
return STATUS_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue