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fixed vgaHLine and VGADDIFillSolid for cases where left edge and right edge are in same 8-pixel group. ( no longer needs to default to slow case )

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svn path=/trunk/; revision=5535
This commit is contained in:
Royce Mitchell III 2003-08-11 19:58:43 +00:00
parent 1503893d83
commit 0eeded0a9a
5 changed files with 97 additions and 70 deletions
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118
reactos/drivers/dd/vga/display/objects/paint.c
View file

@ -48,78 +48,84 @@ BOOL VGADDIFillSolid(SURFOBJ *Surface, RECTL Dimensions, ULONG iColor)
// Make a note of original x // Make a note of original x
orgx = x; orgx = x;
// If width is less than 8, draw using vertical lines // Calculate the left mask pixels, middle bytes and right mask pixel
if ( w < 8 ) ileftpix = 7 - mod8(x-1);
{ rightpix = mod8(x+w);
for (i=x; i<x+w; i++) midpix = (w-leftpix-rightpix) / 8;
vgaVLine(i, y, h, iColor);
// Otherwise, use the optimized code ileftpix = leftpix;
irightpix = rightpix;
imidpix = midpix;
pre1 = xconv[(x-1)&~7] + y80[y];
orgpre1=pre1;
// check for overlap ( very horizontally skinny rect )
if ( (ileftpix+irightpix) > w )
{
int mask = startmasks[ileftpix] & endmasks[irightpix];
WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08); // set the mask
WRITE_PORT_UCHAR((PUCHAR)GRA_D,mask);
tmppre1 = pre1;
for ( j = y; j < y+h; j++ )
{
a = READ_REGISTER_UCHAR ( vidmem+tmppre1 );
WRITE_REGISTER_UCHAR ( vidmem+tmppre1, iColor );
tmppre1 += 80;
}
return TRUE;
} }
else
if ( ileftpix > 0 )
{ {
// Write left pixels
WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08); // set the mask
WRITE_PORT_UCHAR((PUCHAR)GRA_D,startmasks[ileftpix]);
// Calculate the left mask pixels, middle bytes and right mask pixel tmppre1 = pre1;
ileftpix = 7 - mod8(x-1); for ( j = y; j < y+h; j++ )
rightpix = mod8(x+w);
midpix = (w-leftpix-rightpix) / 8;
ileftpix = leftpix;
irightpix = rightpix;
imidpix = midpix;
pre1 = xconv[(x-1)&~7] + y80[y];
orgpre1=pre1;
if ( ileftpix > 0 )
{ {
// Write left pixels a = READ_REGISTER_UCHAR(vidmem + tmppre1);
WRITE_PORT_UCHAR((PUCHAR)0x3ce,0x08); // set the mask WRITE_REGISTER_UCHAR(vidmem + tmppre1, iColor);
WRITE_PORT_UCHAR((PUCHAR)0x3cf,startmasks[ileftpix]); tmppre1 += 80;
tmppre1 = pre1;
for ( j = y; j < y+h; j++ )
{
a = READ_REGISTER_UCHAR(vidmem + tmppre1);
WRITE_REGISTER_UCHAR(vidmem + tmppre1, iColor);
tmppre1 += 80;
}
// Prepare new x for the middle
x = orgx + 8;
} }
if ( imidpix > 0 ) // Prepare new x for the middle
{ x = orgx + 8;
midpre1=xconv[x] + y80[y]; }
// Set mask to all pixels in byte if ( imidpix > 0 )
WRITE_PORT_UCHAR((PUCHAR)0x3ce, 0x08); {
midpre1=xconv[x] + y80[y];
WRITE_PORT_UCHAR((PUCHAR)0x3cf, 0xff); // Set mask to all pixels in byte
WRITE_PORT_UCHAR((PUCHAR)GRA_I, 0x08);
for ( j = y; j < y+h; j++ ) WRITE_PORT_UCHAR((PUCHAR)GRA_D, 0xff);
{
memset(vidmem+midpre1, iColor, imidpix); // write middle pixels, no need to read in latch because of the width
midpre1 += 80;
}
}
x = orgx + w - irightpix;
pre1 = xconv[x] + y80[y];
// Write right pixels
WRITE_PORT_UCHAR((PUCHAR)0x3ce,0x08); // set the mask bits
WRITE_PORT_UCHAR((PUCHAR)0x3cf,endmasks[irightpix]);
for ( j = y; j < y+h; j++ ) for ( j = y; j < y+h; j++ )
{ {
a = READ_REGISTER_UCHAR(vidmem + pre1); memset(vidmem+midpre1, iColor, imidpix); // write middle pixels, no need to read in latch because of the width
WRITE_REGISTER_UCHAR(vidmem + pre1, iColor); midpre1 += 80;
pre1 += 80;
} }
} }
x = orgx + w - irightpix;
pre1 = xconv[x] + y80[y];
// Write right pixels
WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08); // set the mask bits
WRITE_PORT_UCHAR((PUCHAR)GRA_D,endmasks[irightpix]);
for ( j = y; j < y+h; j++ )
{
a = READ_REGISTER_UCHAR(vidmem + pre1);
WRITE_REGISTER_UCHAR(vidmem + pre1, iColor);
pre1 += 80;
}
return TRUE; return TRUE;
} }

28
reactos/drivers/dd/vga/display/vgavideo/vgavideo.c
View file

@ -274,15 +274,15 @@ BOOL vgaHLine(INT x, INT y, INT len, UCHAR c)
ULONG orgpre1, orgx, midpre1; ULONG orgpre1, orgx, midpre1;
ULONG ileftpix, imidpix, irightpix; ULONG ileftpix, imidpix, irightpix;
orgx=x; orgx = x;
if(len<8) /*if ( len < 8 )
{ {
for (i=x; i<x+len; i++) for (i = x; i < x+len; i++ )
vgaPutPixel(i, y, c); vgaPutPixel ( i, y, c );
return TRUE; return TRUE;
} }*/
// Calculate the left mask pixels, middle bytes and right mask pixel // Calculate the left mask pixels, middle bytes and right mask pixel
ileftpix = 7 - mod8(x-1); ileftpix = 7 - mod8(x-1);
@ -292,6 +292,20 @@ BOOL vgaHLine(INT x, INT y, INT len, UCHAR c)
pre1 = xconv[(x-1)&~7] + y80[y]; pre1 = xconv[(x-1)&~7] + y80[y];
orgpre1=pre1; orgpre1=pre1;
// check for overlap ( very short line )
if ( (ileftpix+irightpix) > len )
{
int mask = startmasks[ileftpix] & endmasks[irightpix];
// Write left pixels
WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08); // set the mask
WRITE_PORT_UCHAR((PUCHAR)GRA_D,mask);
a = READ_REGISTER_UCHAR(vidmem + pre1);
WRITE_REGISTER_UCHAR(vidmem + pre1, c);
return TRUE;
}
// Left // Left
if ( ileftpix > 0 ) if ( ileftpix > 0 )
{ {
@ -528,8 +542,8 @@ void DIB_BltToVGA(int x, int y, int w, int h, void *b, int Source_lDelta)
pb = opb; pb = opb;
offset = xconv[i] + y80[y]; offset = xconv[i] + y80[y];
WRITE_PORT_UCHAR((PUCHAR)0x3ce, 0x08); // set the mask WRITE_PORT_UCHAR((PUCHAR)GRA_I, 0x08); // set the mask
WRITE_PORT_UCHAR((PUCHAR)0x3cf, maskbit[i]); WRITE_PORT_UCHAR((PUCHAR)GRA_D, maskbit[i]);
if (0 == ((i - x) % 2)) if (0 == ((i - x) % 2))
{ {

10
reactos/drivers/dd/vga/miniport/initvga.c
View file

@ -82,13 +82,13 @@ void InitVGAMode()
setMode(Mode12); setMode(Mode12);
// Get the VGA into the mode we want to work with // Get the VGA into the mode we want to work with
WRITE_PORT_UCHAR((PUCHAR)0x3ce,0x08); // Set WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08); // Set
WRITE_PORT_UCHAR((PUCHAR)0x3cf,0); // the MASK WRITE_PORT_UCHAR((PUCHAR)GRA_D,0); // the MASK
WRITE_PORT_USHORT((PUSHORT)0x3ce,0x0205); // write mode = 2 (bits 0,1) read mode = 0 (bit 3) WRITE_PORT_USHORT((PUSHORT)GRA_I,0x0205); // write mode = 2 (bits 0,1) read mode = 0 (bit 3)
i = READ_REGISTER_UCHAR(vidmem); // Update bit buffer i = READ_REGISTER_UCHAR(vidmem); // Update bit buffer
WRITE_REGISTER_UCHAR(vidmem, 0); // Write the pixel WRITE_REGISTER_UCHAR(vidmem, 0); // Write the pixel
WRITE_PORT_UCHAR((PUCHAR)0x3ce,0x08); WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08);
WRITE_PORT_UCHAR((PUCHAR)0x3cf,0xff); WRITE_PORT_UCHAR((PUCHAR)GRA_D,0xff);
// Zero out video memory (clear a possibly trashed screen) // Zero out video memory (clear a possibly trashed screen)
RtlZeroMemory(vidmem, 64000); RtlZeroMemory(vidmem, 64000);

4
reactos/drivers/dd/vga/miniport/vgavideo.c
View file

@ -81,8 +81,8 @@ VOID vgaPreCalc()
void vgaSetWriteMode(char mode) void vgaSetWriteMode(char mode)
{ {
VideoPortWritePortUchar((PUCHAR)0x03ce, 0x03); VideoPortWritePortUchar((PUCHAR)GRA_I, 0x03);
VideoPortWritePortUchar((PUCHAR)0x03cf, mode); VideoPortWritePortUchar((PUCHAR)GRA_D, mode);
} }
void vgaSetColor(int cindex, int red, int green, int blue) void vgaSetColor(int cindex, int red, int green, int blue)

7
reactos/drivers/dd/vga/miniport/vgavideo.h
View file

@ -21,6 +21,13 @@ char* vidmem;
#define ATTRIB 0x3c0 #define ATTRIB 0x3c0
#define STATUS 0x3da #define STATUS 0x3da
#define SEQ_I 0x3C4 /* Sequencer Index */
#define SEQ_D 0x3C5 /* Sequencer Data Register */
#define GRA_I 0x3CE /* Graphics Controller Index */
#define GRA_D 0x3CF /* Graphics Controller Data Register */
typedef struct _VideoMode { typedef struct _VideoMode {
unsigned short VidSeg; unsigned short VidSeg;
unsigned char Misc; unsigned char Misc;