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[FAST486]

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- Only flush the TLB when needed.
- Flush the TLB after a reset.


svn path=/trunk/; revision=67698
This commit is contained in:
Aleksandar Andrejevic 2015-05-12 19:10:52 +00:00
parent 5670e997ca
commit 0dc2da8084
4 changed files with 17 additions and 3 deletions
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2
reactos/lib/fast486/common.c
View file

@ -834,7 +834,7 @@ Fast486TaskSwitch(PFAST486_STATE State, FAST486_TASK_SWITCH_TYPE Type, USHORT Se
}
/* Flush the TLB */
if (State->Tlb) RtlFillMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG), 0xFF);
Fast486FlushTlb(State);
/* Update the CPL */
if (NewTssLimit >= (sizeof(FAST486_TSS) - 1)) State->Cpl = GET_SEGMENT_RPL(NewTss.Cs);

11
reactos/lib/fast486/common.inl
View file

@ -138,12 +138,23 @@ Fast486GetPageTableEntry(PFAST486_STATE State,
{
/* Set the TLB entry */
State->Tlb[VirtualAddress >> 12] = TableEntry.Value;
State->TlbEmpty = FALSE;
}
/* Return the table entry */
return TableEntry.Value;
}
FORCEINLINE
VOID
FASTCALL
Fast486FlushTlb(PFAST486_STATE State)
{
if (!State->Tlb || State->TlbEmpty) return;
RtlFillMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG), 0xFF);
State->TlbEmpty = TRUE;
}
FORCEINLINE
BOOLEAN
FASTCALL

4
reactos/lib/fast486/extraops.c
View file

@ -640,10 +640,10 @@ FAST486_OPCODE_HANDLER(Fast486ExtOpcodeLoadControlReg)
State->PrefetchValid = FALSE;
#endif
if (State->Tlb && (ModRegRm.Register == (INT)FAST486_REG_CR3))
if (ModRegRm.Register == (INT)FAST486_REG_CR3)
{
/* Flush the TLB */
RtlFillMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG), 0xFF);
Fast486FlushTlb(State);
}
/* Load a value to the control register */

3
reactos/lib/fast486/fast486.c
View file

@ -284,6 +284,9 @@ Fast486Reset(PFAST486_STATE State)
State->IntAckCallback = IntAckCallback;
State->FpuCallback = FpuCallback;
State->Tlb = Tlb;
/* Flush the TLB */
Fast486FlushTlb(State);
}
VOID