mirror of
https://github.com/reactos/reactos.git
synced 2024-06-30 18:01:07 +00:00
- Fix a bug in memory area creation: Static memory areas had the static flag embedded in their type, so code that was switch()ing on the type would fail to recognize the actual type, because MEMORY_AREA_STATIC was ORed in.
- Add a new memory area type: MEMORY_AREA_OWNED_BY_ARM3. This will allow us to instruct the ReactOS Memory MAnager to "Back. The Fuck. Off." during page faults and such, so we can handle page faults inside ARM3-owned PTEs ourselves. - Right now, all ARM3 PTEs and data is nonpaged, so no page faults should happen, but this may change in the future. - Also will allow us to manage our own PDEs so we can do on-demand inpage instead of syncing with the ReactOS Mm hack cache. - Create all memory areas in one shot in MmCreateSystemMemoryAreas (get rid of MiInitPageDirectoryMap and MiInitPagedPool memory area creation). - Mark all of ours as owned by ARM3. - Make them all static. - The only non-ARM3 one right now is paged pool, we own all the other static areas. - Move this code into mm, instead of mm/ARM3, since memory areas are not an ARM3 concept. - Also create memory areas for session space, session view, and other ARM3 memory ranges, so nobody touches those ranges. - Dump the kernel address space after all this is done, in a MmDbg function in mm. - This cleans up ARM3 of some ROS-specific code, and also collapses Phase 1 and 2 into a single phase. svn path=/trunk/; revision=43486
This commit is contained in:
parent
8774094ea9
commit
071a297838
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@ -46,7 +46,7 @@ typedef ULONG PFN_TYPE, *PPFN_TYPE;
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#define MMDBG_COPY_MAX_SIZE 0x8
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#define MI_STATIC_MEMORY_AREAS (8)
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#define MI_STATIC_MEMORY_AREAS (12)
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#define MEMORY_AREA_INVALID (0)
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#define MEMORY_AREA_SECTION_VIEW (1)
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@ -62,6 +62,7 @@ typedef ULONG PFN_TYPE, *PPFN_TYPE;
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#define MEMORY_AREA_PAGED_POOL (12)
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#define MEMORY_AREA_NO_ACCESS (13)
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#define MEMORY_AREA_PEB_OR_TEB (14)
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#define MEMORY_AREA_OWNED_BY_ARM3 (15)
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#define MEMORY_AREA_STATIC (0x80000000)
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#define MM_PHYSICAL_PAGE_MPW_PENDING (0x8)
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@ -600,20 +600,16 @@ MmArmInitSystem(IN ULONG Phase,
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PLIST_ENTRY NextEntry;
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PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
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ULONG FreePages = 0;
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PMEMORY_AREA MArea;
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PHYSICAL_ADDRESS BoundaryAddressMultiple;
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PFN_NUMBER PageFrameIndex;
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PMMPTE StartPde, EndPde, PointerPte, LastPte;
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MMPTE TempPde = HyperTemplatePte, TempPte = HyperTemplatePte;
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PVOID NonPagedPoolExpansionVa, BaseAddress;
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NTSTATUS Status;
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PVOID NonPagedPoolExpansionVa;
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ULONG OldCount;
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BOOLEAN IncludeType[LoaderMaximum];
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ULONG i;
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PVOID Bitmap;
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PPHYSICAL_MEMORY_RUN Run;
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PFN_NUMBER FreePage, FreePageCount, PagesLeft, BasePage, PageCount;
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BoundaryAddressMultiple.QuadPart = 0;
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if (Phase == 0)
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{
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@ -1084,37 +1080,6 @@ MmArmInitSystem(IN ULONG Phase,
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*PointerPte++ = TempPte;
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}
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//
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// ReactOS requires a memory area to keep the initial NP area off-bounds
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//
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BaseAddress = MmNonPagedPoolStart;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_SYSTEM | MEMORY_AREA_STATIC,
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&BaseAddress,
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MmSizeOfNonPagedPoolInBytes,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// And we need one more for the system NP
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//
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BaseAddress = MmNonPagedSystemStart;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_SYSTEM | MEMORY_AREA_STATIC,
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&BaseAddress,
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(ULONG_PTR)MmNonPagedPoolEnd -
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(ULONG_PTR)MmNonPagedSystemStart,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// Sanity check: make sure we have properly defined the system PTE space
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//
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@ -1324,9 +1289,7 @@ MmArmInitSystem(IN ULONG Phase,
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MiSyncARM3WithROS(MmNonPagedSystemStart, (PVOID)((ULONG_PTR)MmNonPagedPoolEnd - 1));
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MiSyncARM3WithROS(MmPfnDatabase, (PVOID)((ULONG_PTR)MmNonPagedPoolStart + MmSizeOfNonPagedPoolInBytes - 1));
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MiSyncARM3WithROS((PVOID)HYPER_SPACE, (PVOID)(HYPER_SPACE + PAGE_SIZE - 1));
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}
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else // NOW WE HAVE NONPAGED POOL
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{
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//
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// Instantiate memory that we don't consider RAM/usable
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// We use the same exclusions that Windows does, in order to try to be
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@ -1400,53 +1363,6 @@ MmArmInitSystem(IN ULONG Phase,
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// Size up paged pool and build the shadow system page directory
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//
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MiBuildPagedPool();
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//
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// Print the memory layout
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//
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmSystemRangeStart,
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(ULONG_PTR)MmSystemRangeStart + MmBootImageSize,
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"Boot Loaded Image");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmPagedPoolBase,
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(ULONG_PTR)MmPagedPoolBase + MmPagedPoolSize,
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"Paged Pool");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmPfnDatabase,
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(ULONG_PTR)MmPfnDatabase + (MxPfnAllocation << PAGE_SHIFT),
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"PFN Database");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmNonPagedPoolStart,
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(ULONG_PTR)MmNonPagedPoolStart + MmSizeOfNonPagedPoolInBytes,
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"ARM³ Non Paged Pool");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MiSystemViewStart,
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(ULONG_PTR)MiSystemViewStart + MmSystemViewSize,
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"System View Space");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmSessionBase,
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MiSessionSpaceEnd,
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"Session Space");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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PTE_BASE, PDE_BASE,
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"Page Tables");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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PDE_BASE, HYPER_SPACE,
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"Page Directories");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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HYPER_SPACE, HYPER_SPACE + (4 * 1024 * 1024),
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"Hyperspace");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmPagedPoolStart,
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(ULONG_PTR)MmPagedPoolStart + MmSizeOfPagedPoolInBytes,
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"ARM³ Paged Pool");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmNonPagedSystemStart, MmNonPagedPoolExpansionStart,
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"System PTE Space");
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DPRINT1(" 0x%p - 0x%p\t%s\n",
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MmNonPagedPoolExpansionStart, MmNonPagedPoolEnd,
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"Non Paged Pool Expansion PTE Space");
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}
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//
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@ -147,6 +147,15 @@ extern ULONG MxPfnAllocation;
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extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
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extern RTL_BITMAP MiPfnBitMap;
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extern KGUARDED_MUTEX MmPagedPoolMutex;
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extern PVOID MmPagedPoolStart;
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extern PVOID MmPagedPoolEnd;
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extern PVOID MmNonPagedSystemStart;
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extern PVOID MiSystemViewStart;
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extern ULONG MmSystemViewSize;
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extern PVOID MmSessionBase;
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extern PVOID MiSessionSpaceEnd;
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extern ULONG MmSizeOfPagedPoolInBytes;
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extern PMMPTE MmSystemPagePtes;
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VOID
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NTAPI
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@ -1034,48 +1034,4 @@ MmInitGlobalKernelPageDirectory(VOID)
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}
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}
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VOID
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INIT_FUNCTION
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NTAPI
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MiInitPageDirectoryMap(VOID)
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{
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MEMORY_AREA* kernel_map_desc = NULL;
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MEMORY_AREA* hyperspace_desc = NULL;
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PHYSICAL_ADDRESS BoundaryAddressMultiple;
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PVOID BaseAddress;
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NTSTATUS Status;
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DPRINT("MiInitPageDirectoryMap()\n");
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BoundaryAddressMultiple.QuadPart = 0;
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BaseAddress = (PVOID)PAGETABLE_MAP;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_SYSTEM | MEMORY_AREA_STATIC,
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&BaseAddress,
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0x400000,
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PAGE_READWRITE,
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&kernel_map_desc,
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TRUE,
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0,
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BoundaryAddressMultiple);
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if (!NT_SUCCESS(Status))
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{
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KeBugCheck(MEMORY_MANAGEMENT);
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}
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BaseAddress = (PVOID)HYPERSPACE;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_SYSTEM | MEMORY_AREA_STATIC,
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&BaseAddress,
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0x400000,
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PAGE_READWRITE,
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&hyperspace_desc,
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TRUE,
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0,
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BoundaryAddressMultiple);
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if (!NT_SUCCESS(Status))
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{
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KeBugCheck(MEMORY_MANAGEMENT);
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}
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}
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/* EOF */
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@ -996,6 +996,7 @@ MmCreateMemoryArea(PMMSUPPORT AddressSpace,
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//
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ASSERT(MiStaticMemoryAreaCount < MI_STATIC_MEMORY_AREAS);
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MemoryArea = &MiStaticMemoryAreas[MiStaticMemoryAreaCount++];
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Type &= ~MEMORY_AREA_STATIC;
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}
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else
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{
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@ -12,6 +12,9 @@
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#define NDEBUG
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#include <debug.h>
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#define MODULE_INVOLVED_IN_ARM3
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#include "ARM3/miarm.h"
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/* GLOBALS *******************************************************************/
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PCHAR
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@ -69,19 +72,151 @@ MiInitSystemMemoryAreas()
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PVOID BaseAddress;
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PHYSICAL_ADDRESS BoundaryAddressMultiple;
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PMEMORY_AREA MArea;
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NTSTATUS Status;
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BoundaryAddressMultiple.QuadPart = 0;
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//
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// First initialize the page table and hyperspace memory areas
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// Create the memory area to define the PTE base
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//
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MiInitPageDirectoryMap();
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BaseAddress = (PVOID)PTE_BASE;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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4 * 1024 * 1024,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// Create the memory area to define Hyperspace
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//
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BaseAddress = (PVOID)HYPER_SPACE;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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4 * 1024 * 1024,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// Protect the PFN database
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//
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BaseAddress = MmPfnDatabase;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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(MxPfnAllocation << PAGE_SHIFT),
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// ReactOS requires a memory area to keep the initial NP area off-bounds
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//
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BaseAddress = MmNonPagedPoolStart;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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MmSizeOfNonPagedPoolInBytes,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// And we need one more for the system NP
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//
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BaseAddress = MmNonPagedSystemStart;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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(ULONG_PTR)MmNonPagedPoolEnd -
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(ULONG_PTR)MmNonPagedSystemStart,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// We also need one for system view space
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//
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BaseAddress = MiSystemViewStart;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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MmSystemViewSize,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// And another for session space
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//
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BaseAddress = MmSessionBase;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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(ULONG_PTR)MiSessionSpaceEnd -
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(ULONG_PTR)MmSessionBase,
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PAGE_READWRITE,
|
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// One more for ARM paged pool
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//
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BaseAddress = MmPagedPoolStart;
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Status = MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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MmSizeOfPagedPoolInBytes,
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PAGE_READWRITE,
|
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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ASSERT(Status == STATUS_SUCCESS);
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//
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// And now, ReactOS paged pool
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//
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BaseAddress = MmPagedPoolBase;
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MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_PAGED_POOL | MEMORY_AREA_STATIC,
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&BaseAddress,
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MmPagedPoolSize,
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PAGE_READWRITE,
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&MArea,
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TRUE,
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0,
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BoundaryAddressMultiple);
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//
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// Next, the KPCR
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//
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BaseAddress = (PVOID)PCR;
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MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_SYSTEM | MEMORY_AREA_STATIC,
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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PAGE_SIZE * KeNumberProcessors,
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PAGE_READWRITE,
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|
@ -89,13 +224,13 @@ MiInitSystemMemoryAreas()
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TRUE,
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0,
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BoundaryAddressMultiple);
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|
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//
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// Now the KUSER_SHARED_DATA
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//
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BaseAddress = (PVOID)KI_USER_SHARED_DATA;
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MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_SYSTEM | MEMORY_AREA_STATIC,
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MEMORY_AREA_OWNED_BY_ARM3 | MEMORY_AREA_STATIC,
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&BaseAddress,
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PAGE_SIZE,
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PAGE_READWRITE,
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|
@ -105,6 +240,58 @@ MiInitSystemMemoryAreas()
|
|||
BoundaryAddressMultiple);
|
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}
|
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|
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VOID
|
||||
NTAPI
|
||||
MiDbgDumpAddressSpace(VOID)
|
||||
{
|
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//
|
||||
// Print the memory layout
|
||||
//
|
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DPRINT1(" 0x%p - 0x%p\t%s\n",
|
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MmSystemRangeStart,
|
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(ULONG_PTR)MmSystemRangeStart + MmBootImageSize,
|
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"Boot Loaded Image");
|
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DPRINT1(" 0x%p - 0x%p\t%s\n",
|
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MmPagedPoolBase,
|
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(ULONG_PTR)MmPagedPoolBase + MmPagedPoolSize,
|
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"Paged Pool");
|
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DPRINT1(" 0x%p - 0x%p\t%s\n",
|
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MmPfnDatabase,
|
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(ULONG_PTR)MmPfnDatabase + (MxPfnAllocation << PAGE_SHIFT),
|
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"PFN Database");
|
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DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
MmNonPagedPoolStart,
|
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(ULONG_PTR)MmNonPagedPoolStart + MmSizeOfNonPagedPoolInBytes,
|
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"ARM³ Non Paged Pool");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
MiSystemViewStart,
|
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(ULONG_PTR)MiSystemViewStart + MmSystemViewSize,
|
||||
"System View Space");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
MmSessionBase,
|
||||
MiSessionSpaceEnd,
|
||||
"Session Space");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
PTE_BASE, PDE_BASE,
|
||||
"Page Tables");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
PDE_BASE, HYPER_SPACE,
|
||||
"Page Directories");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
HYPER_SPACE, HYPER_SPACE + (4 * 1024 * 1024),
|
||||
"Hyperspace");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
MmPagedPoolStart,
|
||||
(ULONG_PTR)MmPagedPoolStart + MmSizeOfPagedPoolInBytes,
|
||||
"ARM³ Paged Pool");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
MmNonPagedSystemStart, MmNonPagedPoolExpansionStart,
|
||||
"System PTE Space");
|
||||
DPRINT1(" 0x%p - 0x%p\t%s\n",
|
||||
MmNonPagedPoolExpansionStart, MmNonPagedPoolEnd,
|
||||
"Non Paged Pool Expansion PTE Space");
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MiDbgDumpMemoryDescriptors(VOID)
|
||||
|
@ -149,9 +336,6 @@ MmInit1(VOID)
|
|||
//
|
||||
MmArmInitSystem(0, KeLoaderBlock);
|
||||
|
||||
/* Intialize system memory areas */
|
||||
MiInitSystemMemoryAreas();
|
||||
|
||||
/* Initialize the page list */
|
||||
MmInitializePageList();
|
||||
|
||||
|
@ -164,12 +348,13 @@ MmInit1(VOID)
|
|||
MmPagedPoolBase = (PVOID)PAGE_ROUND_UP((ULONG_PTR)MmSystemRangeStart +
|
||||
MmBootImageSize);
|
||||
MmPagedPoolSize = MM_PAGED_POOL_SIZE;
|
||||
|
||||
//
|
||||
// Initialize ARM³ in phase 2
|
||||
//
|
||||
MmArmInitSystem(2, KeLoaderBlock);
|
||||
|
||||
/* Intialize system memory areas */
|
||||
MiInitSystemMemoryAreas();
|
||||
|
||||
/* Dump the address space */
|
||||
MiDbgDumpAddressSpace();
|
||||
|
||||
/* Initialize paged pool */
|
||||
MmInitializePagedPool();
|
||||
|
||||
|
|
|
@ -51,23 +51,7 @@ VOID
|
|||
INIT_FUNCTION
|
||||
NTAPI
|
||||
MmInitializePagedPool(VOID)
|
||||
{
|
||||
PVOID BaseAddress;
|
||||
PHYSICAL_ADDRESS BoundaryAddressMultiple;
|
||||
PMEMORY_AREA MArea;
|
||||
BoundaryAddressMultiple.QuadPart = 0;
|
||||
|
||||
BaseAddress = MmPagedPoolBase;
|
||||
MmCreateMemoryArea(MmGetKernelAddressSpace(),
|
||||
MEMORY_AREA_PAGED_POOL,
|
||||
&BaseAddress,
|
||||
MmPagedPoolSize,
|
||||
PAGE_READWRITE,
|
||||
&MArea,
|
||||
TRUE,
|
||||
0,
|
||||
BoundaryAddressMultiple);
|
||||
|
||||
{
|
||||
/*
|
||||
* We are still at a high IRQL level at this point so explicitly commit
|
||||
* the first page of the paged pool before writing the first block header.
|
||||
|
|
Loading…
Reference in a new issue