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[NTOSKRNL/FREELDR/NDK]
- "equalize" internal arch specific Mm headers - Move some definitions into more appropriate locations svn path=/trunk/; revision=67568
This commit is contained in:
Timo Kreuzer
parent
e2ae1410f2
commit
066c89edc7
10 changed files with 401 additions and 413 deletions
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@ -38,3 +38,30 @@ FORCEINLINE VOID Reboot(VOID)
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{
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DbgBreakPoint();
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}
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typedef struct _PAGE_TABLE_ARM
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{
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HARDWARE_PTE_ARMV6 Pte[1024];
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} PAGE_TABLE_ARM, *PPAGE_TABLE_ARM;
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C_ASSERT(sizeof(PAGE_TABLE_ARM) == PAGE_SIZE);
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typedef struct _PAGE_DIRECTORY_ARM
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{
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union
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{
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HARDWARE_PDE_ARMV6 Pde[4096];
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HARDWARE_LARGE_PTE_ARMV6 Pte[4096];
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};
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} PAGE_DIRECTORY_ARM, *PPAGE_DIRECTORY_ARM;
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C_ASSERT(sizeof(PAGE_DIRECTORY_ARM) == (4 * PAGE_SIZE));
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// FIXME: sync with NDK
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typedef enum _ARM_DOMAIN
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{
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FaultDomain,
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ClientDomain,
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InvalidDomain,
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ManagerDomain
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} ARM_DOMAIN;
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#define PDE_SHIFT 20
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@ -83,7 +83,7 @@ typedef struct _HARDWARE_LARGE_PTE_ARMV6
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ULONG NoExecute:1;
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ULONG Domain:4;
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ULONG Ecc:1;
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ULONG Sbo:1;
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ULONG Sbo:1; // ULONG Accessed:1;?
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ULONG Owner:1;
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ULONG CacheAttributes:3;
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ULONG ReadOnly:1;
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@ -100,7 +100,7 @@ typedef struct _HARDWARE_PTE_ARMV6
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ULONG Valid:1;
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ULONG Buffered:1;
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ULONG Cached:1;
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ULONG Sbo:1;
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ULONG Sbo:1; // ULONG Accessed:1;?
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ULONG Owner:1;
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ULONG CacheAttributes:3;
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ULONG ReadOnly:1;
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@ -6,7 +6,6 @@
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#define _MI_PAGING_LEVELS 4
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/* Memory layout base addresses */
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#define MI_LOWEST_VAD_ADDRESS (PVOID)0x0000000000010000ULL
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#define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL
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#define MI_REAL_SYSTEM_RANGE_START 0xFFFF800000000000ULL
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@ -20,17 +19,19 @@
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#define MI_SESSION_SPACE_END 0xFFFFF97FFFFFFFFFULL
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#define MM_SYSTEM_SPACE_START 0xFFFFF98000000000ULL
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#define MI_PFN_DATABASE 0xFFFFFA8000000000ULL
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
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#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFFFFFFBFFFFFULL
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#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
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#define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
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/* WOW64 address definitions */
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#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
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#define MM_SYSTEM_RANGE_START_WOW64 0x80000000
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
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#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME
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#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START
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#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
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/* Misc address definitions */
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//#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME
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//#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START
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//#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
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#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE)
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#define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define MI_MAPPING_RANGE_START HYPER_SPACE
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@ -40,64 +41,42 @@
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#define MI_WORKING_SET_LIST (MI_VAD_BITMAP + PAGE_SIZE)
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/* Memory sizes */
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
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#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
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#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
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#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_SYSTEM_VIEW_SIZE (16 * _1MB)
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#define MI_SESSION_VIEW_SIZE (20 * _1MB)
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#define MI_SESSION_POOL_SIZE (16 * _1MB)
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#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
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#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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/* Misc constants */
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#define MI_NUMBER_SYSTEM_PTES 22000
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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/* FIXME - different architectures have different cache line sizes... */
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#define MI_MAX_ZERO_BITS 53
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/* Helper macros */
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#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
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#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
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#define MiIsPteOnPdeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPpeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPxeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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#define MI_NUMBER_SYSTEM_PTES 22000
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_MAX_ZERO_BITS 53
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#define SESSION_POOL_LOOKASIDES 21
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/* MMPTE related defines */
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#define MM_EMPTY_PTE_LIST ((ULONG64)0xFFFFFFFF)
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#define MM_EMPTY_LIST ((ULONG_PTR)-1)
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#define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
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#define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
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#define ADDR_TO_PTE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
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#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
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#define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
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#define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
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#define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
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#define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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@ -105,7 +84,7 @@
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#define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
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#define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
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// FIXME, only copied from x86
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/* Macros for portable PTE modification */
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
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#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
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#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
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@ -128,44 +107,10 @@
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#endif
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/* On x64, these are the same */
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#define MMPDE MMPTE
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#define PMMPDE PMMPTE
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#define MMPPE MMPTE
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#define PMMPPE PMMPTE
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#define MMPXE MMPTE
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#define PMMPXE PMMPTE
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#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
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#define ValidKernelPpe ValidKernelPde
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PMMPTE
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FORCEINLINE
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MiAddressToPxe(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
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Offset &= PXI_MASK << 3;
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return (PMMPTE)(PXE_BASE + Offset);
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}
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PMMPTE
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FORCEINLINE
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MiAddressToPpe(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
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Offset &= 0x3FFFF << 3;
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return (PMMPTE)(PPE_BASE + Offset);
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}
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PMMPTE
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FORCEINLINE
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_MiAddressToPde(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
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Offset &= 0x7FFFFFF << 3;
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return (PMMPTE)(PDE_BASE + Offset);
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}
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#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
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/* Convert an address to a corresponding PTE */
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PMMPTE
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FORCEINLINE
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_MiAddressToPte(PVOID Address)
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@ -176,6 +121,38 @@ _MiAddressToPte(PVOID Address)
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}
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#define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
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/* Convert an address to a corresponding PDE */
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PMMPTE
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FORCEINLINE
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_MiAddressToPde(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
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Offset &= 0x7FFFFFF << 3;
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return (PMMPTE)(PDE_BASE + Offset);
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}
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#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
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/* Convert an address to a corresponding PPE */
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PMMPTE
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FORCEINLINE
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MiAddressToPpe(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
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Offset &= 0x3FFFF << 3;
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return (PMMPTE)(PPE_BASE + Offset);
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}
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/* Convert an address to a corresponding PXE */
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PMMPTE
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FORCEINLINE
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MiAddressToPxe(PVOID Address)
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{
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ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
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Offset &= PXI_MASK << 3;
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return (PMMPTE)(PXE_BASE + Offset);
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}
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/* Convert an address to a corresponding PTE offset/index */
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ULONG
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FORCEINLINE
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MiAddressToPti(PVOID Address)
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@ -184,6 +161,17 @@ MiAddressToPti(PVOID Address)
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}
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#define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
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/* Convert an address to a corresponding PDE offset/index */
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ULONG
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FORCEINLINE
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MiAddressToPdi(PVOID Address)
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{
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return ((((ULONG64)Address) >> PDI_SHIFT) & 0x1FF);
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}
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#define MiAddressToPdeOffset(x) MiAddressToPdi(x)
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#define MiGetPdeOffset(x) MiAddressToPdi(x)
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/* Convert an address to a corresponding PXE offset/index */
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ULONG
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FORCEINLINE
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MiAddressToPxi(PVOID Address)
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@ -191,7 +179,6 @@ MiAddressToPxi(PVOID Address)
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return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
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}
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/* Convert a PTE into a corresponding address */
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PVOID
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FORCEINLINE
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@ -201,6 +188,7 @@ MiPteToAddress(PMMPTE PointerPte)
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return (PVOID)(((LONG64)PointerPte << 25) >> 16);
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}
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/* Convert a PDE into a corresponding address */
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PVOID
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FORCEINLINE
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MiPdeToAddress(PMMPTE PointerPde)
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@ -209,6 +197,7 @@ MiPdeToAddress(PMMPTE PointerPde)
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return (PVOID)(((LONG64)PointerPde << 34) >> 16);
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}
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/* Convert a PPE into a corresponding address */
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PVOID
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FORCEINLINE
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MiPpeToAddress(PMMPTE PointerPpe)
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@ -217,6 +206,7 @@ MiPpeToAddress(PMMPTE PointerPpe)
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return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
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}
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/* Convert a PXE into a corresponding address */
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PVOID
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FORCEINLINE
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MiPxeToAddress(PMMPTE PointerPxe)
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@ -225,21 +215,24 @@ MiPxeToAddress(PMMPTE PointerPxe)
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return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
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}
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BOOLEAN
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FORCEINLINE
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MiIsPdeForAddressValid(PVOID Address)
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{
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return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
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(MiAddressToPpe(Address)->u.Hard.Valid) &&
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(MiAddressToPde(Address)->u.Hard.Valid));
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}
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/* Translate between P*Es */
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#define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
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#define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
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#define MiPdeToPpe(_Pde) ((PMMPPE)MiAddressToPte(_Pde))
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#define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
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#define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
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#define MiPdeToPpe(Pde) ((PMMPPE)MiAddressToPte(Pde))
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/* Check P*E boundaries */
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#define MiIsPteOnPdeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPpeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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#define MiIsPteOnPxeBoundary(PointerPte) \
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((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
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/* Sign extend 48 bits */
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#define MiProtoPteToPte(x) (PMMPTE)(((LONG64)(x)->u.Long) >> 16)
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//
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// Decodes a Prototype PTE into the underlying PTE
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//
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#define MiProtoPteToPte(x) \
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(PMMPTE)(((LONG64)(x)->u.Long) >> 16) /* Sign extend 48 bits */
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//
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// Decodes a Prototype PTE into the underlying PTE
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@ -285,3 +278,12 @@ MmInitGlobalKernelPageDirectory(VOID)
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/* Nothing to do */
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}
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BOOLEAN
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FORCEINLINE
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MiIsPdeForAddressValid(PVOID Address)
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{
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return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
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(MiAddressToPpe(Address)->u.Hard.Valid) &&
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(MiAddressToPde(Address)->u.Hard.Valid));
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}
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@ -5,157 +5,147 @@
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#define _MI_PAGING_LEVELS 2
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#define PDE_SHIFT 20
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/* Memory layout base addresses */
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#define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
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#define HYPER_SPACE 0xC0500000
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#define HYPER_SPACE_END 0xC08FFFFF
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#define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
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#define MI_PAGED_POOL_START (PVOID)0xE1000000
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#define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
|
||||
#define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
|
||||
|
||||
//
|
||||
// Number of bits corresponding to the area that a coarse page table entry represents (4KB)
|
||||
//
|
||||
#define PTE_SHIFT 12
|
||||
#define PTE_SIZE (1 << PTE_SHIFT)
|
||||
#define PTE_BASE 0xC0000000
|
||||
#define PDE_BASE 0xC0400000
|
||||
#define PDE_TOP 0xC04FFFFF
|
||||
#define PTE_TOP 0xC03FFFFF
|
||||
|
||||
//
|
||||
// Number of bits corresponding to the area that a coarse page table occupies (1KB)
|
||||
//
|
||||
#define CPT_SHIFT 10
|
||||
#define CPT_SIZE (1 << CPT_SHIFT)
|
||||
#define PTE_PER_PAGE 256
|
||||
#define PDE_PER_PAGE 4096
|
||||
#define PPE_PER_PAGE 1
|
||||
|
||||
/* Misc address definitions */
|
||||
#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
|
||||
#define MM_HIGHEST_VAD_ADDRESS \
|
||||
(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
|
||||
#define MI_MAPPING_RANGE_START ((ULONG)HYPER_SPACE)
|
||||
#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
|
||||
MI_HYPERSPACE_PTES * PAGE_SIZE)
|
||||
#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
|
||||
PAGE_SIZE)
|
||||
#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \
|
||||
PAGE_SIZE)
|
||||
#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \
|
||||
PAGE_SIZE)
|
||||
|
||||
/* Memory sizes */
|
||||
#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
|
||||
#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
|
||||
#define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
|
||||
#define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
|
||||
#define MI_SESSION_VIEW_SIZE (48 * _1MB)
|
||||
#define MI_SESSION_POOL_SIZE (16 * _1MB)
|
||||
#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
|
||||
#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
|
||||
#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
|
||||
MI_SESSION_POOL_SIZE + \
|
||||
MI_SESSION_IMAGE_SIZE + \
|
||||
MI_SESSION_WORKING_SET_SIZE)
|
||||
#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
|
||||
#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
|
||||
#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
|
||||
|
||||
/* Misc constants */
|
||||
#define MM_PTE_SOFTWARE_PROTECTION_BITS 6
|
||||
#define MI_MIN_SECONDARY_COLORS 8
|
||||
#define MI_SECONDARY_COLORS 64
|
||||
#define MI_MAX_SECONDARY_COLORS 1024
|
||||
#define MI_MAX_FREE_PAGE_LISTS 4
|
||||
#define MI_HYPERSPACE_PTES (256 - 1) /* Dee PDR definition */
|
||||
#define MI_ZERO_PTES (32) /* Dee PDR definition */
|
||||
#define MI_MAX_ZERO_BITS 21
|
||||
#define SESSION_POOL_LOOKASIDES 26 // CHECKME
|
||||
|
||||
/* MMPTE related defines */
|
||||
#define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
|
||||
#define MM_EMPTY_LIST ((ULONG_PTR)-1)
|
||||
|
||||
//
|
||||
// Base Addresses
|
||||
//
|
||||
#define PTE_BASE 0xC0000000
|
||||
#define PTE_TOP 0xC03FFFFF
|
||||
#define PDE_BASE 0xC0400000
|
||||
#define PDE_TOP 0xC04FFFFF
|
||||
#define HYPER_SPACE 0xC0500000
|
||||
|
||||
#if 0
|
||||
typedef struct _HARDWARE_PDE_ARMV6
|
||||
{
|
||||
ULONG Valid:1; // Only for small pages
|
||||
ULONG LargePage:1; // Note, if large then Valid = 0
|
||||
ULONG Buffered:1;
|
||||
ULONG Cached:1;
|
||||
ULONG NoExecute:1;
|
||||
ULONG Domain:4;
|
||||
ULONG Ecc:1;
|
||||
ULONG PageFrameNumber:22;
|
||||
} HARDWARE_PDE_ARMV6, *PHARDWARE_PDE_ARMV6;
|
||||
|
||||
typedef struct _HARDWARE_LARGE_PTE_ARMV6
|
||||
{
|
||||
ULONG Valid:1; // Only for small pages
|
||||
ULONG LargePage:1; // Note, if large then Valid = 0
|
||||
ULONG Buffered:1;
|
||||
ULONG Cached:1;
|
||||
ULONG NoExecute:1;
|
||||
ULONG Domain:4;
|
||||
ULONG Ecc:1;
|
||||
ULONG Accessed:1;
|
||||
ULONG Owner:1;
|
||||
ULONG CacheAttributes:3;
|
||||
ULONG ReadOnly:1;
|
||||
ULONG Shared:1;
|
||||
ULONG NonGlobal:1;
|
||||
ULONG SuperLagePage:1;
|
||||
ULONG Reserved:1;
|
||||
ULONG PageFrameNumber:12;
|
||||
} HARDWARE_LARGE_PTE_ARMV6, *PHARDWARE_LARGE_PTE_ARMV6;
|
||||
|
||||
typedef struct _HARDWARE_PTE_ARMV6
|
||||
{
|
||||
ULONG NoExecute:1;
|
||||
ULONG Valid:1;
|
||||
ULONG Buffered:1;
|
||||
ULONG Cached:1;
|
||||
ULONG Accessed:1;
|
||||
ULONG Owner:1;
|
||||
ULONG CacheAttributes:3;
|
||||
ULONG ReadOnly:1;
|
||||
ULONG Shared:1;
|
||||
ULONG NonGlobal:1;
|
||||
ULONG PageFrameNumber:20;
|
||||
} HARDWARE_PTE_ARMV6, *PHARDWARE_PTE_ARMV6;
|
||||
|
||||
C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG));
|
||||
C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG));
|
||||
C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG));
|
||||
#endif
|
||||
|
||||
/* For FreeLDR */
|
||||
typedef struct _PAGE_TABLE_ARM
|
||||
{
|
||||
HARDWARE_PTE_ARMV6 Pte[1024];
|
||||
} PAGE_TABLE_ARM, *PPAGE_TABLE_ARM;
|
||||
|
||||
typedef struct _PAGE_DIRECTORY_ARM
|
||||
{
|
||||
union
|
||||
{
|
||||
HARDWARE_PDE_ARMV6 Pde[4096];
|
||||
HARDWARE_LARGE_PTE_ARMV6 Pte[4096];
|
||||
};
|
||||
} PAGE_DIRECTORY_ARM, *PPAGE_DIRECTORY_ARM;
|
||||
|
||||
C_ASSERT(sizeof(PAGE_TABLE_ARM) == PAGE_SIZE);
|
||||
C_ASSERT(sizeof(PAGE_DIRECTORY_ARM) == (4 * PAGE_SIZE));
|
||||
|
||||
typedef enum _ARM_DOMAIN
|
||||
{
|
||||
FaultDomain,
|
||||
ClientDomain,
|
||||
InvalidDomain,
|
||||
ManagerDomain
|
||||
} ARM_DOMAIN;
|
||||
|
||||
#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.NonGlobal = 1)
|
||||
#define MI_MAKE_DIRTY_PAGE(x)
|
||||
#define MI_MAKE_ACCESSED_PAGE(x)
|
||||
#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
|
||||
#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.ReadOnly = 0)
|
||||
#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0)
|
||||
#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0)
|
||||
#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1)
|
||||
#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0)
|
||||
#define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
|
||||
#define MI_IS_PAGE_DIRTY(x) TRUE
|
||||
#define MI_IS_PAGE_LARGE(x) FALSE
|
||||
|
||||
/* Easy accessing PFN in PTE */
|
||||
#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
|
||||
|
||||
/* Macros for portable PTE modification */
|
||||
#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.NonGlobal = 1)
|
||||
#define MI_MAKE_DIRTY_PAGE(x)
|
||||
#define MI_MAKE_ACCESSED_PAGE(x)
|
||||
#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0)
|
||||
#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0)
|
||||
#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1)
|
||||
#define MI_IS_PAGE_LARGE(x) FALSE
|
||||
#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0)
|
||||
#define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
|
||||
#define MI_IS_PAGE_DIRTY(x) TRUE
|
||||
#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
|
||||
#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.ReadOnly = 0)
|
||||
|
||||
/* Convert an address to a corresponding PTE */
|
||||
#define MiAddressToPte(x) \
|
||||
((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2)))
|
||||
|
||||
/* Convert an address to a corresponding PDE */
|
||||
#define MiAddressToPde(x) \
|
||||
((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2)))
|
||||
|
||||
/* Convert an address to a corresponding PTE offset/index */
|
||||
#define MiAddressToPteOffset(x) \
|
||||
((((ULONG)(x)) << 12) >> 24)
|
||||
|
||||
/* Convert an address to a corresponding PDE offset/index */
|
||||
#define MiAddressToPdeOffset(x) \
|
||||
(((ULONG)(x)) >> 20)
|
||||
#define MiGetPdeOffset MiAddressToPdeOffset
|
||||
|
||||
/* Convert a PTE/PDE into a corresponding address */
|
||||
#define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
|
||||
#define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 18))
|
||||
|
||||
/* Translate between P*Es */
|
||||
#define MiPdeToPte(_Pde) ((PMMPTE)0) /* FIXME */
|
||||
#define MiPteToPde(_Pte) ((PMMPDE)0) /* FIXME */
|
||||
|
||||
/* Check P*E boundaries */
|
||||
#define MiIsPteOnPdeBoundary(PointerPte) \
|
||||
((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
|
||||
|
||||
//
|
||||
// Decodes a Prototype PTE into the underlying PTE
|
||||
//
|
||||
#define MiProtoPteToPte(x) \
|
||||
(PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
|
||||
(((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
|
||||
|
||||
//
|
||||
// Decodes a Prototype PTE into the underlying PTE
|
||||
//
|
||||
#define MiSubsectionPteToSubsection(x) \
|
||||
((x)->u.Subsect.WhichPool == PagedPool) ? \
|
||||
(PMMPTE)((ULONG_PTR)MmSubsectionBase + \
|
||||
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
|
||||
(x)->u.Subsect.SubsectionAddressLow << 3)) : \
|
||||
(PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
|
||||
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
|
||||
(x)->u.Subsect.SubsectionAddressLow << 3))
|
||||
|
||||
//
|
||||
// Number of bits corresponding to the area that a coarse page table occupies (1KB)
|
||||
//
|
||||
#define CPT_SHIFT 10
|
||||
|
||||
/* See PDR definition */
|
||||
#define MI_HYPERSPACE_PTES (256 - 1)
|
||||
#define MI_ZERO_PTES (32)
|
||||
#define MI_MAPPING_RANGE_START ((ULONG)HYPER_SPACE)
|
||||
#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
|
||||
MI_HYPERSPACE_PTES * PAGE_SIZE)
|
||||
#define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
|
||||
PAGE_SIZE)
|
||||
#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
|
||||
PAGE_SIZE)
|
||||
#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \
|
||||
PAGE_SIZE)
|
||||
#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \
|
||||
PAGE_SIZE)
|
||||
|
||||
/* Retrives the PDE entry for the given VA */
|
||||
#define MiGetPdeAddress(x) ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2)))
|
||||
#define MiAddressToPde(x) MiGetPdeAddress(x)
|
||||
|
||||
/* Retrieves the PTE entry for the given VA */
|
||||
#define MiGetPteAddress(x) ((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2)))
|
||||
#define MiAddressToPte(x) MiGetPteAddress(x)
|
||||
|
||||
/* Retrives the PDE offset for the given VA */
|
||||
#define MiGetPdeOffset(x) (((ULONG)(x)) >> 20)
|
||||
#define MiGetPteOffset(x) ((((ULONG)(x)) << 12) >> 24)
|
||||
#define MiAddressToPteOffset(x) MiGetPteOffset(x)
|
||||
|
||||
/* Convert a PTE into a corresponding address */
|
||||
#define MiPteToAddress(x) ((PVOID)((ULONG)(x) << 10))
|
||||
#define MiPdeToAddress(x) ((PVOID)((ULONG)(x) << 18))
|
||||
|
||||
|
|
|
|||
|
|
@ -9,39 +9,76 @@
|
|||
#define _MI_PAGING_LEVELS 2
|
||||
#endif
|
||||
|
||||
/* MMPTE related defines */
|
||||
#define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
|
||||
#define MM_EMPTY_LIST ((ULONG_PTR)-1)
|
||||
/* Memory layout base addresses */
|
||||
#define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
|
||||
#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
|
||||
#define HYPER_SPACE 0xC0400000
|
||||
#define HYPER_SPACE_END 0xC07FFFFF
|
||||
#define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
|
||||
#define MI_PAGED_POOL_START (PVOID)0xE1000000
|
||||
#define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
|
||||
#define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
|
||||
|
||||
/* FIXME: These are different for PAE */
|
||||
#define PTE_BASE 0xC0000000
|
||||
#define PDE_BASE 0xC0300000
|
||||
#define PDE_TOP 0xC0300FFF
|
||||
#define PTE_TOP 0xC03FFFFF
|
||||
#define HYPER_SPACE 0xC0400000
|
||||
#define HYPER_SPACE_END 0xC07FFFFF
|
||||
|
||||
#define PTE_PER_PAGE 0x400
|
||||
#define PDE_PER_PAGE 0x400
|
||||
#define PPE_PER_PAGE 1
|
||||
|
||||
/* Converting address to a corresponding PDE or PTE entry */
|
||||
#define MiAddressToPde(x) \
|
||||
((PMMPDE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE))
|
||||
#define MiAddressToPte(x) \
|
||||
((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE))
|
||||
#define MiAddressToPteOffset(x) \
|
||||
((((ULONG)(x)) << 10) >> 22)
|
||||
/* Misc address definitions */
|
||||
#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
|
||||
#define MM_HIGHEST_VAD_ADDRESS \
|
||||
(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
|
||||
#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
|
||||
#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
|
||||
MI_HYPERSPACE_PTES * PAGE_SIZE)
|
||||
#define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \
|
||||
PAGE_SIZE)
|
||||
#define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \
|
||||
PAGE_SIZE)
|
||||
#define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \
|
||||
PAGE_SIZE)
|
||||
|
||||
/* Convert a PTE into a corresponding address */
|
||||
#define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
|
||||
#define MiPdeToAddress(PDE) ((PVOID)((ULONG)(PDE) << 20))
|
||||
#define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
|
||||
#define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
|
||||
/* Memory sizes */
|
||||
#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
|
||||
#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
|
||||
#define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
|
||||
#define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
|
||||
#define MI_SESSION_VIEW_SIZE (48 * _1MB)
|
||||
#define MI_SESSION_POOL_SIZE (16 * _1MB)
|
||||
#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
|
||||
#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
|
||||
#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
|
||||
MI_SESSION_POOL_SIZE + \
|
||||
MI_SESSION_IMAGE_SIZE + \
|
||||
MI_SESSION_WORKING_SET_SIZE)
|
||||
#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
|
||||
#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
|
||||
#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
|
||||
|
||||
#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
|
||||
#define ADDR_TO_PDE_OFFSET(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
|
||||
#define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
|
||||
/* Misc constants */
|
||||
#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
|
||||
#define MI_MIN_SECONDARY_COLORS 8
|
||||
#define MI_SECONDARY_COLORS 64
|
||||
#define MI_MAX_SECONDARY_COLORS 1024
|
||||
#define MI_MAX_FREE_PAGE_LISTS 4
|
||||
#define MI_HYPERSPACE_PTES (256 - 1)
|
||||
#define MI_ZERO_PTES (32)
|
||||
#define MI_MAX_ZERO_BITS 21
|
||||
#define SESSION_POOL_LOOKASIDES 26
|
||||
|
||||
/* MMPTE related defines */
|
||||
#define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF)
|
||||
#define MM_EMPTY_LIST ((ULONG_PTR)-1)
|
||||
|
||||
#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
|
||||
|
||||
/* Easy accessing PFN in PTE */
|
||||
#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
|
||||
|
|
@ -68,19 +105,53 @@
|
|||
#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
|
||||
#endif
|
||||
|
||||
#define MI_HYPERSPACE_PTES (256 - 1)
|
||||
#define MI_ZERO_PTES (32)
|
||||
#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
|
||||
#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
|
||||
MI_HYPERSPACE_PTES * PAGE_SIZE)
|
||||
#define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \
|
||||
PAGE_SIZE)
|
||||
#define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \
|
||||
PAGE_SIZE)
|
||||
#define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \
|
||||
PAGE_SIZE)
|
||||
|
||||
/* On x86, these two are the same */
|
||||
#define MMPDE MMPTE
|
||||
#define PMMPDE PMMPTE
|
||||
#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
|
||||
|
||||
/* Convert an address to a corresponding PTE */
|
||||
#define MiAddressToPte(x) \
|
||||
((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE))
|
||||
|
||||
/* Convert an address to a corresponding PDE */
|
||||
#define MiAddressToPde(x) \
|
||||
((PMMPDE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE))
|
||||
|
||||
/* Convert an address to a corresponding PTE offset/index */
|
||||
#define MiAddressToPteOffset(x) \
|
||||
((((ULONG)(x)) << 10) >> 22)
|
||||
|
||||
/* Convert an address to a corresponding PDE offset/index */
|
||||
#define MiAddressToPdeOffset(x) \
|
||||
(((ULONG)(x)) / (1024 * PAGE_SIZE))
|
||||
#define MiGetPdeOffset MiAddressToPdeOffset
|
||||
|
||||
/* Convert a PTE/PDE into a corresponding address */
|
||||
#define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10))
|
||||
#define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 20))
|
||||
|
||||
/* Translate between P*Es */
|
||||
#define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
|
||||
#define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
|
||||
|
||||
/* Check P*E boundaries */
|
||||
#define MiIsPteOnPdeBoundary(PointerPte) \
|
||||
((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
|
||||
|
||||
//
|
||||
// Decodes a Prototype PTE into the underlying PTE
|
||||
//
|
||||
#define MiProtoPteToPte(x) \
|
||||
(PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
|
||||
(((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
|
||||
|
||||
//
|
||||
// Decodes a Prototype PTE into the underlying PTE
|
||||
//
|
||||
#define MiSubsectionPteToSubsection(x) \
|
||||
((x)->u.Subsect.WhichPool == PagedPool) ? \
|
||||
(PMMPTE)((ULONG_PTR)MmSubsectionBase + \
|
||||
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
|
||||
(x)->u.Subsect.SubsectionAddressLow << 3)) : \
|
||||
(PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
|
||||
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
|
||||
(x)->u.Subsect.SubsectionAddressLow << 3))
|
||||
|
|
|
|||
|
|
@ -6,55 +6,8 @@
|
|||
* PROGRAMMERS: ReactOS Portable Systems Group
|
||||
*/
|
||||
|
||||
#ifndef _M_AMD64
|
||||
|
||||
#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
|
||||
#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
|
||||
#define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
|
||||
#define MI_MAX_FREE_PAGE_LISTS 4
|
||||
|
||||
#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
|
||||
|
||||
#define MI_SESSION_VIEW_SIZE (48 * _1MB)
|
||||
#define MI_SESSION_POOL_SIZE (16 * _1MB)
|
||||
#define MI_SESSION_IMAGE_SIZE (8 * _1MB)
|
||||
#define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
|
||||
#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
|
||||
MI_SESSION_POOL_SIZE + \
|
||||
MI_SESSION_IMAGE_SIZE + \
|
||||
MI_SESSION_WORKING_SET_SIZE)
|
||||
|
||||
#define MI_SYSTEM_VIEW_SIZE (32 * _1MB)
|
||||
|
||||
#define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000
|
||||
#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000
|
||||
#define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
|
||||
#define MI_PAGED_POOL_START (PVOID)0xE1000000
|
||||
#define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
|
||||
#define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
|
||||
|
||||
#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL)
|
||||
|
||||
#define MI_MIN_SECONDARY_COLORS 8
|
||||
#define MI_SECONDARY_COLORS 64
|
||||
#define MI_MAX_SECONDARY_COLORS 1024
|
||||
|
||||
#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
|
||||
#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
|
||||
#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
|
||||
|
||||
#define MM_HIGHEST_VAD_ADDRESS \
|
||||
(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
|
||||
#define MI_LOWEST_VAD_ADDRESS (PVOID)MM_LOWEST_USER_ADDRESS
|
||||
|
||||
#define MI_DEFAULT_SYSTEM_PTE_COUNT 50000
|
||||
#define MI_MAX_ZERO_BITS 21
|
||||
|
||||
#endif /* !_M_AMD64 */
|
||||
|
||||
/* Make the code cleaner with some definitions for size multiples */
|
||||
#define _1KB (1024u)
|
||||
#define _1MB (1024 * _1KB)
|
||||
|
|
@ -72,28 +25,15 @@
|
|||
/* Size of a page directory */
|
||||
#define PD_SIZE (PDE_COUNT * sizeof(MMPDE))
|
||||
|
||||
/* Size of all page directories for a process */
|
||||
#define SYSTEM_PD_SIZE (PD_COUNT * PD_SIZE)
|
||||
|
||||
/* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
|
||||
#ifdef _M_IX86
|
||||
#define PD_COUNT 1
|
||||
#define PDE_COUNT 1024
|
||||
#define PTE_COUNT 1024
|
||||
C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
|
||||
#define MiIsPteOnPdeBoundary(PointerPte) \
|
||||
((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
|
||||
#elif _M_ARM
|
||||
#define PPE_PER_PAGE 1
|
||||
#define PDE_PER_PAGE 4096
|
||||
#define PTE_PER_PAGE 256
|
||||
#define PD_COUNT 1
|
||||
#define PDE_COUNT 4096
|
||||
#define PTE_COUNT 256
|
||||
#else
|
||||
/* Stop using these! */
|
||||
#define PD_COUNT PPE_PER_PAGE
|
||||
#define PDE_COUNT PDE_PER_PAGE
|
||||
#define PTE_COUNT PTE_PER_PAGE
|
||||
|
||||
/* Size of all page directories for a process */
|
||||
#define SYSTEM_PD_SIZE (PD_COUNT * PD_SIZE)
|
||||
#ifdef _M_IX86
|
||||
C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
|
||||
#endif
|
||||
|
||||
//
|
||||
|
|
@ -210,19 +150,6 @@ extern const ULONG MmProtectToValue[32];
|
|||
#define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
|
||||
(((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
|
||||
|
||||
//
|
||||
// Corresponds to MMPTE_SOFTWARE.Protection
|
||||
//
|
||||
#ifdef _M_IX86
|
||||
#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
|
||||
#elif _M_ARM
|
||||
#define MM_PTE_SOFTWARE_PROTECTION_BITS 6
|
||||
#elif _M_AMD64
|
||||
#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
|
||||
#else
|
||||
#error Define these please!
|
||||
#endif
|
||||
|
||||
//
|
||||
// Creates a software PTE with the given protection
|
||||
//
|
||||
|
|
@ -237,8 +164,13 @@ extern const ULONG MmProtectToValue[32];
|
|||
//
|
||||
// Special values for LoadedImports
|
||||
//
|
||||
#ifdef _WIN64
|
||||
#define MM_SYSLDR_NO_IMPORTS (PVOID)0xFFFFFFFFFFFFFFFEULL
|
||||
#define MM_SYSLDR_BOOT_LOADED (PVOID)0xFFFFFFFFFFFFFFFFULL
|
||||
#else
|
||||
#define MM_SYSLDR_NO_IMPORTS (PVOID)0xFFFFFFFE
|
||||
#define MM_SYSLDR_BOOT_LOADED (PVOID)0xFFFFFFFF
|
||||
#endif
|
||||
#define MM_SYSLDR_SINGLE_ENTRY 0x1
|
||||
|
||||
//
|
||||
|
|
@ -277,49 +209,15 @@ extern const ULONG MmProtectToValue[32];
|
|||
#define MI_GET_NEXT_COLOR() (MI_GET_PAGE_COLOR(++MmSystemPageColor))
|
||||
#define MI_GET_NEXT_PROCESS_COLOR(x) (MI_GET_PAGE_COLOR(++(x)->NextPageColor))
|
||||
|
||||
#ifndef _M_AMD64
|
||||
//
|
||||
// Decodes a Prototype PTE into the underlying PTE
|
||||
//
|
||||
#define MiProtoPteToPte(x) \
|
||||
(PMMPTE)((ULONG_PTR)MmPagedPoolStart + \
|
||||
(((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2))
|
||||
|
||||
//
|
||||
// Decodes a Prototype PTE into the underlying PTE
|
||||
//
|
||||
#define MiSubsectionPteToSubsection(x) \
|
||||
((x)->u.Subsect.WhichPool == PagedPool) ? \
|
||||
(PMMPTE)((ULONG_PTR)MmSubsectionBase + \
|
||||
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
|
||||
(x)->u.Subsect.SubsectionAddressLow << 3)) : \
|
||||
(PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \
|
||||
(((x)->u.Subsect.SubsectionAddressHigh << 7) | \
|
||||
(x)->u.Subsect.SubsectionAddressLow << 3))
|
||||
#endif
|
||||
|
||||
//
|
||||
// Prototype PTEs that don't yet have a pagefile association
|
||||
//
|
||||
#ifdef _M_AMD64
|
||||
#ifdef _WIN64
|
||||
#define MI_PTE_LOOKUP_NEEDED 0xffffffffULL
|
||||
#else
|
||||
#define MI_PTE_LOOKUP_NEEDED 0xFFFFF
|
||||
#endif
|
||||
|
||||
//
|
||||
// Number of session lists in the MM_SESSIONS_SPACE structure
|
||||
//
|
||||
#if defined(_M_AMD64)
|
||||
#define SESSION_POOL_LOOKASIDES 21
|
||||
#elif defined(_M_IX86)
|
||||
#define SESSION_POOL_LOOKASIDES 26
|
||||
#elif defined(_M_ARM)
|
||||
#define SESSION_POOL_LOOKASIDES 26 // CHECKME
|
||||
#else
|
||||
#error Not Defined!
|
||||
#endif
|
||||
|
||||
//
|
||||
// Number of session data and tag pages
|
||||
//
|
||||
|
|
@ -342,7 +240,7 @@ extern const ULONG MmProtectToValue[32];
|
|||
//
|
||||
// FIXFIX: These should go in ex.h after the pool merge
|
||||
//
|
||||
#ifdef _M_AMD64
|
||||
#ifdef _WIN64
|
||||
#define POOL_BLOCK_SIZE 16
|
||||
#else
|
||||
#define POOL_BLOCK_SIZE 8
|
||||
|
|
@ -385,11 +283,6 @@ extern const ULONG MmProtectToValue[32];
|
|||
#define POOL_BILLED_PROCESS_INVALID 13
|
||||
#define POOL_HEADER_SIZE_INVALID 32
|
||||
|
||||
#ifdef _M_ARM
|
||||
#define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct _POOL_DESCRIPTOR
|
||||
{
|
||||
POOL_TYPE PoolType;
|
||||
|
|
@ -413,7 +306,7 @@ typedef struct _POOL_HEADER
|
|||
{
|
||||
struct
|
||||
{
|
||||
#ifdef _M_AMD64
|
||||
#ifdef _WIN64
|
||||
USHORT PreviousSize:8;
|
||||
USHORT PoolIndex:8;
|
||||
USHORT BlockSize:8;
|
||||
|
|
@ -427,12 +320,12 @@ typedef struct _POOL_HEADER
|
|||
};
|
||||
ULONG Ulong1;
|
||||
};
|
||||
#ifdef _M_AMD64
|
||||
#ifdef _WIN64
|
||||
ULONG PoolTag;
|
||||
#endif
|
||||
union
|
||||
{
|
||||
#ifdef _M_AMD64
|
||||
#ifdef _WIN64
|
||||
PEPROCESS ProcessBilled;
|
||||
#else
|
||||
ULONG PoolTag;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,10 @@
|
|||
extern PMMPTE MmDebugPte;
|
||||
#endif
|
||||
|
||||
/* Helper macros */
|
||||
#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
|
||||
#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
|
||||
|
||||
/* GLOBALS *****************************************************************/
|
||||
|
||||
/* Template PTE and PDE for a kernel page */
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ MiGetPageTableForProcess(IN PEPROCESS Process,
|
|||
//
|
||||
// Get the PDE
|
||||
//
|
||||
PointerPde = MiGetPdeAddress(Address);
|
||||
PointerPde = MiAddressToPde(Address);
|
||||
if (PointerPde->u.Hard.Coarse.Valid)
|
||||
{
|
||||
//
|
||||
|
|
@ -141,7 +141,7 @@ MiGetPageTableForProcess(IN PEPROCESS Process,
|
|||
// Save it
|
||||
//
|
||||
//MmGlobalKernelPageDirectory[PdeOffset] = TempPde.u.Hard.AsUlong;
|
||||
//DPRINT1("KPD: %p PDEADDR: %p\n", &MmGlobalKernelPageDirectory[PdeOffset], MiGetPdeAddress(Address));
|
||||
//DPRINT1("KPD: %p PDEADDR: %p\n", &MmGlobalKernelPageDirectory[PdeOffset], MiAddressToPde(Address));
|
||||
|
||||
//
|
||||
// FIXFIX: Double check with Felix tomorrow
|
||||
|
|
@ -150,7 +150,7 @@ MiGetPageTableForProcess(IN PEPROCESS Process,
|
|||
//
|
||||
// Get the PTE for this 1MB region
|
||||
//
|
||||
PointerPte = MiGetPteAddress(MiGetPteAddress(Address));
|
||||
PointerPte = MiAddressToPte(MiAddressToPte(Address));
|
||||
DPRINT1("PointerPte: %p\n", PointerPte);
|
||||
|
||||
//
|
||||
|
|
@ -206,7 +206,7 @@ MiGetPageTableForProcess(IN PEPROCESS Process,
|
|||
//
|
||||
// Return the PTE
|
||||
//
|
||||
return MiGetPteAddress(Address);
|
||||
return MiAddressToPte(Address);
|
||||
}
|
||||
|
||||
MMPTE
|
||||
|
|
@ -647,8 +647,8 @@ MmInitGlobalKernelPageDirectory(VOID)
|
|||
// Good place to setup template PTE/PDEs.
|
||||
// We are lazy and pick a known-good PTE
|
||||
//
|
||||
MiArmTemplatePte = *MiGetPteAddress(0x80000000);
|
||||
MiArmTemplatePde = *MiGetPdeAddress(0x80000000);
|
||||
MiArmTemplatePte = *MiAddressToPte(0x80000000);
|
||||
MiArmTemplatePde = *MiAddressToPde(0x80000000);
|
||||
|
||||
//
|
||||
// Loop the 2GB of address space which belong to the kernel
|
||||
|
|
@ -693,7 +693,7 @@ MmGetPhysicalAddress(IN PVOID Address)
|
|||
// ARM Hack while we still use a section PTE
|
||||
//
|
||||
PMMPDE_HARDWARE PointerPde;
|
||||
PointerPde = MiGetPdeAddress(PCR);
|
||||
PointerPde = MiAddressToPde(PCR);
|
||||
ASSERT(PointerPde->u.Hard.Section.Valid == 1);
|
||||
PhysicalAddress.QuadPart = PointerPde->u.Hard.Section.PageFrameNumber;
|
||||
PhysicalAddress.QuadPart <<= CPT_SHIFT;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
#pragma alloc_text(INIT, MmInitGlobalKernelPageDirectory)
|
||||
#endif
|
||||
|
||||
#define ADDR_TO_PDE_OFFSET MiAddressToPdeOffset
|
||||
#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
|
||||
|
||||
/* GLOBALS *****************************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@
|
|||
#pragma alloc_text(INIT, MmInitGlobalKernelPageDirectory)
|
||||
#endif
|
||||
|
||||
|
||||
/* GLOBALS *****************************************************************/
|
||||
|
||||
#define PA_BIT_PRESENT (0)
|
||||
|
|
|
|||
Loading…
Reference in a new issue