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[UNIATA]

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- Update to 0.45a8
CORE-8432 #resolve

svn path=/trunk/; revision=63984
This commit is contained in:
Thomas Faber 2014-08-30 10:17:53 +00:00
parent 7ad0c2acd8
commit 038c129cf6
9 changed files with 86 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

1
reactos/drivers/storage/ide/uniata/atapi.h
View file

@ -938,6 +938,7 @@ typedef struct _IDENTIFY_DATA {
USHORT v30:1;
USHORT Reserved:10;
} SATA;
USHORT Flags;
} TransportMajor;
USHORT TransportMinor; // 223

21
reactos/drivers/storage/ide/uniata/bm_devs.h
View file

@ -319,12 +319,13 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
#define ATA_M88SX6042 0x604211ab
#define ATA_M88SX6081 0x608111ab
#define ATA_M88SX7042 0x704211ab
#define ATA_M88SX6101 0x610111ab
#define ATA_M88SX6102 0x610211ab
#define ATA_M88SX6111 0x611111ab
#define ATA_M88SX6121 0x612111ab
#define ATA_M88SX6141 0x614111ab
#define ATA_M88SX6145 0x614511ab
#define ATA_M88SE6101 0x610111ab
#define ATA_M88SE6102 0x610211ab
#define ATA_M88SE6111 0x611111ab
#define ATA_M88SE6121 0x612111ab
#define ATA_M88SE6141 0x614111ab
#define ATA_M88SE6145 0x614511ab
#define ATA_M88SE9123 0x91231b4b
#define ATA_MARVELL2_ID 0x1b4b
#define ATA_MICRON_ID 0x1042
@ -934,6 +935,7 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
PCI_DEV_HW_SPEC_BM( 6121, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6121" , UNIATA_SATA | UNIATA_AHCI ),
PCI_DEV_HW_SPEC_BM( 6141, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6141" , UNIATA_SATA | UNIATA_AHCI ),
PCI_DEV_HW_SPEC_BM( 6145, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6145" , UNIATA_SATA | UNIATA_AHCI ),
PCI_DEV_HW_SPEC_BM( 9123, 1b4b, 0x00, ATA_UDMA6, "Marvell 88SX9123" , UNIATA_SATA | UNIATA_AHCI ),
/* PCI_DEV_HW_SPEC_BM( 91a4, 1b4b, 0x00, ATA_UDMA6, "Marvell 88SE912x" , 0 ),*/
PCI_DEV_HW_SPEC_BM( 01bc, 10de, 0x00, ATA_UDMA5, "nVidia nForce" , 0 ),
@ -1139,11 +1141,12 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
*/
PCI_DEV_HW_SPEC_BM( 5513, 1039, 0xc2, ATA_UDMA2, "SiS ATA-xxx" , 0 ),
PCI_DEV_HW_SPEC_BM( 5513, 1039, 0x00, ATA_WDMA2, "SiS ATA-xxx" , 0 ),
PCI_DEV_HW_SPEC_BM( 5518, 1039, 0x00, ATA_UDMA6, "SiS 962/3" , SIS133NEW | SIS_BASE ),
PCI_DEV_HW_SPEC_BM( 0601, 1039, 0x00, ATA_WDMA2, "SiS ATA-xxx" , 0 ),
PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_UDMA6, "SiS PATA-1183" , SIS133NEW),
PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150, "SiS SATA 1182" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS SATA 183" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_SA150, "SiS 1183 SATA" , SISSATA),
PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150, "SiS 1182" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS 183 RAID" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0182, 1039, 0x00, ATA_SA150, "SiS SATA 182" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0181, 1039, 0x00, ATA_SA150, "SiS SATA 181" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0180, 1039, 0x00, ATA_SA150, "SiS SATA 180" , SISSATA | UNIATA_SATA),

1
reactos/drivers/storage/ide/uniata/config.h
View file

@ -43,6 +43,7 @@
/***************************************/
//#define UNIATA_DUMP_ATAPI
#define UNIATA_DUMP_RW
/***************************************/
// Optimization for uni-processor machines

34
reactos/drivers/storage/ide/uniata/id_ata.cpp
View file

@ -1677,6 +1677,25 @@ IssueIdentify(
ULONGLONG NativeNumOfSectors=0;
ULONGLONG cylinders=0;
ULONGLONG tmp_cylinders=0;
KdPrint2((PRINT_PREFIX "PhysLogSectorSize %#x, %#x, offset %#x\n",
deviceExtension->FullIdentifyData.PhysLogSectorSize,
deviceExtension->FullIdentifyData.LargeSectorSize,
deviceExtension->FullIdentifyData.LogicalSectorOffset
));
KdPrint2((PRINT_PREFIX "NV PM_Sup %d, PM_En %d, En %d, PM ver %#x ver %#x\n",
deviceExtension->FullIdentifyData.NVCache_PM_Supported,
deviceExtension->FullIdentifyData.NVCache_PM_Enabled,
deviceExtension->FullIdentifyData.NVCache_Enabled,
deviceExtension->FullIdentifyData.NVCache_PM_Version,
deviceExtension->FullIdentifyData.NVCache_Version
));
KdPrint2((PRINT_PREFIX "R-rate %#x\n",
deviceExtension->FullIdentifyData.NominalMediaRotationRate
));
// Read very-old-style drive geometry
KdPrint2((PRINT_PREFIX "CHS %#x:%#x:%#x\n",
deviceExtension->FullIdentifyData.NumberOfCylinders,
@ -2243,6 +2262,7 @@ AtapiResetController__(
UniataAhciReset(HwDeviceExtension, j);
} else {
KdPrint2((PRINT_PREFIX " skip not implemented\n"));
continue;
}
} else {
KdPrint2((PRINT_PREFIX " ATA path, chan %#x\n", chan));
@ -5181,6 +5201,7 @@ continue_PIO:
} else {
KdPrint2((PRINT_PREFIX "AtapiInterrupt: !DRQ, !BUSY, WordsLeft %#x\n", AtaReq->WordsLeft));
if (AtaReq->WordsLeft) {
// Funky behaviour seen with PCI IDE (not all, just one).
@ -5568,7 +5589,7 @@ IntrPrepareResetController:
} else if (interruptReason == (ATAPI_IR_IO_toHost | ATAPI_IR_COD_Cmd) && !(statusByte & IDE_STATUS_DRQ)) {
KdPrint2((PRINT_PREFIX "AtapiInterrupt: interruptReason = CompleteRequest\n"));
// Command complete. We exactly know this because os IReason.
// Command complete. We exactly know this because of IReason.
if(DmaTransfer) {
KdPrint2((PRINT_PREFIX "AtapiInterrupt: CompleteRequest, was DmaTransfer\n"));
@ -5582,6 +5603,9 @@ IntrPrepareResetController:
AtaReq->DataBuffer += wordCount;
AtaReq->WordsLeft -= wordCount;
AtaReq->WordsTransfered += wordCount;
KdPrint2((PRINT_PREFIX "AtapiInterrupt: wordCount %#x, WordsTransfered %#x\n", wordCount, AtaReq->WordsTransfered));
}
//if (AtaReq->WordsLeft) {
// status = SRB_STATUS_DATA_OVERRUN;
@ -6921,6 +6945,13 @@ AtapiSendCommand(
case SCSIOP_WRITE16:
// all right
break;
case SCSIOP_READ_CD:
case SCSIOP_READ_CD_MSF:
if(deviceExtension->opt_AtapiDmaRawRead) {
// all right
break;
}
/* FALL THROUGH */
default:
KdPrint2((PRINT_PREFIX "AtapiSendCommand: SRB_STATUS_BUSY\n"));
return SRB_STATUS_BUSY;
@ -7100,6 +7131,7 @@ call_dma_setup:
}
break;
case SCSIOP_READ_CD:
case SCSIOP_READ_CD_MSF:
if(deviceExtension->opt_AtapiDmaRawRead)
goto call_dma_setup;
break;

1
reactos/drivers/storage/ide/uniata/id_dma.cpp
View file

@ -105,6 +105,7 @@ AtapiVirtToPhysAddr_(
ULONG addr;
ph_addr = MmGetPhysicalAddress(data);
KdPrint3((PRINT_PREFIX "AtapiVirtToPhysAddr_: %x -> %8.8x:%8.8x\n", data, ph_addr.HighPart, ph_addr.LowPart));
if(!ph_addru && ph_addr.HighPart) {
// do so until we add 64bit address support
// or some workaround

9
reactos/drivers/storage/ide/uniata/id_init.cpp
View file

@ -355,9 +355,9 @@ unknown_dev:
}
static BUSMASTER_CONTROLLER_INFORMATION const SiSAdapters[] = {
PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_UDMA6, "SiS 1183" , SIS133NEW),
PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_SA150, "SiS 1183 IDE" , SIS133NEW),
PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150, "SiS 1182" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS 183" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS 183 RAID" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0182, 1039, 0x00, ATA_SA150, "SiS 182" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0181, 1039, 0x00, ATA_SA150, "SiS 181" , SISSATA | UNIATA_SATA),
PCI_DEV_HW_SPEC_BM( 0180, 1039, 0x00, ATA_SA150, "SiS 180" , SISSATA | UNIATA_SATA),
@ -376,7 +376,7 @@ unknown_dev:
/* PCI_DEV_HW_SPEC_BM( 0640, 1039, 0x00, ATA_UDMA4, "SiS 640" , SIS_SOUTH ),*/
PCI_DEV_HW_SPEC_BM( 0635, 1039, 0x00, ATA_UDMA5, "SiS 635" , SIS100NEW ),
PCI_DEV_HW_SPEC_BM( 0633, 1039, 0x00, ATA_UDMA5, "SiS 633" , SIS100NEW ),
PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x00, ATA_UDMA5, "SiS 630S" , SIS100OLD ),
PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x30, ATA_UDMA5, "SiS 630S" , SIS100OLD ),
PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x00, ATA_UDMA4, "SiS 630" , SIS66 ),
PCI_DEV_HW_SPEC_BM( 0620, 1039, 0x00, ATA_UDMA4, "SiS 620" , SIS66 ),
@ -2390,6 +2390,9 @@ AtapiChipInit(
break;
}
}
if(deviceExtension->HwFlags & UNIATA_SATA) {
// do nothing for SATA
} else
if(ChipType == SIS133NEW) {
USHORT tmp16;
// check 80-pin cable

26
reactos/drivers/storage/ide/uniata/id_sata.cpp
View file

@ -645,9 +645,7 @@ UniataAhciInit(
PHW_CHANNEL chan;
ULONG offs;
ULONG BaseMemAddress;
#ifdef DBG
ULONG PI;
#endif //DBG
ULONG CAP;
ULONG CAP2;
ULONG BOHC;
@ -757,11 +755,12 @@ UniataAhciInit(
if(CAP & AHCI_CAP_SAM) {
KdPrint2((PRINT_PREFIX " AHCI legasy SATA\n"));
}
#ifdef DBG
/* get the number of HW channels */
PI = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_PI);
deviceExtension->AHCI_PI = PI;
KdPrint2((PRINT_PREFIX " AHCI PI %#x\n", PI));
#endif //DBG
CAP2 = UniataAhciReadHostPort4(deviceExtension, IDX_AHCI_CAP2);
if(CAP2 & AHCI_CAP2_BOH) {
KdPrint2((PRINT_PREFIX " retry BOHC\n"));
@ -977,18 +976,22 @@ UniataAhciDetect(
max((CAP & AHCI_CAP_NOP_MASK)+1, n);
KdPrint2((PRINT_PREFIX " CommandSlots %d\n", (CAP & AHCI_CAP_NCS_MASK)>>8 ));
KdPrint2((PRINT_PREFIX " Channels %d\n", n));
KdPrint2((PRINT_PREFIX " Detected Channels %d / %d\n", NumberChannels, n));
switch(deviceExtension->DevID) {
case ATA_M88SX6111:
case ATA_M88SE6111:
KdPrint2((PRINT_PREFIX " Marvell M88SE6111 -> 1\n"));
NumberChannels = 1;
break;
case ATA_M88SX6121:
NumberChannels = 2;
case ATA_M88SE6121:
KdPrint2((PRINT_PREFIX " Marvell M88SE6121 -> 2\n"));
NumberChannels = min(NumberChannels, 2);
break;
case ATA_M88SX6141:
case ATA_M88SX6145:
NumberChannels = 4;
case ATA_M88SE6141:
case ATA_M88SE6145:
case ATA_M88SE9123:
KdPrint2((PRINT_PREFIX " Marvell M88SE614x/9123 -> 4\n"));
NumberChannels = min(NumberChannels, 4);
break;
} // switch()
@ -997,6 +1000,7 @@ UniataAhciDetect(
found = FALSE;
goto exit_detect;
}
KdPrint2((PRINT_PREFIX " Adjusted Channels %d\n", NumberChannels));
#ifdef DBG
v_Mj = ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f);

14
reactos/drivers/storage/ide/uniata/id_sata.h
View file

@ -407,8 +407,18 @@ BuildAhciInternalSrb (
IN ULONG Length = 0
);
#define UniataAhciChanImplemented(deviceExtension, c) \
(((deviceExtension)->AHCI_PI) & (1 << c))
__inline
BOOLEAN
UniataAhciChanImplemented(
IN PHW_DEVICE_EXTENSION deviceExtension,
IN ULONG c
)
{
#ifdef DBG
KdPrint2((PRINT_PREFIX "imp: %#x & %#x\n", (deviceExtension)->AHCI_PI, (1<<c) ));
#endif
return (((deviceExtension)->AHCI_PI) & ((ULONG)1 << c)) ? TRUE : FALSE;
} // end UniataAhciChanImplemented()
#endif //__UNIATA_SATA__H__

10
reactos/drivers/storage/ide/uniata/uniata_ver.h
View file

@ -1,10 +1,10 @@
#define UNIATA_VER_STR "45a3"
#define UNIATA_VER_DOT 0.45.1.3
#define UNIATA_VER_STR "45a8"
#define UNIATA_VER_DOT 0.45.1.8
#define UNIATA_VER_MJ 0
#define UNIATA_VER_MN 45
#define UNIATA_VER_SUB_MJ 1
#define UNIATA_VER_SUB_MN 3
#define UNIATA_VER_DOT_COMMA 0,45,1,3
#define UNIATA_VER_DOT_STR "0.45.1.3"
#define UNIATA_VER_SUB_MN 8
#define UNIATA_VER_DOT_COMMA 0,45,1,8
#define UNIATA_VER_DOT_STR "0.45.1.8"
#define UNIATA_VER_YEAR 2014
#define UNIATA_VER_YEAR_STR "2014"