Intravision/reactos
1
0
Fork 0
mirror of https://github.com/reactos/reactos.git synced 2025-07-31 17:01:53 +00:00
Code Issues Projects Releases Packages Wiki Activity

[FREELDR]

Browse source 
set CF, ZF and SF based on REGS structure, when doing int's. Fixes slowness during 2nd stage boot in QEMU. Dedicated to Samuel.

svn path=/trunk/; revision=54062
This commit is contained in:
Timo Kreuzer 2011-10-09 16:26:19 +00:00
parent 975d94d909
commit 0386650c63
1 changed files with 18 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

21
reactos/boot/freeldr/freeldr/arch/realmode/int386.inc
View file

@ -1,6 +1,10 @@
#include "../../include/arch/pc/pcbios.h"
#define EFLAGS_CF HEX(01)
#define EFLAGS_ZF HEX(40)
#define EFLAGS_SF HEX(80)
Int386:
/* Save all registers + segment registers */
push ds
@ -13,6 +17,20 @@ Int386:
mov al, byte ptr ds:[BSS_IntVector]
mov byte ptr ds:[Int386_vector_opcode], al
/* Get current EFLAGS and mask CF, ZF and SF */
pushf
pop cx
and cx, not (EFLAGS_CF or EFLAGS_ZF or EFLAGS_SF)
/* Get flags CF, ZF and SF from the REGS structure */
mov ax, word ptr cs:[BSS_RegisterSet + REGS_EFLAGS]
and ax, (EFLAGS_CF or EFLAGS_ZF or EFLAGS_SF)
/* Combine flags and set them */
or ax, cx
push ax
popf
/* Setup the registers */
mov ax, word ptr cs:[BSS_RegisterSet + REGS_DS]
mov ds, ax
@ -31,9 +49,6 @@ Int386:
mov edi, dword ptr cs:[BSS_RegisterSet + REGS_EDI]
mov ebp, dword ptr cs:[BSS_RegisterSet + REGS_EBP]
/* Do not set the flags register */
/* only return its value in regsout */
/* Call the interrupt vector */
/*int Int386_vector*/
.byte HEX(0cd)