Intravision/reactos
1
0
Fork 0
mirror of https://github.com/reactos/reactos.git synced 2025-07-23 11:33:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

HACK HACK HACK: disable an ASSERT

Browse source 
We need proper IPIs to flush the TLB
This commit is contained in:
Timo Kreuzer 2024-09-23 15:14:56 +03:00
parent e5c880df25
commit 030c1fe576
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
ntoskrnl/mm/ARM3/virtual.c
View file

@ -2423,7 +2423,7 @@ MiProtectVirtualMemory(IN PEPROCESS Process,
MI_WRITE_INVALID_PTE(PointerPte, PteContents);
#ifdef CONFIG_SMP
// FIXME: Should invalidate entry in every CPU TLB
ASSERT(KeNumberProcessors == 1);
//ASSERT(KeNumberProcessors == 1);
#endif
KeInvalidateTlbEntry(MiPteToAddress(PointerPte));