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https://github.com/reactos/reactos.git
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[BOOTVID] Simplify the code by introducing and using IO port helper macros.
- Move around two header includes. - Remove a redundant assignment in VgaInterpretCmdStream().
This commit is contained in:
Hermès Bélusca-Maïto
parent
0f3f8b2a35
commit
025cfb108b
3 changed files with 67 additions and 64 deletions
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@ -1,8 +1,5 @@
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#include "precomp.h"
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#include <ntifs.h>
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#include <ndk/halfuncs.h>
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/* PRIVATE FUNCTIONS *********************************************************/
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static BOOLEAN
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@ -227,9 +224,6 @@ VgaInterpretCmdStream(IN PUSHORT CmdStream)
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/* Unknown major function, fail */
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return FALSE;
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}
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/* Get the next command */
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Cmd = *CmdStream;
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}
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/* If we got here, return success */
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@ -245,114 +239,115 @@ VgaIsPresent(VOID)
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UCHAR i;
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/* Read the VGA Address Register */
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VgaReg = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE);
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VgaReg = __inpb(0x3CE);
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/* Select Read Map Select Register */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4);
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__outpb(0x3CE, 4);
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/* Read it back...it should be 4 */
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if (((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE)) & 0xF) != 4) return FALSE;
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/* Read it back... it should be 4 */
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if ((__inpb(0x3CE) & 0xF) != 4)
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return FALSE;
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/* Read the VGA Data Register */
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VgaReg2 = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF);
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VgaReg2 = __inpb(0x3CF);
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/* Enable all planes */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 3);
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__outpb(0x3CF, 3);
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/* Read it back...it should be 3 */
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if (READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) != 0x3)
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/* Read it back... it should be 3 */
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if (__inpb(0x3CF) != 0x3)
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{
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/* Reset the registers and fail */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0);
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__outpb(0x3CF, 0);
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return FALSE;
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}
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/* Select Bit Mask Register */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8);
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__outpb(0x3CE, 8);
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/* Read it back...it should be 8 */
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if (((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE)) & 0xF) != 8)
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/* Read it back... it should be 8 */
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if ((__inpb(0x3CE) & 0xF) != 8)
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{
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/* Reset the registers and fail */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0);
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__outpb(0x3CE, 4);
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__outpb(0x3CF, 0);
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return FALSE;
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}
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/* Read the VGA Data Register */
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VgaReg3 = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF);
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VgaReg3 = __inpb(0x3CF);
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/* Loop bitmasks */
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for (i = 0xBB; i; i >>= 1)
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{
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/* Set bitmask */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, i);
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__outpb(0x3CF, i);
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/* Read it back...it should be the same */
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if (READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) != i)
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/* Read it back... it should be the same */
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if (__inpb(0x3CF) != i)
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{
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/* Reset the registers and fail */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0xFF);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0);
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__outpb(0x3CF, 0xFF);
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__outpb(0x3CE, 4);
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__outpb(0x3CF, 0);
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return FALSE;
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}
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}
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/* Select Read Map Select Register */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 4);
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__outpb(0x3CE, 4);
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/* Read it back...it should be 3 */
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if (READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) != 3)
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/* Read it back... it should be 3 */
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if (__inpb(0x3CF) != 3)
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{
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/* Reset the registers and fail */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 0xFF);
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__outpb(0x3CF, 0);
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__outpb(0x3CE, 8);
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__outpb(0x3CF, 0xFF);
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return FALSE;
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}
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/* Write the registers we read earlier */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, VgaReg2);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, VgaReg3);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, VgaReg);
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__outpb(0x3CF, VgaReg2);
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__outpb(0x3CE, 8);
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__outpb(0x3CF, VgaReg3);
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__outpb(0x3CE, VgaReg);
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/* Read sequencer address */
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SeqReg = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4);
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SeqReg = __inpb(0x3C4);
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/* Select memory mode register */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4, 4);
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__outpb(0x3C4, 4);
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/* Read it back...it should still be 4 */
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if (((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4)) & 7) != 4)
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/* Read it back... it should still be 4 */
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if ((__inpb(0x3C4) & 7) != 4)
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{
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/* Fail */
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/* Fail */
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return FALSE;
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}
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/* Read sequencer Data */
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SeqReg2 = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5);
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SeqReg2 = __inpb(0x3C5);
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/* Write null plane */
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WRITE_PORT_USHORT((PUSHORT)VgaRegisterBase + 0x3C4, 0x100);
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__outpw(0x3C4, 0x100);
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/* Write sequencer flag */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5, SeqReg2 ^ 8);
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__outpb(0x3C5, SeqReg2 ^ 8);
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/* Read it back */
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if ((READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5)) != (SeqReg2 ^ 8))
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if (__inpb(0x3C5) != (SeqReg2 ^ 8))
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{
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/* Not the same value...restore registers and fail */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5, 2);
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WRITE_PORT_USHORT((PUSHORT)VgaRegisterBase + 0x3C4, 0x300);
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/* Not the same value... restore registers and fail */
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__outpb(0x3C5, 2);
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__outpw(0x3C4, 0x300);
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return FALSE;
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}
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/* Now write the registers we read */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C5, SeqReg2);
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WRITE_PORT_USHORT((PUSHORT)VgaRegisterBase + 0x3C4, 0x300);
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3C4, SeqReg);
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__outpb(0x3C5, SeqReg2);
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__outpw(0x3C4, 0x300);
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__outpb(0x3C4, SeqReg);
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/* VGA is present! */
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return TRUE;
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@ -458,7 +453,7 @@ VidInitialize(IN BOOLEAN SetMode)
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/* Initialize it */
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VgaInterpretCmdStream(AT_Initialization);
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}
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/* VGA is ready */
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return TRUE;
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}
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@ -70,12 +70,6 @@ ULONG curr_y = 0;
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static ULONG VidTextColor = 0xF;
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static BOOLEAN CarriageReturn = FALSE;
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#define __outpb(Port, Value) \
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WRITE_PORT_UCHAR((PUCHAR)(VgaRegisterBase + (Port)), (UCHAR)(Value))
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#define __outpw(Port, Value) \
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WRITE_PORT_USHORT((PUSHORT)(VgaRegisterBase + (Port)), (USHORT)(Value))
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/* PRIVATE FUNCTIONS *********************************************************/
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static VOID
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@ -88,7 +82,7 @@ ReadWriteMode(IN UCHAR Mode)
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__outpb(0x3CE, 5);
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/* Get the current register value, minus the current mode */
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Value = READ_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF) & 0xF4;
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Value = __inpb(0x3CF) & 0xF4;
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/* Set the new mode */
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__outpb(0x3CF, Mode | Value);
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@ -750,10 +744,10 @@ NTAPI
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VidCleanUp(VOID)
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{
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/* Select bit mask register */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CE, 8);
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__outpb(0x3CE, 8);
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/* Clear it */
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WRITE_PORT_UCHAR((PUCHAR)VgaRegisterBase + 0x3CF, 255);
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__outpb(0x3CF, 255);
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}
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/*
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@ -2,12 +2,14 @@
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#define _BOOTVID_PCH_
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#include <ntddk.h>
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#include <ntifs.h>
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#include <ndk/halfuncs.h>
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#include <drivers/bootvid/bootvid.h>
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/* Define if FontData has upside down characters */
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#undef CHAR_GEN_UPSIDE_DOWN
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#define BOOTCHAR_HEIGHT 13
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#define BOOTCHAR_HEIGHT 13
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/* Command Stream Definitions */
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#define CMD_STREAM_WRITE 0x0
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@ -40,11 +42,23 @@ NTAPI
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InitializePalette(VOID);
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/* Globals */
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extern USHORT AT_Initialization[];
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extern ULONG curr_x;
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extern ULONG curr_y;
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extern ULONG_PTR VgaRegisterBase;
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extern ULONG_PTR VgaBase;
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extern USHORT AT_Initialization[];
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extern UCHAR FontData[256 * BOOTCHAR_HEIGHT];
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#define __inpb(Port) \
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READ_PORT_UCHAR((PUCHAR)(VgaRegisterBase + (Port)))
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#define __inpw(Port) \
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READ_PORT_USHORT((PUSHORT)(VgaRegisterBase + (Port)))
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#define __outpb(Port, Value) \
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WRITE_PORT_UCHAR((PUCHAR)(VgaRegisterBase + (Port)), (UCHAR)(Value))
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#define __outpw(Port, Value) \
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WRITE_PORT_USHORT((PUSHORT)(VgaRegisterBase + (Port)), (USHORT)(Value))
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#endif /* _BOOTVID_PCH_ */
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