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- Reimplement HalpAssignPCISlotResources() (based on the old implementation, just changing to the new way of reading/writing PCI config space, formatting and other misc changes).
svn path=/trunk/; revision=27330
This commit is contained in:
Aleksey Bragin
parent
129a800f3f
commit
017976049f
1 changed files with 127 additions and 3 deletions
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@ -485,6 +485,14 @@ HalpReleasePciDeviceForDebugging(IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
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return STATUS_NOT_IMPLEMENTED;
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}
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static ULONG STDCALL
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PciSize(ULONG Base, ULONG Mask)
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{
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ULONG Size = Mask & Base; /* Find the significant bits */
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Size = Size & ~(Size - 1); /* Get the lowest of them to find the decode size */
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return Size;
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}
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NTSTATUS
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NTAPI
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HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler,
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@ -494,10 +502,126 @@ HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject OPTIONAL,
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IN ULONG Slot,
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IN OUT PCM_RESOURCE_LIST *pAllocatedResources)
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IN OUT PCM_RESOURCE_LIST *AllocatedResources)
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{
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KEBUGCHECK(0);
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return STATUS_SUCCESS;
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PCI_COMMON_CONFIG PciConfig;
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SIZE_T Address;
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SIZE_T ResourceCount;
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ULONG Size[PCI_TYPE0_ADDRESSES];
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NTSTATUS Status = STATUS_SUCCESS;
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UCHAR Offset;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor;
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PCI_SLOT_NUMBER SlotNumber;
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ULONG WriteBuffer;
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/* FIXME: Should handle 64-bit addresses */
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/* Read configuration data */
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SlotNumber.u.AsULONG = Slot;
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HalpReadPCIConfig(BusHandler, SlotNumber, &PciConfig, 0, PCI_COMMON_HDR_LENGTH);
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/* Check if we read it correctly */
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if (PciConfig.VendorID == PCI_INVALID_VENDORID)
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return STATUS_NO_SUCH_DEVICE;
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/* Read the PCI configuration space for the device and store base address and
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size information in temporary storage. Count the number of valid base addresses */
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ResourceCount = 0;
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for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
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{
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if (0xffffffff == PciConfig.u.type0.BaseAddresses[Address])
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PciConfig.u.type0.BaseAddresses[Address] = 0;
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/* Memory resource */
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if (0 != PciConfig.u.type0.BaseAddresses[Address])
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{
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ResourceCount++;
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Offset = FIELD_OFFSET(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
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/* Write 0xFFFFFFFF there */
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WriteBuffer = 0xffffffff;
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HalpWritePCIConfig(BusHandler, SlotNumber, &WriteBuffer, Offset, sizeof(ULONG));
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/* Read that figure back from the config space */
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HalpReadPCIConfig(BusHandler, SlotNumber, &Size[Address], Offset, sizeof(ULONG));
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/* Write back initial value */
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HalpWritePCIConfig(BusHandler, SlotNumber, &PciConfig.u.type0.BaseAddresses[Address], Offset, sizeof(ULONG));
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}
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}
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/* Interrupt resource */
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if (0 != PciConfig.u.type0.InterruptLine)
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ResourceCount++;
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/* Allocate output buffer and initialize */
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*AllocatedResources = ExAllocatePoolWithTag(
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PagedPool,
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sizeof(CM_RESOURCE_LIST) +
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(ResourceCount - 1) * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR),
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TAG('H','a','l',' '));
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if (NULL == *AllocatedResources)
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return STATUS_NO_MEMORY;
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(*AllocatedResources)->Count = 1;
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(*AllocatedResources)->List[0].InterfaceType = PCIBus;
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(*AllocatedResources)->List[0].BusNumber = BusHandler->BusNumber;
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(*AllocatedResources)->List[0].PartialResourceList.Version = 1;
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(*AllocatedResources)->List[0].PartialResourceList.Revision = 1;
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(*AllocatedResources)->List[0].PartialResourceList.Count = ResourceCount;
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Descriptor = (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
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/* Store configuration information */
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for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
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{
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if (0 != PciConfig.u.type0.BaseAddresses[Address])
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{
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if (/*PCI_BASE_ADDRESS_SPACE_MEMORY*/ 0 ==
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(PciConfig.u.type0.BaseAddresses[Address] & 0x1))
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{
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Descriptor->Type = CmResourceTypeMemory;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE; /* FIXME Just a guess */
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Descriptor->u.Memory.Start.QuadPart = (PciConfig.u.type0.BaseAddresses[Address] & PCI_ADDRESS_MEMORY_ADDRESS_MASK);
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Descriptor->u.Memory.Length = PciSize(Size[Address], PCI_ADDRESS_MEMORY_ADDRESS_MASK);
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}
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else if (PCI_ADDRESS_IO_SPACE ==
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(PciConfig.u.type0.BaseAddresses[Address] & 0x1))
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{
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
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Descriptor->Flags = CM_RESOURCE_PORT_IO; /* FIXME Just a guess */
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Descriptor->u.Port.Start.QuadPart = PciConfig.u.type0.BaseAddresses[Address] &= PCI_ADDRESS_IO_ADDRESS_MASK;
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Descriptor->u.Port.Length = PciSize(Size[Address], PCI_ADDRESS_IO_ADDRESS_MASK & 0xffff);
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}
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else
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{
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ASSERT(FALSE);
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return STATUS_UNSUCCESSFUL;
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}
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Descriptor++;
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}
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}
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if (0 != PciConfig.u.type0.InterruptLine)
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{
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Descriptor->Type = CmResourceTypeInterrupt;
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Descriptor->ShareDisposition = CmResourceShareShared; /* FIXME Just a guess */
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Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE; /* FIXME Just a guess */
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Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
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Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
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Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
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Descriptor++;
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}
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ASSERT(Descriptor == (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors + ResourceCount);
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/* FIXME: Should store the resources in the registry resource map */
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return Status;
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}
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ULONG
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