diff --git a/hal/halx86/generic/bios.c b/hal/halx86/generic/bios.c
index 329f0d227f7..cc8e57d1721 100644
--- a/hal/halx86/generic/bios.c
+++ b/hal/halx86/generic/bios.c
@@ -81,35 +81,35 @@ HalpPushInt(IN PHAL_BIOS_FRAME BiosFrame,
 {
     PUSHORT Stack;
     ULONG Eip;
-    
+
     /* Calculate stack address (SP) */
     Stack = (PUSHORT)(BiosFrame->SsBase + (BiosFrame->Esp & 0xFFFF));
-    
+
     /* Push EFlags */
     Stack--;
     *Stack = BiosFrame->EFlags & 0xFFFF;
-    
+
     /* Push CS */
     Stack--;
     *Stack = BiosFrame->SegCs & 0xFFFF;
-        
+
     /* Push IP */
     Stack--;
     *Stack = BiosFrame->Eip & 0xFFFF;
-    
+
     /* Compute new CS:IP from the IVT address for this interrupt entry */
     Eip = *(PULONG)(Interrupt * 4);
     BiosFrame->Eip = Eip & 0xFFFF;
     BiosFrame->SegCs = Eip >> 16;
-    
+
     /* Update stack address */
     BiosFrame->Esp = (ULONG_PTR)Stack & 0xFFFF;
-    
+
     /* Update CS to linear */
     BiosFrame->CsBase = BiosFrame->SegCs << 4;
     BiosFrame->CsLimit = 0xFFFF;
     BiosFrame->CsFlags = 0;
-    
+
     /* We're done */
     return TRUE;
 }
@@ -120,19 +120,19 @@ HalpOpcodeINTnn(IN PHAL_BIOS_FRAME BiosFrame)
 {
     UCHAR Interrupt;
     PKTRAP_FRAME TrapFrame;
-    
+
     /* Convert SS to linear */
     BiosFrame->SsBase = BiosFrame->SegSs << 4;
     BiosFrame->SsLimit = 0xFFFF;
     BiosFrame->SsFlags = 0;
-    
+
     /* Increase EIP and validate */
     BiosFrame->Eip++;
     if (BiosFrame->Eip > BiosFrame->CsLimit) return FALSE;
-    
+
     /* Read interrupt number */
     Interrupt = *(PUCHAR)(BiosFrame->CsBase + BiosFrame->Eip);
-    
+
     /* Increase EIP and push the interrupt */
     BiosFrame->Eip++;
     if (HalpPushInt(BiosFrame, Interrupt))
@@ -143,11 +143,11 @@ HalpOpcodeINTnn(IN PHAL_BIOS_FRAME BiosFrame)
         TrapFrame->HardwareEsp = BiosFrame->Esp;
         TrapFrame->SegCs = BiosFrame->SegCs;
         TrapFrame->EFlags = BiosFrame->EFlags;
-        
+
         /* Success */
         return TRUE;
     }
-    
+
     /* Failure */
     return FALSE;
 }
@@ -158,7 +158,7 @@ HalpDispatchV86Opcode(IN PKTRAP_FRAME TrapFrame)
 {
     UCHAR Instruction;
     HAL_BIOS_FRAME BiosFrame;
-    
+
     /* Fill out the BIOS frame */
     BiosFrame.TrapFrame = TrapFrame;
     BiosFrame.SegSs = TrapFrame->HardwareSegSs;
@@ -167,15 +167,15 @@ HalpDispatchV86Opcode(IN PKTRAP_FRAME TrapFrame)
     BiosFrame.SegCs = TrapFrame->SegCs;
     BiosFrame.Eip = TrapFrame->Eip;
     BiosFrame.Prefix = 0;
-    
+
     /* Convert CS to linear */
     BiosFrame.CsBase = BiosFrame.SegCs << 4;
     BiosFrame.CsLimit = 0xFFFF;
     BiosFrame.CsFlags = 0;
-    
+
     /* Validate IP */
     if (BiosFrame.Eip > BiosFrame.CsLimit) return FALSE;
-    
+
     /* Read IP */
     Instruction = *(PUCHAR)(BiosFrame.CsBase + BiosFrame.Eip);
     if (Instruction != 0xCD)
@@ -184,17 +184,17 @@ HalpDispatchV86Opcode(IN PKTRAP_FRAME TrapFrame)
         HalpOpcodeInvalid(&BiosFrame);
         return FALSE;
     }
-    
+
     /* Handle the interrupt */
     if (HalpOpcodeINTnn(&BiosFrame))
     {
         /* Update EIP */
         TrapFrame->Eip = BiosFrame.Eip;
-        
+
         /* We're done */
         return TRUE;
     }
-    
+
     /* Failure */
     return FALSE;
 }
@@ -209,7 +209,7 @@ HalpTrap0DHandler(IN PKTRAP_FRAME TrapFrame)
 {
     /* Enter the trap */
     KiEnterTrap(TrapFrame);
-    
+
     /* Check if this is a V86 trap */
     if (TrapFrame->EFlags & EFLAGS_V86_MASK)
     {
@@ -217,7 +217,7 @@ HalpTrap0DHandler(IN PKTRAP_FRAME TrapFrame)
         HalpDispatchV86Opcode(TrapFrame);
         KiEoiHelper(TrapFrame);
     }
-    
+
     /* Strange, it isn't! This can happen during NMI */
     DPRINT1("HAL: Trap0D while not in V86 mode\n");
     KiDumpTrapFrame(TrapFrame);
@@ -235,7 +235,7 @@ HalpTrap06(VOID)
     Ke386SetDs(KGDT_R3_DATA | RPL_MASK);
     Ke386SetFs(KGDT_R0_PCR);
 
-    /* Restore the stack */ 
+    /* Restore the stack */
     KeGetPcr()->TSS->Esp0 = HalpSavedEsp0;
 
     /* Return back to where we left */
@@ -252,24 +252,24 @@ HalpBiosCall(VOID)
     /* Must be volatile so it doesn't get optimized away! */
     volatile KTRAP_FRAME V86TrapFrame;
     ULONG_PTR StackOffset, CodeOffset;
-    
+
     /* Save the context, check for return */
     if (_setjmp(HalpSavedContext))
     {
         /* Returned from v86 */
         return;
     }
-    
+
     /* Kill alignment faults */
     __writecr0(__readcr0() & ~CR0_AM);
-    
+
     /* Set new stack address */
     KeGetPcr()->TSS->Esp0 = (ULONG)&V86TrapFrame - 0x20 - sizeof(FX_SAVE_AREA);
 
     /* Compute segmented IP and SP offsets */
     StackOffset = (ULONG_PTR)&HalpRealModeEnd - 4 - (ULONG_PTR)HalpRealModeStart;
     CodeOffset = (ULONG_PTR)HalpRealModeStart & 0xFFF;
-    
+
     /* Now build the V86 trap frame */
     V86TrapFrame.V86Es = 0;
     V86TrapFrame.V86Ds = 0;
@@ -280,7 +280,7 @@ HalpBiosCall(VOID)
     V86TrapFrame.EFlags = __readeflags() | EFLAGS_V86_MASK | EFLAGS_IOPL;
     V86TrapFrame.SegCs = 0x2000;
     V86TrapFrame.Eip = CodeOffset;
-    
+
     /* Exit to V86 mode */
     HalpExitToV86((PKTRAP_FRAME)&V86TrapFrame);
 }
@@ -339,7 +339,7 @@ HalpBorrowTss(VOID)
     TssGdt->HighWord.Bits.Type = I386_TSS;
     TssGdt->HighWord.Bits.Pres = 1;
     TssGdt->HighWord.Bits.Dpl = 0;
-    
+
     //
     // Load new TSS and return old one
     //
@@ -353,7 +353,7 @@ HalpReturnTss(VOID)
 {
     PKGDTENTRY TssGdt;
     PKTSS TssBase;
-    
+
     //
     // Get the original TSS
     //
@@ -497,7 +497,7 @@ HalpMapRealModeMemory(VOID)
         // Map the physical address into our real-mode region
         //
         Pte->PageFrameNumber = V86Pte->PageFrameNumber;
-        
+
         //
         // Keep going until we've reached the end of our region
         //
@@ -557,7 +557,7 @@ HalpSetupRealModeIoPermissionsAndTask(VOID)
     //
     // Save our stack pointer
     //
-    HalpSavedEsp0 = KeGetPcr()->TSS->Esp0; 
+    HalpSavedEsp0 = KeGetPcr()->TSS->Esp0;
 }
 
 VOID
@@ -661,7 +661,7 @@ HalpBiosDisplayReset(VOID)
     //
     HalpMapRealModeMemory();
 
-    // 
+    //
     // On P5, the first 7 entries of the IDT are write protected to work around
     // the cmpxchg8b lock errata. Unprotect them here so we can set our custom
     // invalid op-code handler.
@@ -699,7 +699,7 @@ HalpBiosDisplayReset(VOID)
     // Restore TSS and IOPM
     //
     HalpRestoreIoPermissionsAndTask();
-    
+
     //
     // Restore low memory mapping
     //