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reactos/hal/halx86/apic/tsccal.S

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[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
#include <asm.inc>
#include "tsc.h"
.code
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
#ifdef _M_IX86
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
EXTERN _TscCalibrationPhase:BYTE
EXTERN _TscCalibrationArray:QWORD
[HAL] - Fix I/O APIC register access - set APIC logical id based on Cpu (currently flat model with up to 8 cpus supported) - In HalpInitializeTsc, setup the RTC clock, since the timer is initialized later - in the TSC calibration ISR, send EOI and read RTC register C to get the next interrupt svn path=/trunk/; revision=53634
2011-09-08 08:15:39 +00:00
EXTERN _HalpSendEOI@0:PROC
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
PUBLIC _TscCalibrationISR
_TscCalibrationISR:
push eax
push ecx
push edx
/* The first thing we do is read the current TSC value */
rdtsc
/* Read the current phase */
movzx ecx, byte ptr ds:[_TscCalibrationPhase]
/* Check if we're already done */
cmp cl, NUM_SAMPLES
jnb _CalibrationISR_Exit
/* Store the current value */
[HAL] - Fix I/O APIC register access - set APIC logical id based on Cpu (currently flat model with up to 8 cpus supported) - In HalpInitializeTsc, setup the RTC clock, since the timer is initialized later - in the TSC calibration ISR, send EOI and read RTC register C to get the next interrupt svn path=/trunk/; revision=53634
2011-09-08 08:15:39 +00:00
shl ecx, 3
mov dword ptr _TscCalibrationArray[ecx], eax
mov dword ptr _TscCalibrationArray[ecx + 4], edx
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
/* Advance phase */
inc byte ptr ds:[_TscCalibrationPhase]
_CalibrationISR_Exit:
[HAL] - Fix I/O APIC register access - set APIC logical id based on Cpu (currently flat model with up to 8 cpus supported) - In HalpInitializeTsc, setup the RTC clock, since the timer is initialized later - in the TSC calibration ISR, send EOI and read RTC register C to get the next interrupt svn path=/trunk/; revision=53634
2011-09-08 08:15:39 +00:00
/* Read CMOS register C */
mov al, HEX(0C)
out HEX(70), al
jmp $+2
in al, HEX(71)
jmp $+2
/* Send EOI */
call _HalpSendEOI@0
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
pop edx
pop ecx
pop eax
iretd
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
#else
EXTERN TscCalibrationPhase:BYTE
EXTERN TscCalibrationArray:DWORD
[HAL/APIC/AMD64] - add common amd64 asm trap macros - fix amd64 version of HackEoi - send EOI in amd64 trap exit code, so we avoid using HackEoi - modify HalpClockInterruptHandler for better portability - fix amd64 TscCalibrationISR svn path=/trunk/; revision=53719
2011-09-16 09:39:41 +00:00
EXTERN HalpSendEOI:PROC
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
PUBLIC TscCalibrationISR
FUNC TscCalibrationISR
push rax
[HAL/APIC/AMD64] - add common amd64 asm trap macros - fix amd64 version of HackEoi - send EOI in amd64 trap exit code, so we avoid using HackEoi - modify HalpClockInterruptHandler for better portability - fix amd64 TscCalibrationISR svn path=/trunk/; revision=53719
2011-09-16 09:39:41 +00:00
push rbx
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
push rcx
push rdx
.ENDPROLOG
/* The first thing we do is read the current TSC value */
rdtsc
/* Read the current phase */
[HALX86] Use addressing relative to RIP
2021-04-21 17:46:59 +00:00
movzx rcx, byte ptr [rip+TscCalibrationPhase]
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
/* Check if we're already done */
cmp cl, NUM_SAMPLES
jnb CalibrationISR_Exit
/* Store the current value */
[HAL/APIC/AMD64] - add common amd64 asm trap macros - fix amd64 version of HackEoi - send EOI in amd64 trap exit code, so we avoid using HackEoi - modify HalpClockInterruptHandler for better portability - fix amd64 TscCalibrationISR svn path=/trunk/; revision=53719
2011-09-16 09:39:41 +00:00
shl rcx, 3
[HALX86] Use addressing relative to RIP
2021-04-21 17:46:59 +00:00
lea rbx, [rip+TscCalibrationArray]
[HAL/APIC/AMD64] - add common amd64 asm trap macros - fix amd64 version of HackEoi - send EOI in amd64 trap exit code, so we avoid using HackEoi - modify HalpClockInterruptHandler for better portability - fix amd64 TscCalibrationISR svn path=/trunk/; revision=53719
2011-09-16 09:39:41 +00:00
mov dword ptr [rbx + rcx], eax
mov dword ptr [rbx + rcx + 4], edx
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
/* Advance phase */
[HALX86] Use addressing relative to RIP
2021-04-21 17:46:59 +00:00
inc byte ptr [rip+TscCalibrationPhase]
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
CalibrationISR_Exit:
[HAL/APIC/AMD64] - add common amd64 asm trap macros - fix amd64 version of HackEoi - send EOI in amd64 trap exit code, so we avoid using HackEoi - modify HalpClockInterruptHandler for better portability - fix amd64 TscCalibrationISR svn path=/trunk/; revision=53719
2011-09-16 09:39:41 +00:00
/* Read CMOS register C */
mov al, HEX(0C)
out HEX(70), al
jmp $+2
in al, HEX(71)
jmp $+2
/* Send EOI */
call HalpSendEOI
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
pop rdx
pop rcx
[HAL/APIC/AMD64] - add common amd64 asm trap macros - fix amd64 version of HackEoi - send EOI in amd64 trap exit code, so we avoid using HackEoi - modify HalpClockInterruptHandler for better portability - fix amd64 TscCalibrationISR svn path=/trunk/; revision=53719
2011-09-16 09:39:41 +00:00
pop rbx
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
pop rax
iretq
[ASM] Improve .proc / .endproc syntax, so that the full symbolic name is passed, which allows to create fastcall symbols. Remove the need to pass the function name to .endp svn path=/trunk/; revision=54112
2011-10-13 15:16:29 +00:00
ENDFUNC
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631
2011-09-07 21:41:50 +00:00
#endif
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611
2011-09-06 21:01:49 +00:00
END
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