2008-02-12 05:55:12 +00:00
|
|
|
|
|
|
|
|
.macro TEXTAREA
|
2010-11-23 16:33:29 +00:00
|
|
|
.section .text, "rx"
|
2008-02-12 05:55:12 +00:00
|
|
|
.align 2
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro NESTED_ENTRY Name
|
|
|
|
|
.global &Name
|
|
|
|
|
.align 2
|
|
|
|
|
.func &Name
|
|
|
|
|
&Name:
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro PROLOG_END Name
|
|
|
|
|
prolog_&Name:
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro ENTRY_END Name
|
|
|
|
|
end_&Name:
|
|
|
|
|
.endfunc
|
|
|
|
|
.endm
|
- Rewrite the low-level trap/exception/system call code from the ground up:
- Do not corrupt the stack anymore
- Use a consistent trap frame layout (enable OldIrql and PreviousMode, and set the 0xBADB0D00 debug mark)
- Use slower but more correct trap prolog/epilog code for now.
- Generalize all prolog/epilog code into macros just like on x86. As a result, traps are now 6 lines of code.
- Rewrite the system call interface from the ground up:
- System calls didn't actually work: a debug print made the stack layout magical enough so that they didn't normally crush, but only slowly ate the stack.
- Copying arguments from caller to system call was, as the comment on the original code so aptly put it, "total shit".
- Due to ABI concerns, and to provide an actual template on how you're -supposed- to implement something like system calls on RISC processors, we now use
a model similar to BSD, but about ten times better (with that much less code too). We'll document it later on the RosPSG Wiki.
- This code probably contains some of the most vile-yet-elegant macro magic ever written for such low-level code as system call dispatching.
- The result of all this is that we're at the same place as before (RamdiskAddDevice needs to be implemented by the Ramdisk guys) but with a sane low-level
backend that isn't slowly eating away the stack, corrupting data, and basically working through random chance.
- Move timebase code from stubs.c to its own file, time.c.
- Silence multiple debug prints and fix a corrupted debug print in KiSystemStartup.
svn path=/trunk/; revision=34366
2008-07-08 09:11:44 +00:00
|
|
|
|
|
|
|
|
.macro TRAP_PROLOG Abort
|
|
|
|
|
//
|
|
|
|
|
// Fixup lr
|
|
|
|
|
//
|
|
|
|
|
.if \Abort
|
|
|
|
|
sub lr, lr, #8
|
|
|
|
|
.else
|
|
|
|
|
sub lr, lr, #4
|
|
|
|
|
.endif
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Save the bottom 4 registers
|
|
|
|
|
//
|
|
|
|
|
stmdb sp, {r0-r3}
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Save the abort lr, sp, spsr, cpsr
|
|
|
|
|
//
|
|
|
|
|
mov r0, lr
|
|
|
|
|
mov r1, sp
|
|
|
|
|
mrs r2, cpsr
|
|
|
|
|
mrs r3, spsr
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Switch to SVC mode
|
|
|
|
|
//
|
|
|
|
|
bic r2, r2, #CPSR_MODES
|
|
|
|
|
orr r2, r2, #CPSR_SVC_MODE
|
|
|
|
|
msr cpsr_c, r2
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Save the SVC sp before we modify it
|
|
|
|
|
//
|
|
|
|
|
mov r2, sp
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Make space for the trap frame
|
|
|
|
|
//
|
|
|
|
|
sub sp, sp, #TrapFrameLength
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Save abt32 state
|
|
|
|
|
//
|
|
|
|
|
str r0, [sp, #TrPc]
|
|
|
|
|
str lr, [sp, #TrSvcLr]
|
|
|
|
|
str r2, [sp, #TrSvcSp]
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Restore the saved SPSR
|
|
|
|
|
//
|
|
|
|
|
msr spsr_all, r3
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Restore our 4 registers
|
|
|
|
|
//
|
|
|
|
|
ldmdb r1, {r0-r3}
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Build trap frame
|
|
|
|
|
// FIXME: Change to stmdb later
|
|
|
|
|
//
|
|
|
|
|
str r0, [sp, #TrR0]
|
|
|
|
|
str r1, [sp, #TrR1]
|
|
|
|
|
str r2, [sp, #TrR2]
|
|
|
|
|
str r3, [sp, #TrR3]
|
|
|
|
|
str r4, [sp, #TrR4]
|
|
|
|
|
str r5, [sp, #TrR5]
|
|
|
|
|
str r6, [sp, #TrR6]
|
|
|
|
|
str r7, [sp, #TrR7]
|
|
|
|
|
str r8, [sp, #TrR8]
|
|
|
|
|
str r9, [sp, #TrR9]
|
|
|
|
|
str r10, [sp, #TrR10]
|
|
|
|
|
str r11, [sp, #TrR11]
|
|
|
|
|
str r12, [sp, #TrR12]
|
|
|
|
|
mov r12, sp
|
|
|
|
|
add r12, r12, #TrUserSp
|
|
|
|
|
stm r12, {sp, lr}^
|
|
|
|
|
mrs r0, spsr_all
|
|
|
|
|
str r0, [sp, #TrSpsr]
|
|
|
|
|
ldr r0, =0xBADB0D00
|
|
|
|
|
str r0, [sp, #TrDbgArgMark]
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro SYSCALL_PROLOG
|
|
|
|
|
//
|
|
|
|
|
// Make space for the trap frame
|
|
|
|
|
//
|
|
|
|
|
sub sp, sp, #TrapFrameLength
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Build trap frame
|
|
|
|
|
// FIXME: Change to stmdb later
|
|
|
|
|
//
|
|
|
|
|
str r0, [sp, #TrR0]
|
|
|
|
|
str r1, [sp, #TrR1]
|
|
|
|
|
str r2, [sp, #TrR2]
|
|
|
|
|
str r3, [sp, #TrR3]
|
|
|
|
|
str r4, [sp, #TrR4]
|
|
|
|
|
str r5, [sp, #TrR5]
|
|
|
|
|
str r6, [sp, #TrR6]
|
|
|
|
|
str r7, [sp, #TrR7]
|
|
|
|
|
str r8, [sp, #TrR8]
|
|
|
|
|
str r9, [sp, #TrR9]
|
|
|
|
|
str r10, [sp, #TrR10]
|
|
|
|
|
str r11, [sp, #TrR11]
|
|
|
|
|
str r12, [sp, #TrR12]
|
|
|
|
|
mov r12, sp
|
|
|
|
|
add r12, r12, #TrUserSp
|
|
|
|
|
stm r12, {sp, lr}^
|
|
|
|
|
str sp, [sp, #TrSvcSp]
|
|
|
|
|
str lr, [sp, #TrPc]
|
|
|
|
|
mrs r0, spsr_all
|
|
|
|
|
str r0, [sp, #TrSpsr]
|
|
|
|
|
ldr r0, =0xBADB0D00
|
|
|
|
|
str r0, [sp, #TrDbgArgMark]
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro TRAP_EPILOG SystemCall
|
|
|
|
|
//
|
|
|
|
|
// ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00)
|
|
|
|
|
//
|
|
|
|
|
ldr r0, [sp, #TrDbgArgMark]
|
|
|
|
|
ldr r1, =0xBADB0D00
|
|
|
|
|
cmp r0, r1
|
|
|
|
|
bne 1f
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Get the SPSR and restore it
|
|
|
|
|
//
|
|
|
|
|
ldr r0, [sp, #TrSpsr]
|
|
|
|
|
msr spsr_all, r0
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Restore the registers
|
|
|
|
|
// FIXME: Use LDMIA later
|
|
|
|
|
//
|
|
|
|
|
mov r0, sp
|
|
|
|
|
add r0, r0, #TrUserSp
|
|
|
|
|
ldm r0, {sp, lr}^
|
|
|
|
|
ldr r0, [sp, #TrR0]
|
|
|
|
|
ldr r1, [sp, #TrR1]
|
|
|
|
|
ldr r2, [sp, #TrR2]
|
|
|
|
|
ldr r3, [sp, #TrR3]
|
|
|
|
|
ldr r4, [sp, #TrR4]
|
|
|
|
|
ldr r5, [sp, #TrR5]
|
|
|
|
|
ldr r6, [sp, #TrR6]
|
|
|
|
|
ldr r7, [sp, #TrR7]
|
|
|
|
|
ldr r8, [sp, #TrR8]
|
|
|
|
|
ldr r9, [sp, #TrR9]
|
|
|
|
|
ldr r10, [sp, #TrR10]
|
|
|
|
|
ldr r11, [sp, #TrR11]
|
|
|
|
|
ldr r12, [sp, #TrR12]
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Restore program execution state
|
|
|
|
|
//
|
|
|
|
|
.if \SystemCall
|
|
|
|
|
ldr lr, [sp, #TrPc]
|
|
|
|
|
add sp, sp, #TrapFrameLength
|
|
|
|
|
movs pc, lr
|
|
|
|
|
.else
|
|
|
|
|
add sp, sp, #TrSvcSp
|
|
|
|
|
ldmia sp, {sp, lr, pc}^
|
|
|
|
|
.endif
|
|
|
|
|
1:
|
|
|
|
|
b .
|
|
|
|
|
.endm
|