2011-05-22 19:36:13 +00:00
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#pragma once
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#include <ntddk.h>
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//
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// OHCI Operational Registers
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//
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#define OHCI_REVISION_OFFSET (0x00)
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#define OHCI_REVISION_LOW(rev) ((rev) & 0x0f)
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#define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03)
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//
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// OHCI Control Register
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//
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#define OHCI_CONTROL_OFFSET (0x004)
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#define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK (0x003)
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#define OHCI_CONTROL_BULK_RATIO_1_1 (0x000)
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#define OHCI_CONTROL_BULK_RATIO_1_2 (0x001)
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#define OHCI_CONTROL_BULK_RATIO_1_3 (0x002)
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#define OHCI_CONTROL_BULK_RATIO_1_4 (0x003)
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#define OHCI_PERIODIC_LIST_ENABLE (0x004)
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#define OHCI_ISOCHRONOUS_ENABLE (0x008)
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#define OHCI_CONTROL_LIST_ENABLE (0x010)
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#define OHCI_BULK_LIST_ENABLE (0x020)
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#define OHCI_HC_FUNCTIONAL_STATE_MASK (0x0C0)
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#define OHCI_HC_FUNCTIONAL_STATE_RESET (0x000)
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#define OHCI_HC_FUNCTIONAL_STATE_RESUME (0x040)
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#define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL (0x080)
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#define OHCI_HC_FUNCTIONAL_STATE_SUSPEND (0x0c0)
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#define OHCI_INTERRUPT_ROUTING (0x100)
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#define OHCI_REMOTE_WAKEUP_CONNECTED (0x200)
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#define OHCI_REMORE_WAKEUP_ENABLED (0x400)
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//
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// OHCI Command Status Register
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//
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#define OHCI_COMMAND_STATUS_OFFSET (0x08)
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#define OHCI_HOST_CONTROLLER_RESET 0x00000001
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#define OHCI_CONTROL_LIST_FILLED 0x00000002
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#define OHCI_BULK_LIST_FILLED 0x00000004
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#define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008
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#define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000
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//
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// OHCI Interrupt Status Register
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//
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#define OHCI_INTERRUPT_STATUS_OFFSET 0x0c
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#define OHCI_SCHEDULING_OVERRUN 0x00000001
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#define OHCI_WRITEBACK_DONE_HEAD 0x00000002
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#define OHCI_START_OF_FRAME 0x00000004
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#define OHCI_RESUME_DETECTED 0x00000008
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#define OHCI_UNRECOVERABLE_ERROR 0x00000010
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#define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020
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#define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040
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#define OHCI_OWNERSHIP_CHANGE 0x40000000
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#define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000
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//
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// OHCI Interrupt Enable Register
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//
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#define OHCI_INTERRUPT_ENABLE_OFFSET 0x10
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//
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// OHCI Interrupt Enable Register
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//
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#define OHCI_INTERRUPT_DISABLE_OFFSET 0x14
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//
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// OHCI HCCA Register
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//
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#define OHCI_HCCA_OFFSET 0x18
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#define OHCI_PERIOD_CURRENT_ED_OFFSET 0x1c
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#define OHCI_CONTROL_HEAD_ED_OFFSET 0x20
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#define OHCI_CONTROL_CURRENT_ED_OFFSET 0x24
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#define OHCI_BULK_HEAD_ED_OFFSET 0x28
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//
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// OHCI Root Hub Descriptor A register
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//
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#define OHCI_RH_DESCRIPTOR_A_OFFSET 0x48
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#define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff)
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#define OHCI_RH_POWER_SWITCHING_MODE 0x0100
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#define OHCI_RH_NO_POWER_SWITCHING 0x0200
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#define OHCI_RH_DEVICE_TYPE 0x0400
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#define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800
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#define OHCI_RH_NO_OVER_CURRENT_PROTECTION 0x1000
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#define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24)
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//
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// Root Hub Descriptor B register (section 7.4.2)
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//
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#define OHCI_RH_DESCRIPTOR_B 0x4c
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//
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// Root Hub status register (section 7.4.3)
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//
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#define OHCI_RH_STATUS 0x50
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#define OHCI_RH_LOCAL_POWER_STATUS 0x00000001
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#define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002
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#define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000
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#define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000
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#define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000
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#define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000
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//
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// Root Hub port status (n) register (section 7.4.4)
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//
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#define OHCI_RH_PORT_STATUS(n) (0x54 + (n) * 4)// 0 based indexing
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#define OHCI_RH_PORTSTATUS_CCS 0x00000001
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#define OHCI_RH_PORTSTATUS_PES 0x00000002
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#define OHCI_RH_PORTSTATUS_PSS 0x00000004
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#define OHCI_RH_PORTSTATUS_POCI 0x00000008
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#define OHCI_RH_PORTSTATUS_PRS 0x00000010
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#define OHCI_RH_PORTSTATUS_PPS 0x00000100
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#define OHCI_RH_PORTSTATUS_LSDA 0x00000200
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#define OHCI_RH_PORTSTATUS_CSC 0x00010000
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#define OHCI_RH_PORTSTATUS_PESC 0x00020000
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#define OHCI_RH_PORTSTATUS_PSSC 0x00040000
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#define OHCI_RH_PORTSTATUS_OCIC 0x00080000
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#define OHCI_RH_PORTSTATUS_PRSC 0x00100000
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//
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// Enable List
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//
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#define OHCI_ENABLE_LIST (OHCI_PERIODIC_LIST_ENABLE \
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| OHCI_ISOCHRONOUS_ENABLE \
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| OHCI_CONTROL_LIST_ENABLE \
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| OHCI_BULK_LIST_ENABLE)
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//
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// All interupts
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//
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#define OHCI_ALL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
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| OHCI_WRITEBACK_DONE_HEAD \
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| OHCI_START_OF_FRAME \
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| OHCI_RESUME_DETECTED \
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| OHCI_UNRECOVERABLE_ERROR \
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| OHCI_FRAME_NUMBER_OVERFLOW \
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| OHCI_ROOT_HUB_STATUS_CHANGE \
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| OHCI_OWNERSHIP_CHANGE)
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//
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// All normal interupts
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//
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#define OHCI_NORMAL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
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| OHCI_WRITEBACK_DONE_HEAD \
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| OHCI_RESUME_DETECTED \
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| OHCI_UNRECOVERABLE_ERROR \
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| OHCI_ROOT_HUB_STATUS_CHANGE)
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//
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// FSMPS
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//
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#define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16)
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//
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// Periodic
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//
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#define OHCI_PERIODIC(i) ((i) * 9 / 10)
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// --------------------------------
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// HCCA structure (section 4.4)
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// 256 bytes aligned
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// --------------------------------
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#define OHCI_NUMBER_OF_INTERRUPTS 32
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#define OHCI_STATIC_ENDPOINT_COUNT 6
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#define OHCI_BIGGEST_INTERVAL 32
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typedef struct
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{
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ULONG InterruptTable[OHCI_NUMBER_OF_INTERRUPTS];
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ULONG CurrentFrameNumber;
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ULONG DoneHead;
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UCHAR Reserved[120];
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}OHCIHCCA, *POHCIHCCA;
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#define OHCI_DONE_INTERRUPTS 1
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#define OHCI_HCCA_SIZE 256
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#define OHCI_HCCA_ALIGN 256
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#define OHCI_PAGE_SIZE 0x1000
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#define OHCI_PAGE(x) ((x) &~ 0xfff)
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#define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
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typedef struct
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{
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// Hardware part
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ULONG Flags;
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ULONG TailPhysicalDescriptor;
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ULONG HeadPhysicalDescriptor;
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ULONG NextPhysicalEndpoint;
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// Software part
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PHYSICAL_ADDRESS PhysicalAddress;
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}OHCI_ENDPOINT_DESCRIPTOR, *POHCI_ENDPOINT_DESCRIPTOR;
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#define OHCI_ENDPOINT_SKIP 0x00004000
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//
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// Maximum port count set by OHCI
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//
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2011-05-23 11:29:55 +00:00
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#define OHCI_MAX_PORT_COUNT 15
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typedef struct
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{
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ULONG PortStatus;
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ULONG PortChange;
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}OHCI_PORT_STATUS;
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typedef struct {
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// Hardware part 16 bytes
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uint32 flags; // Flags field
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uint32 buffer_physical; // Physical buffer pointer
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uint32 next_physical_descriptor; // Physical pointer next descriptor
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uint32 last_physical_byte_address; // Physical pointer to buffer end
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// Software part
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addr_t physical_address; // Physical address of this descriptor
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size_t buffer_size; // Size of the buffer
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void *buffer_logical; // Logical pointer to the buffer
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void *next_logical_descriptor; // Logical pointer next descriptor
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} ohci_general_td;
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