reactos/hal/halx86/apic/tsc.h


#ifndef _TSC_H_
#define _TSC_H_

#define NUM_SAMPLES 4
#define MSR_RDTSC 0x10

#ifndef __ASM__

void __cdecl TscCalibrationISR(void);
extern LARGE_INTEGER HalpCpuClockFrequency;
VOID NTAPI HalpInitializeTsc(void);

#ifdef _M_AMD64
#define KiGetIdtEntry(Pcr, Vector) &((Pcr)->IdtBase[Vector])
#else
#define KiGetIdtEntry(Pcr, Vector) &((Pcr)->IDT[Vector])
#endif

#endif

#endif /* !_TSC_H_ */
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611 2011-09-06 21:01:49 +00:00
[HAL] Add some header guards. 2017-12-09 12:20:22 +00:00			`#ifndef _TSC_H_`
			`#define _TSC_H_`
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611 2011-09-06 21:01:49 +00:00
			`#define NUM_SAMPLES 4`
			`#define MSR_RDTSC 0x10`

			`#ifndef __ASM__`

Sprinkle cdecl declarations liberally all around to make a bunch of the base components compile (freeldr compiles but does not link yet). Some of these should really be NTAPI, working on that. svn path=/trunk/; revision=69238 2015-09-15 10:35:49 +00:00			`void __cdecl TscCalibrationISR(void);`
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611 2011-09-06 21:01:49 +00:00			`extern LARGE_INTEGER HalpCpuClockFrequency;`
[HAL] Fix HalpInitializeTsc prototype. svn path=/trunk/; revision=69865 2015-11-10 13:19:40 +00:00			`VOID NTAPI HalpInitializeTsc(void);`
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611 2011-09-06 21:01:49 +00:00
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631 2011-09-07 21:41:50 +00:00			`#ifdef _M_AMD64`
			`#define KiGetIdtEntry(Pcr, Vector) &((Pcr)->IdtBase[Vector])`
			`#else`
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611 2011-09-06 21:01:49 +00:00			`#define KiGetIdtEntry(Pcr, Vector) &((Pcr)->IDT[Vector])`
[HAL] - Don't use debug prints before the debugger is even initialized - acquire cmos spinlock when accessing the cmos registers - Fix amd64 build svn path=/trunk/; revision=53631 2011-09-07 21:41:50 +00:00			`#endif`
[HAL] Start implementing APIC support, which is needed for both SMP and x64. It will use the local APIC + I/O APIC for interrupt control, the RTC instead of the PIT for the timer interrupt (PIT doesn't always work with I/O APIC), the APIC timer for profiling and finally the TSC for the performance counter and KeStallExecutionProcessor. The code is incomplete and doesn't work yet svn path=/trunk/; revision=53611 2011-09-06 21:01:49 +00:00
			`#endif`
[HAL] Add some header guards. 2017-12-09 12:20:22 +00:00
			`#endif /* !_TSC_H_ */`