2010-03-05 17:22:18 +00:00
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/*
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* PROJECT: ReactOS VGA Miniport Driver
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* LICENSE: Microsoft NT4 DDK Sample Code License
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2015-11-05 18:07:00 +00:00
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* FILE: win32ss/drivers/miniport/vga_new/vga.h
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2010-03-05 17:22:18 +00:00
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* PURPOSE: Main Header File
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* PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation
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* ReactOS Portable Systems Group
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*/
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2014-02-07 17:32:20 +00:00
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#ifndef _VGA_NEW_PCH_
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#define _VGA_NEW_PCH_
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2014-02-04 17:01:57 +00:00
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#include <ntdef.h>
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#include <dderror.h>
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#include <miniport.h>
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#include <video.h>
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2010-03-05 17:22:18 +00:00
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#include "cmdcnst.h"
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//
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// Base address of VGA memory range. Also used as base address of VGA
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// memory when loading a font, which is done with the VGA mapped at A0000.
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//
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#define MEM_VGA 0xA0000
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#define MEM_VGA_SIZE 0x20000
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//
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// For memory mapped IO
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//
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#define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000)
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//
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// Port definitions for filling the ACCESS_RANGES structure in the miniport
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// information, defines the range of I/O ports the VGA spans.
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// There is a break in the IO ports - a few ports are used for the parallel
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// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
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// so all VGA ports are in one address range.
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//
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#define VGA_BASE_IO_PORT 0x000003B0
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#define VGA_START_BREAK_PORT 0x000003BB
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#define VGA_END_BREAK_PORT 0x000003C0
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#define VGA_MAX_IO_PORT 0x000003DF
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//
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// VGA register definitions
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//
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// eVb: 3.1 [VGA] - Use offsets from the VGA Port Address instead of absolute
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#define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
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#define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
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#define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
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// in mono mode
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#define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
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// port in mono mode
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#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
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// Register to read to reset
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// Attribute Controller index/data
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#define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
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#define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
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// for writes, but only Address is
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// readable at 0x3C0
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#define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
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// readable here
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#define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
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// port
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#define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
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// port
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#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
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// entire VGA subsystem
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#define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
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#define SEQ_DATA_PORT 0x0015 // Data registers
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#define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
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#define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
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// write-only
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#define DAC_STATE_PORT 0x0017 // DAC state (read/write),
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// read-only
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#define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
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#define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
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#define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
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// port
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#define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
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#define GRAPH_DATA_PORT 0x001F // and Data registers
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#define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
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#define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
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#define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
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#define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
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// port in color mode
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// eVb: 3.2 [END]
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#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in color mode
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//
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// Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
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// VGA registers.
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//
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#define CRTC_ADDRESS_MONO_OFFSET 0x04
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#define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
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#define ATT_ADDRESS_OFFSET 0x10
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#define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
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#define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
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#define SEQ_ADDRESS_OFFSET 0x14
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#define DAC_PIXEL_MASK_OFFSET 0x16
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#define DAC_STATE_OFFSET 0x17
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#define DAC_ADDRESS_WRITE_OFFSET 0x18
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#define GRAPH_ADDRESS_OFFSET 0x1E
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#define CRTC_ADDRESS_COLOR_OFFSET 0x24
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#define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
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//
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// VGA indexed register indexes.
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//
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// CL-GD542x specific registers:
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//
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#define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
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#define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad
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#define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad
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#define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad
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#define IND_CL_REV_REG 0x25 // index in CRTC of ID Register
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#define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
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//
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#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
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#define IND_CURSOR_END 0x0B // and End registers
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#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
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#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
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#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
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// End register, which has the bit
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// that protects/unprotects CRTC
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// index registers 0-7
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#define IND_CR2C 0x2C // Nordic LCD Interface Register
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#define IND_CR2D 0x2D // Nordic LCD Display Control
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#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
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#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
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#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
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#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
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#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
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#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
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#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
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#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
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#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
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#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
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// CRTC
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#define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
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// in CRTC
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#define IND_PERF_TUNING 0x16 // index of performance tuning in Seq
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#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
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// synchronous reset
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#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
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// synchronous reset
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//
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// Value to write to Extensions Control register values extensions.
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//
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#define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact!
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#define CL64xx_EXTENSION_ENABLE_VALUE 0xEC
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#define CL64xx_EXTENSION_DISABLE_VALUE 0xCE
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#define CL64xx_TRISTATE_CONTROL_REG 0xA1
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#define CL6340_ENABLE_READBACK_REGISTER 0xE0
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#define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0
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#define CL6340_ENABLE_READBACK_OFF_VALUE 0x00
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#define CL6340_IDENTIFICATION_REGISTER 0xE9
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//
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// Values for Attribute Controller Index register to turn video off
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// and on, by setting bit 5 to 0 (off) or 1 (on).
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//
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#define VIDEO_DISABLE 0
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#define VIDEO_ENABLE 0x20
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#define INDEX_ENABLE_AUTO_START 0x31
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// Masks to keep only the significant bits of the Graphics Controller and
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// Sequencer Address registers. Masking is necessary because some VGAs, such
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// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
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// these bits if extensions are enabled.
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//
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#define GRAPH_ADDR_MASK 0x0F
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#define SEQ_ADDR_MASK 0x07
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//
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// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
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//
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#define CHAIN4_MASK 0x08
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//
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// Value written to the Read Map register when identifying the existence of
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// a VGA in VgaInitialize. This value must be different from the final test
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// value written to the Bit Mask in that routine.
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//
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#define READ_MAP_TEST_SETTING 0x03
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//
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// Default text mode setting for various registers, used to restore their
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// states if VGA detection fails after they've been modified.
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//
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#define MEMORY_MODE_TEXT_DEFAULT 0x02
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#define BIT_MASK_DEFAULT 0xFF
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#define READ_MAP_DEFAULT 0x00
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//
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// Palette-related info.
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//
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//
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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//
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// Highest valid palette register index
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//
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#define VIDEO_MAX_PALETTE_REGISTER 0x0F
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//
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// Driver Specific Attribute Flags
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//
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#define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to
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// the blt engine.
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#define CAPS_SW_POINTER 0x00000004 // Use software pointer.
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#define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers.
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#define CAPS_MM_IO 0x00000010 // Use memory mapped IO.
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#define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported
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#define CAPS_IS_542x 0x00000040 // This is a 542x
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#define CAPS_IS_5436 0x00000080 // This is a 5436
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#define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel,
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// but 6x4 resolution
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//
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// Structure used to describe each video mode in ModesVGA[].
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//
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typedef struct {
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USHORT fbType; // color or monochrome, text or graphics, via
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// VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
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USHORT numPlanes; // # of video memory planes
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USHORT bitsPerPlane; // # of bits of color in each plane
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SHORT col; // # of text columns across screen with default font
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SHORT row; // # of text rows down screen with default font
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USHORT hres; // # of pixels across screen
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USHORT vres; // # of scan lines down screen
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// eVb: 3.2 [VGA] - Store frequency next to resolution data
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ULONG Frequency; // Vertical Frequency
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// eVb: 3.2 [END]
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USHORT wbytes; // # of bytes from start of one scan line to start of next
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ULONG sbytes; // total size of addressable display memory in bytes
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// eVb: 3.3 [VBE] - Add VBE mode and bank flag
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ULONG NoBankSwitch;
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ULONG Mode;
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// eVb: 3.3 [VBE]
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PUSHORT CmdStream; // pointer to array of register-setting commands to
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// set up mode
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2010-12-21 21:55:29 +00:00
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// eVb: 3.4 [VBE] - Add fields to track linear addresses/sizes and flags
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2010-03-05 17:22:18 +00:00
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ULONG PhysBase;
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ULONG FrameBufferBase;
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ULONG FrameBufferSize;
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ULONG PhysSize;
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ULONG LogicalWidth;
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ULONG NonVgaMode;
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ULONG Granularity;
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// eVb: 3.4 [END]
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} VIDEOMODE, *PVIDEOMODE;
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//
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// Mode into which to put the VGA before starting a VDM, so it's a plain
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// vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
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// 80x25 text mode.)
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//
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#define DEFAULT_MODE 0
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//
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// Info used by the Validator functions and save/restore code.
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// Structure used to trap register accesses that must be done atomically.
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//
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#define VGA_MAX_VALIDATOR_DATA 100
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#define VGA_VALIDATOR_UCHAR_ACCESS 1
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#define VGA_VALIDATOR_USHORT_ACCESS 2
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#define VGA_VALIDATOR_ULONG_ACCESS 3
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typedef struct _VGA_VALIDATOR_DATA {
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ULONG Port;
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UCHAR AccessType;
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ULONG Data;
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} VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
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//
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// Number of bytes to save in each plane.
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//
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#define VGA_PLANE_SIZE 0x10000
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//
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// Number of each type of indexed register in a standard VGA, used by
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// validator and state save/restore functions.
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//
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// Note: VDMs currently only support basic VGAs only.
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//
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#define VGA_NUM_SEQUENCER_PORTS 5
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#define VGA_NUM_CRTC_PORTS 25
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#define VGA_NUM_GRAPH_CONT_PORTS 9
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#define VGA_NUM_ATTRIB_CONT_PORTS 21
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#define VGA_NUM_DAC_ENTRIES 256
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#define EXT_NUM_GRAPH_CONT_PORTS 0
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#define EXT_NUM_SEQUENCER_PORTS 0
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#define EXT_NUM_CRTC_PORTS 0
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#define EXT_NUM_ATTRIB_CONT_PORTS 0
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#define EXT_NUM_DAC_ENTRIES 0
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//
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// These constants determine the offsets within the
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// VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
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// restore the VGA's state.
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//
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#define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
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#define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
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#define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
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VGA_NUM_SEQUENCER_PORTS)
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#define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
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VGA_NUM_CRTC_PORTS)
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#define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
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VGA_NUM_GRAPH_CONT_PORTS)
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#define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
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VGA_NUM_ATTRIB_CONT_PORTS)
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#define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
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(3 * VGA_NUM_DAC_ENTRIES))
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#define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
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#define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
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EXT_NUM_SEQUENCER_PORTS)
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#define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
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EXT_NUM_CRTC_PORTS)
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#define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
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EXT_NUM_GRAPH_CONT_PORTS)
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#define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
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EXT_NUM_ATTRIB_CONT_PORTS)
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#define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
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#define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
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sizeof (VGA_VALIDATOR_DATA)) + \
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sizeof (ULONG) + \
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sizeof (ULONG) + \
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sizeof (PVIDEO_ACCESS_RANGE)
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#define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
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#define VGA_MISC_DATA_AREA_SIZE 0
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#define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
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#define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
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#define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
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#define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
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//
|
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|
|
// Space needed to store all state data.
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|
//
|
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#define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
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|
//
|
|
|
|
|
// Device extension for the driver object. This data is only used
|
|
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|
|
// locally, so this structure can be added to as needed.
|
|
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|
|
//
|
|
|
|
|
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|
|
|
typedef struct _HW_DEVICE_EXTENSION {
|
|
|
|
|
|
|
|
|
|
PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
|
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|
|
|
PHYSICAL_ADDRESS PhysicalFrameOffset; // physical memory address and
|
|
|
|
|
ULONG PhysicalVideoMemoryLength; // length of display memory
|
|
|
|
|
ULONG PhysicalFrameLength; // length of display memory for
|
|
|
|
|
// the current mode.
|
|
|
|
|
|
|
|
|
|
PUCHAR IOAddress; // base I/O address of VGA ports
|
|
|
|
|
PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory
|
|
|
|
|
ULONG ModeIndex; // index of current mode in ModesVGA[]
|
|
|
|
|
PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
|
|
|
|
|
// current mode
|
|
|
|
|
|
|
|
|
|
VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
|
|
|
|
|
|
|
|
|
|
UCHAR CursorEnable; // whether cursor is enabled or not
|
|
|
|
|
UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
|
|
|
|
|
UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
|
2010-12-21 21:55:29 +00:00
|
|
|
|
// eVb: 3.5 [VBE] - Add fields for VBE support and XP+ INT10 interface
|
2010-03-05 17:22:18 +00:00
|
|
|
|
VIDEO_PORT_INT10_INTERFACE Int10Interface;
|
|
|
|
|
BOOLEAN VesaBiosOk;
|
|
|
|
|
// eVb: 3.5 [END]
|
|
|
|
|
} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Function prototypes.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Vga init scripts for font loading
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
extern USHORT EnableA000Data[];
|
|
|
|
|
extern USHORT DisableA000Color[];
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Mode Information
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
extern ULONG NumVideoModes;
|
|
|
|
|
extern VIDEOMODE ModesVGA[];
|
|
|
|
|
extern PVIDEOMODE VgaModeList;
|
|
|
|
|
|
2010-12-21 21:55:29 +00:00
|
|
|
|
// eVb: 3.5 [VGA] - Add ATI/Mach64 Access Range
|
2010-03-05 17:22:18 +00:00
|
|
|
|
#define NUM_VGA_ACCESS_RANGES 5
|
|
|
|
|
// eVb: 3.5 [END]
|
|
|
|
|
extern VIDEO_ACCESS_RANGE VgaAccessRange[];
|
|
|
|
|
|
2010-12-21 21:55:29 +00:00
|
|
|
|
/* VESA Bios Magic number */
|
|
|
|
|
#define VESA_MAGIC ('V' + ('E' << 8) + ('S' << 16) + ('A' << 24))
|
|
|
|
|
|
2010-03-05 17:22:18 +00:00
|
|
|
|
#include "vbe.h"
|
2014-02-07 17:32:20 +00:00
|
|
|
|
|
|
|
|
|
#endif /* _VGA_NEW_PCH_ */
|