2018-09-08 08:12:39 +00:00
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/*
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* PROJECT: ReactOS USB OHCI Miniport Driver
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* LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
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* PURPOSE: USBOHCI hardware declarations
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* COPYRIGHT: Copyright 2017-2018 Vadim Galyant <vgal@rambler.ru>
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*/
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2018-01-12 20:09:58 +00:00
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#define OHCI_NUMBER_OF_INTERRUPTS 32
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#define OHCI_MAX_PORT_COUNT 15
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#define ED_EOF -1
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#define OHCI_MAXIMUM_OVERHEAD 210 // 5.4 FrameInterval Counter, in bit-times
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#define OHCI_DEFAULT_FRAME_INTERVAL 11999 // 6.3.1 Frame Timing
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#define OHCI_MINIMAL_POTPGT 25 // == 50 ms., PowerOnToPowerGoodTime (HcRhDescriptorA Register)
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/* Controller states */
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#define OHCI_HC_STATE_RESET 0
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#define OHCI_HC_STATE_RESUME 1
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#define OHCI_HC_STATE_OPERATIONAL 2
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#define OHCI_HC_STATE_SUSPEND 3
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/* Endpoint Descriptor Control */
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#define OHCI_ED_DATA_FLOW_DIRECTION_FROM_TD 0
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#define OHCI_ED_DATA_FLOW_DIRECTION_OUT 1
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#define OHCI_ED_DATA_FLOW_DIRECTION_IN 2
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#define OHCI_ENDPOINT_FULL_SPEED 0
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#define OHCI_ENDPOINT_LOW_SPEED 1
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#define OHCI_ENDPOINT_GENERAL_FORMAT 0
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#define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 1
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/* Transfer Descriptor Control */
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#define OHCI_TD_INTERRUPT_IMMEDIATE 0
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#define OHCI_TD_INTERRUPT_NONE 7
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#define OHCI_TD_DIRECTION_PID_SETUP 0
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#define OHCI_TD_DIRECTION_PID_OUT 1
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#define OHCI_TD_DIRECTION_PID_IN 2
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#define OHCI_TD_DIRECTION_PID_RESERVED 3
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#define OHCI_TD_DATA_TOGGLE_FROM_ED 0
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#define OHCI_TD_DATA_TOGGLE_DATA0 2
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#define OHCI_TD_DATA_TOGGLE_DATA1 3
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#define OHCI_TD_CONDITION_NO_ERROR 0x00
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#define OHCI_TD_CONDITION_CRC_ERROR 0x01
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#define OHCI_TD_CONDITION_BIT_STUFFING 0x02
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#define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03
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#define OHCI_TD_CONDITION_STALL 0x04
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#define OHCI_TD_CONDITION_NO_RESPONSE 0x05
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#define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06
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#define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07
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#define OHCI_TD_CONDITION_DATA_OVERRUN 0x08
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#define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09
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#define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0C
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#define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0D
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#define OHCI_TD_CONDITION_NOT_ACCESSED 0x0E
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typedef union _OHCI_TRANSFER_CONTROL {
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struct {
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ULONG Reserved : 18;
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ULONG BufferRounding : 1;
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ULONG DirectionPID : 2;
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ULONG DelayInterrupt : 3;
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ULONG DataToggle : 2;
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ULONG ErrorCount : 2;
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ULONG ConditionCode : 4;
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};
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ULONG AsULONG;
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} OHCI_TRANSFER_CONTROL, *POHCI_TRANSFER_CONTROL;
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C_ASSERT(sizeof(OHCI_TRANSFER_CONTROL) == sizeof(ULONG));
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typedef struct _OHCI_TRANSFER_DESCRIPTOR { // must be aligned to a 16-byte boundary
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OHCI_TRANSFER_CONTROL Control;
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ULONG CurrentBuffer; // physical address of the next memory location
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ULONG NextTD; // pointer to the next TD on the list of TDs
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ULONG BufferEnd; // physical address of the last byte
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} OHCI_TRANSFER_DESCRIPTOR, *POHCI_TRANSFER_DESCRIPTOR;
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C_ASSERT(sizeof(OHCI_TRANSFER_DESCRIPTOR) == 16);
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typedef union _OHCI_ISO_TRANSFER_CONTROL {
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struct {
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ULONG StartingFrame : 16;
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ULONG Reserved1 : 5;
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ULONG DelayInterrupt : 3;
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ULONG FrameCount : 3;
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ULONG Reserved2 : 1;
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ULONG ConditionCode : 4;
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};
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ULONG AsULONG;
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} OHCI_ISO_TRANSFER_CONTROL, *POHCI_ISO_TRANSFER_CONTROL;
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C_ASSERT(sizeof(OHCI_ISO_TRANSFER_CONTROL) == sizeof(ULONG));
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typedef struct _OHCI_ISO_TRANSFER_DESCRIPTOR { // must be aligned to a 32-byte boundary
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OHCI_ISO_TRANSFER_CONTROL Control;
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ULONG BufferPage0; // physical page number of the 1 byte of the data buffer
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ULONG NextTD; // pointer to the next Isochronous TD on the queue of Isochronous TDs
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ULONG BufferEnd; // physical address of the last byte in the buffer
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USHORT Offset[8]; // for determine size and start addr. iso packet | PacketStatusWord - completion code
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} OHCI_ISO_TRANSFER_DESCRIPTOR, *POHCI_ISO_TRANSFER_DESCRIPTOR;
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C_ASSERT(sizeof(OHCI_ISO_TRANSFER_DESCRIPTOR) == 32);
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typedef union _OHCI_ENDPOINT_CONTROL {
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struct {
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ULONG FunctionAddress : 7;
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ULONG EndpointNumber : 4;
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ULONG Direction : 2;
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ULONG Speed : 1;
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ULONG sKip : 1;
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ULONG Format : 1;
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ULONG MaximumPacketSize : 11;
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ULONG Reserved : 5;
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};
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ULONG AsULONG;
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} OHCI_ENDPOINT_CONTROL, *POHCI_ENDPOINT_CONTROL;
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C_ASSERT(sizeof(OHCI_ENDPOINT_CONTROL) == sizeof(ULONG));
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/* Bit flags for HeadPointer member of the EP descriptor */
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#define OHCI_ED_HEAD_POINTER_HALT 0x00000001 // hardware stopped bit
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#define OHCI_ED_HEAD_POINTER_CARRY 0x00000002 // hardware toggle carry bit
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#define OHCI_ED_HEAD_POINTER_MASK 0XFFFFFFF0 // mask physical pointer
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#define OHCI_ED_HEAD_POINTER_FLAGS_MASK 0X0000000F // mask bit flags
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typedef struct _OHCI_ENDPOINT_DESCRIPTOR { // must be aligned to a 16-byte boundary
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OHCI_ENDPOINT_CONTROL EndpointControl;
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ULONG TailPointer; // if TailP and HeadP are different, then the list contains a TD to be processed
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ULONG HeadPointer; // physical pointer to the next TD to be processed for this endpoint
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ULONG NextED; // entry points to the next ED on the list
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} OHCI_ENDPOINT_DESCRIPTOR, *POHCI_ENDPOINT_DESCRIPTOR;
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C_ASSERT(sizeof(OHCI_ENDPOINT_DESCRIPTOR) == 16);
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typedef struct _OHCI_HCCA { // must be located on a 256-byte boundary
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ULONG InterrruptTable[OHCI_NUMBER_OF_INTERRUPTS];
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USHORT FrameNumber;
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USHORT Pad1;
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ULONG DoneHead;
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UCHAR reserved_hc[116];
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UCHAR Pad[4];
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} OHCI_HCCA, *POHCI_HCCA;
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C_ASSERT(sizeof(OHCI_HCCA) == 256);
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typedef union _OHCI_REG_CONTROL {
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struct {
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ULONG ControlBulkServiceRatio : 2;
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ULONG PeriodicListEnable : 1;
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ULONG IsochronousEnable : 1;
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ULONG ControlListEnable : 1;
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ULONG BulkListEnable : 1;
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ULONG HostControllerFunctionalState : 2;
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ULONG InterruptRouting : 1;
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ULONG RemoteWakeupConnected : 1;
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ULONG RemoteWakeupEnable : 1;
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ULONG Reserved : 21;
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};
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ULONG AsULONG;
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} OHCI_REG_CONTROL, *POHCI_REG_CONTROL;
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C_ASSERT(sizeof(OHCI_REG_CONTROL) == sizeof(ULONG));
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typedef union _OHCI_REG_COMMAND_STATUS {
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struct {
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ULONG HostControllerReset : 1;
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ULONG ControlListFilled : 1;
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ULONG BulkListFilled : 1;
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ULONG OwnershipChangeRequest : 1;
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ULONG Reserved1 : 12;
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ULONG SchedulingOverrunCount : 1;
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ULONG Reserved2 : 15;
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};
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ULONG AsULONG;
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} OHCI_REG_COMMAND_STATUS, *POHCI_REG_COMMAND_STATUS;
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C_ASSERT(sizeof(OHCI_REG_COMMAND_STATUS) == sizeof(ULONG));
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typedef union _OHCI_REG_INTERRUPT_STATUS {
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struct {
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ULONG SchedulingOverrun : 1;
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ULONG WritebackDoneHead : 1;
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ULONG StartofFrame : 1;
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ULONG ResumeDetected : 1;
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ULONG UnrecoverableError : 1;
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ULONG FrameNumberOverflow : 1;
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ULONG RootHubStatusChange : 1;
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ULONG Reserved1 : 23;
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ULONG OwnershipChange : 1;
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ULONG Reserved2 : 1;
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};
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ULONG AsULONG;
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} OHCI_REG_INTERRUPT_STATUS, *POHCI_REG_INTERRUPT_STATUS;
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C_ASSERT(sizeof(OHCI_REG_INTERRUPT_STATUS) == sizeof(ULONG));
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typedef union _OHCI_REG_INTERRUPT_ENABLE_DISABLE {
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struct {
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ULONG SchedulingOverrun : 1;
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ULONG WritebackDoneHead : 1;
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ULONG StartofFrame : 1;
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ULONG ResumeDetected : 1;
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ULONG UnrecoverableError : 1;
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ULONG FrameNumberOverflow : 1;
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ULONG RootHubStatusChange : 1;
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ULONG Reserved1 : 23;
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ULONG OwnershipChange : 1;
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ULONG MasterInterruptEnable : 1;
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};
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ULONG AsULONG;
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} OHCI_REG_INTERRUPT_ENABLE_DISABLE, *POHCI_REG_INTERRUPT_ENABLE_DISABLE;
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C_ASSERT(sizeof(OHCI_REG_INTERRUPT_ENABLE_DISABLE) == sizeof(ULONG));
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typedef union _OHCI_REG_FRAME_INTERVAL {
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struct {
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ULONG FrameInterval : 14;
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ULONG Reserved : 2;
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ULONG FSLargestDataPacket : 15;
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ULONG FrameIntervalToggle : 1;
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};
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ULONG AsULONG;
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} OHCI_REG_FRAME_INTERVAL, *POHCI_REG_FRAME_INTERVAL;
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C_ASSERT(sizeof(OHCI_REG_FRAME_INTERVAL) == sizeof(ULONG));
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typedef union _OHCI_REG_RH_DESCRIPTORA {
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struct {
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ULONG NumberDownstreamPorts : 8;
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ULONG PowerSwitchingMode : 1;
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ULONG NoPowerSwitching : 1;
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ULONG DeviceType : 1;
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ULONG OverCurrentProtectionMode : 1;
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ULONG NoOverCurrentProtection : 1;
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ULONG Reserved : 11;
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ULONG PowerOnToPowerGoodTime : 8;
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};
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ULONG AsULONG;
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} OHCI_REG_RH_DESCRIPTORA, *POHCI_REG_RH_DESCRIPTORA;
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C_ASSERT(sizeof(OHCI_REG_RH_DESCRIPTORA) == sizeof(ULONG));
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typedef union _OHCI_REG_RH_STATUS {
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union {
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struct { // read
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ULONG LocalPowerStatus : 1;
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ULONG OverCurrentIndicator : 1;
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ULONG Reserved10 : 13;
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ULONG DeviceRemoteWakeupEnable : 1;
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ULONG LocalPowerStatusChange : 1;
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ULONG OverCurrentIndicatorChangeR : 1;
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ULONG Reserved20 : 14;
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};
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struct { // write
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ULONG ClearGlobalPower : 1;
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ULONG Reserved11 : 14;
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ULONG SetRemoteWakeupEnable : 1;
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ULONG SetGlobalPower : 1;
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ULONG OverCurrentIndicatorChangeW : 1;
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ULONG Reserved22 : 13;
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ULONG ClearRemoteWakeupEnable : 1;
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};
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};
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ULONG AsULONG;
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} OHCI_REG_RH_STATUS, *POHCI_REG_RH_STATUS;
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C_ASSERT(sizeof(OHCI_REG_RH_STATUS) == sizeof(ULONG));
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typedef union _OHCI_REG_RH_PORT_STATUS {
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struct {
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union {
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struct { // read
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USHORT CurrentConnectStatus : 1;
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USHORT PortEnableStatus : 1;
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USHORT PortSuspendStatus : 1;
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USHORT PortOverCurrentIndicator : 1;
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USHORT PortResetStatus : 1;
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USHORT Reserved1r : 3;
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USHORT PortPowerStatus : 1;
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USHORT LowSpeedDeviceAttached : 1;
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USHORT Reserved2r : 6;
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};
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struct { // write
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USHORT ClearPortEnable : 1;
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USHORT SetPortEnable : 1;
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USHORT SetPortSuspend : 1;
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USHORT ClearSuspendStatus : 1;
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USHORT SetPortReset : 1;
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USHORT Reserved1w : 3;
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USHORT SetPortPower : 1;
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USHORT ClearPortPower : 1;
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USHORT Reserved2w : 6;
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};
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};
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USHORT ConnectStatusChange : 1;
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USHORT PortEnableStatusChange : 1;
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USHORT PortSuspendStatusChange : 1;
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USHORT PortOverCurrentIndicatorChange : 1;
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USHORT PortResetStatusChange : 1;
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USHORT Reserved3 : 11;
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};
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ULONG AsULONG;
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} OHCI_REG_RH_PORT_STATUS, *POHCI_REG_RH_PORT_STATUS;
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C_ASSERT(sizeof(OHCI_REG_RH_PORT_STATUS) == sizeof(ULONG));
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typedef struct _OHCI_OPERATIONAL_REGISTERS {
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ULONG HcRevision;
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OHCI_REG_CONTROL HcControl;
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OHCI_REG_COMMAND_STATUS HcCommandStatus;
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OHCI_REG_INTERRUPT_STATUS HcInterruptStatus;
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OHCI_REG_INTERRUPT_ENABLE_DISABLE HcInterruptEnable;
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OHCI_REG_INTERRUPT_ENABLE_DISABLE HcInterruptDisable;
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ULONG HcHCCA;
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ULONG HcPeriodCurrentED;
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ULONG HcControlHeadED;
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ULONG HcControlCurrentED;
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ULONG HcBulkHeadED;
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ULONG HcBulkCurrentED;
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ULONG HcDoneHead;
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OHCI_REG_FRAME_INTERVAL HcFmInterval;
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ULONG HcFmRemaining;
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ULONG HcFmNumber;
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ULONG HcPeriodicStart;
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ULONG HcLSThreshold;
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OHCI_REG_RH_DESCRIPTORA HcRhDescriptorA;
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ULONG HcRhDescriptorB;
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OHCI_REG_RH_STATUS HcRhStatus;
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OHCI_REG_RH_PORT_STATUS HcRhPortStatus[OHCI_MAX_PORT_COUNT];
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} OHCI_OPERATIONAL_REGISTERS, *POHCI_OPERATIONAL_REGISTERS;
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